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Eran Libertyf046ccd2005-07-28 10:08:46 -05001/*
Dave Liu19580e62007-09-18 12:37:57 +08002 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
Eran Libertyf046ccd2005-07-28 10:08:46 -05003 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
Eran Libertyf046ccd2005-07-28 10:08:46 -050021 */
22
23#include <common.h>
24#include <mpc83xx.h>
25#include <ioports.h>
26
Wolfgang Denkd87080b2006-03-31 18:32:53 +020027DECLARE_GLOBAL_DATA_PTR;
28
Dave Liu7737d5c2006-11-03 12:11:15 -060029#ifdef CONFIG_QE
30extern qe_iop_conf_t qe_iop_conf_tab[];
31extern void qe_config_iopin(u8 port, u8 pin, int dir,
32 int open_drain, int assign);
33extern void qe_init(uint qe_base);
34extern void qe_reset(void);
35
36static void config_qe_ioports(void)
37{
38 u8 port, pin;
39 int dir, open_drain, assign;
40 int i;
41
42 for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) {
43 port = qe_iop_conf_tab[i].port;
44 pin = qe_iop_conf_tab[i].pin;
45 dir = qe_iop_conf_tab[i].dir;
46 open_drain = qe_iop_conf_tab[i].open_drain;
47 assign = qe_iop_conf_tab[i].assign;
48 qe_config_iopin(port, pin, dir, open_drain, assign);
49 }
50}
51#endif
52
Eran Libertyf046ccd2005-07-28 10:08:46 -050053/*
54 * Breathe some life into the CPU...
55 *
56 * Set up the memory map,
57 * initialize a bunch of registers,
58 * initialize the UPM's
59 */
60void cpu_init_f (volatile immap_t * im)
61{
Eran Libertyf046ccd2005-07-28 10:08:46 -050062 /* Pointer is writable since we allocated a register for it */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
Eran Libertyf046ccd2005-07-28 10:08:46 -050064
65 /* Clear initial global data */
66 memset ((void *) gd, 0, sizeof (gd_t));
67
Timur Tabi2ad6b512006-10-31 18:44:42 -060068 /* system performance tweaking */
69
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#ifdef CONFIG_SYS_ACR_PIPE_DEP
Timur Tabi2ad6b512006-10-31 18:44:42 -060071 /* Arbiter pipeline depth */
Kumar Gala4feab4d2007-02-27 23:51:42 -060072 im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073 (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT);
Timur Tabi2ad6b512006-10-31 18:44:42 -060074#endif
75
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#ifdef CONFIG_SYS_ACR_RPTCNT
Kim Phillips9e896472008-01-16 12:06:16 -060077 /* Arbiter repeat count */
78 im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079 (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT);
Kim Phillips9e896472008-01-16 12:06:16 -060080#endif
81
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#ifdef CONFIG_SYS_SPCR_OPT
Michael Barkowski5bbeea82008-03-20 13:15:34 -040083 /* Optimize transactions between CSB and other devices */
84 im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085 (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
Michael Barkowski5bbeea82008-03-20 13:15:34 -040086#endif
87
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#ifdef CONFIG_SYS_SPCR_TSECEP
Dave Liua8cb43a2008-01-17 18:23:19 +080089 /* all eTSEC's Emergency priority */
Kim Phillips9e896472008-01-16 12:06:16 -060090 im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSECEP) |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091 (CONFIG_SYS_SPCR_TSECEP << SPCR_TSECEP_SHIFT);
Kim Phillips9e896472008-01-16 12:06:16 -060092#endif
93
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#ifdef CONFIG_SYS_SPCR_TSEC1EP
Timur Tabi2ad6b512006-10-31 18:44:42 -060095 /* TSEC1 Emergency priority */
Kim Phillips9e896472008-01-16 12:06:16 -060096 im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC1EP) |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097 (CONFIG_SYS_SPCR_TSEC1EP << SPCR_TSEC1EP_SHIFT);
Timur Tabi2ad6b512006-10-31 18:44:42 -060098#endif
99
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#ifdef CONFIG_SYS_SPCR_TSEC2EP
Timur Tabi2ad6b512006-10-31 18:44:42 -0600101 /* TSEC2 Emergency priority */
Kim Phillips9e896472008-01-16 12:06:16 -0600102 im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_TSEC2EP) |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103 (CONFIG_SYS_SPCR_TSEC2EP << SPCR_TSEC2EP_SHIFT);
Kumar Gala4feab4d2007-02-27 23:51:42 -0600104#endif
105
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#ifdef CONFIG_SYS_SCCR_ENCCM
Kumar Gala4feab4d2007-02-27 23:51:42 -0600107 /* Encryption clock mode */
Kim Phillips9e896472008-01-16 12:06:16 -0600108 im->clk.sccr = (im->clk.sccr & ~SCCR_ENCCM) |
Norbert van Bolhuisb5816262009-03-13 08:58:14 +0100109 (CONFIG_SYS_SCCR_ENCCM << SCCR_ENCCM_SHIFT);
Timur Tabi2ad6b512006-10-31 18:44:42 -0600110#endif
111
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#ifdef CONFIG_SYS_SCCR_PCICM
Kim Phillips9e896472008-01-16 12:06:16 -0600113 /* PCI & DMA clock mode */
114 im->clk.sccr = (im->clk.sccr & ~SCCR_PCICM) |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115 (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT);
Kim Phillips9e896472008-01-16 12:06:16 -0600116#endif
117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#ifdef CONFIG_SYS_SCCR_TSECCM
Kim Phillips9e896472008-01-16 12:06:16 -0600119 /* all TSEC's clock mode */
120 im->clk.sccr = (im->clk.sccr & ~SCCR_TSECCM) |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121 (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT);
Kim Phillips9e896472008-01-16 12:06:16 -0600122#endif
123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#ifdef CONFIG_SYS_SCCR_TSEC1CM
Kim Phillips9e896472008-01-16 12:06:16 -0600125 /* TSEC1 clock mode */
126 im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1CM) |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127 (CONFIG_SYS_SCCR_TSEC1CM << SCCR_TSEC1CM_SHIFT);
Kim Phillips9e896472008-01-16 12:06:16 -0600128#endif
129
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#ifdef CONFIG_SYS_SCCR_TSEC2CM
Kim Phillips9e896472008-01-16 12:06:16 -0600131 /* TSEC2 clock mode */
132 im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2CM) |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133 (CONFIG_SYS_SCCR_TSEC2CM << SCCR_TSEC2CM_SHIFT);
Kim Phillips9e896472008-01-16 12:06:16 -0600134#endif
135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#ifdef CONFIG_SYS_SCCR_TSEC1ON
Kim Phillips9e896472008-01-16 12:06:16 -0600137 /* TSEC1 clock switch */
138 im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC1ON) |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139 (CONFIG_SYS_SCCR_TSEC1ON << SCCR_TSEC1ON_SHIFT);
Kim Phillips9e896472008-01-16 12:06:16 -0600140#endif
141
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#ifdef CONFIG_SYS_SCCR_TSEC2ON
Kim Phillips9e896472008-01-16 12:06:16 -0600143 /* TSEC2 clock switch */
144 im->clk.sccr = (im->clk.sccr & ~SCCR_TSEC2ON) |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145 (CONFIG_SYS_SCCR_TSEC2ON << SCCR_TSEC2ON_SHIFT);
Kim Phillips9e896472008-01-16 12:06:16 -0600146#endif
147
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#ifdef CONFIG_SYS_SCCR_USBMPHCM
Kim Phillips9e896472008-01-16 12:06:16 -0600149 /* USB MPH clock mode */
150 im->clk.sccr = (im->clk.sccr & ~SCCR_USBMPHCM) |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151 (CONFIG_SYS_SCCR_USBMPHCM << SCCR_USBMPHCM_SHIFT);
Kim Phillips9e896472008-01-16 12:06:16 -0600152#endif
153
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#ifdef CONFIG_SYS_SCCR_USBDRCM
Kim Phillips9e896472008-01-16 12:06:16 -0600155 /* USB DR clock mode */
156 im->clk.sccr = (im->clk.sccr & ~SCCR_USBDRCM) |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157 (CONFIG_SYS_SCCR_USBDRCM << SCCR_USBDRCM_SHIFT);
Kim Phillips9e896472008-01-16 12:06:16 -0600158#endif
159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#ifdef CONFIG_SYS_SCCR_SATACM
Kim Phillips9e896472008-01-16 12:06:16 -0600161 /* SATA controller clock mode */
162 im->clk.sccr = (im->clk.sccr & ~SCCR_SATACM) |
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163 (CONFIG_SYS_SCCR_SATACM << SCCR_SATACM_SHIFT);
Timur Tabi2ad6b512006-10-31 18:44:42 -0600164#endif
165
Eran Libertyf046ccd2005-07-28 10:08:46 -0500166 /* RSR - Reset Status Register - clear all status (4.6.1.3) */
167 gd->reset_status = im->reset.rsr;
168 im->reset.rsr = ~(RSR_RES);
169
Nick Spence46497052008-08-28 14:09:19 -0700170 /* AER - Arbiter Event Register - store status */
171 gd->arbiter_event_attributes = im->arbiter.aeatr;
172 gd->arbiter_event_address = im->arbiter.aeadr;
173
Eran Libertyf046ccd2005-07-28 10:08:46 -0500174 /*
175 * RMR - Reset Mode Register
176 * contains checkstop reset enable (4.6.1.4)
177 */
178 im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));
179
180 /* LCRR - Clock Ratio Register (10.3.1.16) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181 im->lbus.lcrr = CONFIG_SYS_LCRR;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500182
183 /* Enable Time Base & Decrimenter ( so we will have udelay() )*/
184 im->sysconf.spcr |= SPCR_TBEN;
185
186 /* System General Purpose Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#ifdef CONFIG_SYS_SICRH
Andre Schwarz846f1572008-06-23 11:40:56 +0200188#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC8313)
189 /* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190 im->sysconf.sicrh = (im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH;
Andre Schwarz846f1572008-06-23 11:40:56 +0200191#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192 im->sysconf.sicrh = CONFIG_SYS_SICRH;
Kumar Gala9260a562006-01-11 11:12:57 -0600193#endif
Andre Schwarz846f1572008-06-23 11:40:56 +0200194#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#ifdef CONFIG_SYS_SICRL
196 im->sysconf.sicrl = CONFIG_SYS_SICRL;
Kumar Gala9260a562006-01-11 11:12:57 -0600197#endif
Dave Liu24c3aca2006-12-07 21:13:15 +0800198 /* DDR control driver register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#ifdef CONFIG_SYS_DDRCDR
200 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
Dave Liu24c3aca2006-12-07 21:13:15 +0800201#endif
Dave Liu19580e62007-09-18 12:37:57 +0800202 /* Output buffer impedance register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200203#ifdef CONFIG_SYS_OBIR
204 im->sysconf.obir = CONFIG_SYS_OBIR;
Dave Liu19580e62007-09-18 12:37:57 +0800205#endif
Dave Liu24c3aca2006-12-07 21:13:15 +0800206
Dave Liu7737d5c2006-11-03 12:11:15 -0600207#ifdef CONFIG_QE
208 /* Config QE ioports */
209 config_qe_ioports();
210#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500211
212 /*
213 * Memory Controller:
214 */
215
216 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
217 * addresses - these have to be modified later when FLASH size
218 * has been determined
219 */
220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#if defined(CONFIG_SYS_BR0_PRELIM) \
222 && defined(CONFIG_SYS_OR0_PRELIM) \
223 && defined(CONFIG_SYS_LBLAWBAR0_PRELIM) \
224 && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
225 im->lbus.bank[0].br = CONFIG_SYS_BR0_PRELIM;
226 im->lbus.bank[0].or = CONFIG_SYS_OR0_PRELIM;
227 im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
228 im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500229#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#error CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
Eran Libertyf046ccd2005-07-28 10:08:46 -0500231#endif
232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
234 im->lbus.bank[1].br = CONFIG_SYS_BR1_PRELIM;
235 im->lbus.bank[1].or = CONFIG_SYS_OR1_PRELIM;
Kumar Galac99f3842006-01-25 16:12:46 -0600236#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
238 im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
239 im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500240#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200241#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
242 im->lbus.bank[2].br = CONFIG_SYS_BR2_PRELIM;
243 im->lbus.bank[2].or = CONFIG_SYS_OR2_PRELIM;
Kumar Galac99f3842006-01-25 16:12:46 -0600244#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
246 im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
247 im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500248#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
250 im->lbus.bank[3].br = CONFIG_SYS_BR3_PRELIM;
251 im->lbus.bank[3].or = CONFIG_SYS_OR3_PRELIM;
Kumar Galac99f3842006-01-25 16:12:46 -0600252#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
254 im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
255 im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500256#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
258 im->lbus.bank[4].br = CONFIG_SYS_BR4_PRELIM;
259 im->lbus.bank[4].or = CONFIG_SYS_OR4_PRELIM;
Kumar Galac99f3842006-01-25 16:12:46 -0600260#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
262 im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
263 im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500264#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
266 im->lbus.bank[5].br = CONFIG_SYS_BR5_PRELIM;
267 im->lbus.bank[5].or = CONFIG_SYS_OR5_PRELIM;
Kumar Galac99f3842006-01-25 16:12:46 -0600268#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
270 im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
271 im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500272#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
274 im->lbus.bank[6].br = CONFIG_SYS_BR6_PRELIM;
275 im->lbus.bank[6].or = CONFIG_SYS_OR6_PRELIM;
Kumar Galac99f3842006-01-25 16:12:46 -0600276#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
278 im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
279 im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500280#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
282 im->lbus.bank[7].br = CONFIG_SYS_BR7_PRELIM;
283 im->lbus.bank[7].or = CONFIG_SYS_OR7_PRELIM;
Kumar Galac99f3842006-01-25 16:12:46 -0600284#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200285#if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
286 im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
287 im->sysconf.lblaw[7].ar = CONFIG_SYS_LBLAWAR7_PRELIM;
Eran Libertyf046ccd2005-07-28 10:08:46 -0500288#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#ifdef CONFIG_SYS_GPIO1_PRELIM
290 im->gpio[0].dat = CONFIG_SYS_GPIO1_DAT;
291 im->gpio[0].dir = CONFIG_SYS_GPIO1_DIR;
Kumar Galaa15b44d2006-01-11 11:21:14 -0600292#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#ifdef CONFIG_SYS_GPIO2_PRELIM
294 im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
295 im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
Kumar Galaa15b44d2006-01-11 11:21:14 -0600296#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500297}
298
Eran Libertyf046ccd2005-07-28 10:08:46 -0500299int cpu_init_r (void)
300{
Dave Liu7737d5c2006-11-03 12:11:15 -0600301#ifdef CONFIG_QE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302 uint qe_base = CONFIG_SYS_IMMR + 0x00100000; /* QE immr base */
Dave Liu7737d5c2006-11-03 12:11:15 -0600303 qe_init(qe_base);
304 qe_reset();
305#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500306 return 0;
307}
Dave Liu9be39a62007-06-25 10:41:56 +0800308
309/*
Nick Spence46497052008-08-28 14:09:19 -0700310 * Print out the bus arbiter event
311 */
312#if defined(CONFIG_DISPLAY_AER_FULL)
313static int print_83xx_arb_event(int force)
314{
315 static char* event[] = {
316 "Address Time Out",
317 "Data Time Out",
318 "Address Only Transfer Type",
319 "External Control Word Transfer Type",
320 "Reserved Transfer Type",
321 "Transfer Error",
322 "reserved",
323 "reserved"
324 };
325 static char* master[] = {
326 "e300 Core Data Transaction",
327 "reserved",
328 "e300 Core Instruction Fetch",
329 "reserved",
330 "TSEC1",
331 "TSEC2",
332 "USB MPH",
333 "USB DR",
334 "Encryption Core",
335 "I2C Boot Sequencer",
336 "JTAG",
337 "reserved",
338 "eSDHC",
339 "PCI1",
340 "PCI2",
341 "DMA",
342 "QUICC Engine 00",
343 "QUICC Engine 01",
344 "QUICC Engine 10",
345 "QUICC Engine 11",
346 "reserved",
347 "reserved",
348 "reserved",
349 "reserved",
350 "SATA1",
351 "SATA2",
352 "SATA3",
353 "SATA4",
354 "reserved",
355 "PCI Express 1",
356 "PCI Express 2",
357 "TDM-DMAC"
358 };
359 static char *transfer[] = {
360 "Address-only, Clean Block",
361 "Address-only, lwarx reservation set",
362 "Single-beat or Burst write",
363 "reserved",
364 "Address-only, Flush Block",
365 "reserved",
366 "Burst write",
367 "reserved",
368 "Address-only, sync",
369 "Address-only, tlbsync",
370 "Single-beat or Burst read",
371 "Single-beat or Burst read",
372 "Address-only, Kill Block",
373 "Address-only, icbi",
374 "Burst read",
375 "reserved",
376 "Address-only, eieio",
377 "reserved",
378 "Single-beat write",
379 "reserved",
380 "ecowx - Illegal single-beat write",
381 "reserved",
382 "reserved",
383 "reserved",
384 "Address-only, TLB Invalidate",
385 "reserved",
386 "Single-beat or Burst read",
387 "reserved",
388 "eciwx - Illegal single-beat read",
389 "reserved",
390 "Burst read",
391 "reserved"
392 };
393
394 int etype = (gd->arbiter_event_attributes & AEATR_EVENT)
395 >> AEATR_EVENT_SHIFT;
396 int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID)
397 >> AEATR_MSTR_ID_SHIFT;
398 int tbst = (gd->arbiter_event_attributes & AEATR_TBST)
399 >> AEATR_TBST_SHIFT;
400 int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE)
401 >> AEATR_TSIZE_SHIFT;
402 int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE)
403 >> AEATR_TTYPE_SHIFT;
404
405 if (!force && !gd->arbiter_event_address)
406 return 0;
407
408 puts("Arbiter Event Status:\n");
409 printf(" Event Address: 0x%08lX\n", gd->arbiter_event_address);
410 printf(" Event Type: 0x%1x = %s\n", etype, event[etype]);
411 printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]);
412 printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize,
413 tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize);
414 printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]);
415
416 return gd->arbiter_event_address;
417}
418
419#elif defined(CONFIG_DISPLAY_AER_BRIEF)
420
421static int print_83xx_arb_event(int force)
422{
423 if (!force && !gd->arbiter_event_address)
424 return 0;
425
426 printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n",
427 gd->arbiter_event_attributes, gd->arbiter_event_address);
428
429 return gd->arbiter_event_address;
430}
431#endif /* CONFIG_DISPLAY_AER_xxxx */
432
433/*
Dave Liu9be39a62007-06-25 10:41:56 +0800434 * Figure out the cause of the reset
435 */
436int prt_83xx_rsr(void)
437{
438 static struct {
439 ulong mask;
440 char *desc;
441 } bits[] = {
442 {
443 RSR_SWSR, "Software Soft"}, {
444 RSR_SWHR, "Software Hard"}, {
445 RSR_JSRS, "JTAG Soft"}, {
446 RSR_CSHR, "Check Stop"}, {
447 RSR_SWRS, "Software Watchdog"}, {
448 RSR_BMRS, "Bus Monitor"}, {
449 RSR_SRS, "External/Internal Soft"}, {
450 RSR_HRS, "External/Internal Hard"}
451 };
452 static int n = sizeof bits / sizeof bits[0];
453 ulong rsr = gd->reset_status;
454 int i;
455 char *sep;
456
457 puts("Reset Status:");
458
459 sep = " ";
460 for (i = 0; i < n; i++)
461 if (rsr & bits[i].mask) {
462 printf("%s%s", sep, bits[i].desc);
463 sep = ", ";
464 }
Nick Spence46497052008-08-28 14:09:19 -0700465 puts("\n");
466
467#if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF)
468 print_83xx_arb_event(rsr & RSR_BMRS);
469#endif
470 puts("\n");
471
Dave Liu9be39a62007-06-25 10:41:56 +0800472 return 0;
473}