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wdenk0f8c9762002-08-19 11:57:05 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenk0f8c9762002-08-19 11:57:05 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
37#define CONFIG_CPU86 1 /* ...on a CPU86 board */
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050038#define CONFIG_CPM2 1 /* Has a CPM2 */
wdenk0f8c9762002-08-19 11:57:05 +000039
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040#ifdef CONFIG_BOOT_ROM
41#define CONFIG_SYS_TEXT_BASE 0xFF800000
42#else
43#define CONFIG_SYS_TEXT_BASE 0xFF000000
44#endif
45
wdenk0f8c9762002-08-19 11:57:05 +000046/*
47 * select serial console configuration
48 *
49 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
50 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
51 * for SCC).
52 *
53 * if CONFIG_CONS_NONE is defined, then the serial console routines must
54 * defined elsewhere (for example, on the cogent platform, there are serial
55 * ports on the motherboard which are used for the serial console - see
56 * cogent/cma101/serial.[ch]).
57 */
58#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
59#define CONFIG_CONS_ON_SCC /* define if console on SCC */
60#undef CONFIG_CONS_NONE /* define if console on something else*/
61#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
62
63#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
64#define CONFIG_BAUDRATE 230400
65#else
66#define CONFIG_BAUDRATE 9600
67#endif
68
69/*
70 * select ethernet configuration
71 *
72 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
73 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
74 * for FCC)
75 *
76 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050077 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenk0f8c9762002-08-19 11:57:05 +000078 */
79#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
80#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
81#undef CONFIG_ETHER_NONE /* define if ether on something else */
82#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
83
84#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
85
86/*
87 * - Rx-CLK is CLK11
88 * - Tx-CLK is CLK12
89 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
90 * - Enable Full Duplex in FSMR
91 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
93# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
94# define CONFIG_SYS_CPMFCR_RAMTYPE 0
95# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
wdenk0f8c9762002-08-19 11:57:05 +000096
97#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
98
99/*
100 * - Rx-CLK is CLK13
101 * - Tx-CLK is CLK14
102 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
103 * - Enable Full Duplex in FSMR
104 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
106# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
107# define CONFIG_SYS_CPMFCR_RAMTYPE 0
108# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
wdenk0f8c9762002-08-19 11:57:05 +0000109
110#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
111
112/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
113#define CONFIG_8260_CLKIN 64000000 /* in Hz */
114
115#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
116
wdenk0f8c9762002-08-19 11:57:05 +0000117#define CONFIG_PREBOOT \
118 "echo; " \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100119 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; " \
wdenk0f8c9762002-08-19 11:57:05 +0000120 "echo"
121
122#undef CONFIG_BOOTARGS
123#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200124 "bootp; " \
125 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
126 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk0f8c9762002-08-19 11:57:05 +0000127 "bootm"
128
129/*-----------------------------------------------------------------------
130 * I2C/EEPROM/RTC configuration
131 */
132#define CONFIG_SOFT_I2C /* Software I2C support enabled */
133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134# define CONFIG_SYS_I2C_SPEED 50000
135# define CONFIG_SYS_I2C_SLAVE 0xFE
wdenk0f8c9762002-08-19 11:57:05 +0000136/*
137 * Software (bit-bang) I2C driver configuration
138 */
139#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
140#define I2C_ACTIVE (iop->pdir |= 0x00010000)
141#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
142#define I2C_READ ((iop->pdat & 0x00010000) != 0)
143#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
144 else iop->pdat &= ~0x00010000
145#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
146 else iop->pdat &= ~0x00020000
147#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
148
149#define CONFIG_RTC_PCF8563
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_I2C_RTC_ADDR 0x51
wdenk0f8c9762002-08-19 11:57:05 +0000151
152#undef CONFIG_WATCHDOG /* watchdog disabled */
153
154/*-----------------------------------------------------------------------
wdenk0f8c9762002-08-19 11:57:05 +0000155 * Miscellaneous configuration options
156 */
157
158#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200159#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenk0f8c9762002-08-19 11:57:05 +0000160
Jon Loeliger5d2ebe12007-07-09 21:16:53 -0500161/*
162 * BOOTP options
163 */
164#define CONFIG_BOOTP_SUBNETMASK
165#define CONFIG_BOOTP_GATEWAY
166#define CONFIG_BOOTP_HOSTNAME
167#define CONFIG_BOOTP_BOOTPATH
168#define CONFIG_BOOTP_BOOTFILESIZE
wdenk0f8c9762002-08-19 11:57:05 +0000169
wdenk0f8c9762002-08-19 11:57:05 +0000170
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500171/*
172 * Command line configuration.
173 */
174#include <config_cmd_default.h>
175
176#define CONFIG_CMD_BEDBUG
177#define CONFIG_CMD_DATE
178#define CONFIG_CMD_DHCP
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500179#define CONFIG_CMD_EEPROM
180#define CONFIG_CMD_I2C
181#define CONFIG_CMD_NFS
182#define CONFIG_CMD_SNTP
183
wdenk0f8c9762002-08-19 11:57:05 +0000184
185/*
186 * Miscellaneous configurable options
187 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_LONGHELP /* undef to save memory */
189#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500190#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000192#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000194#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
196#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
197#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk0f8c9762002-08-19 11:57:05 +0000198
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
200#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenk0f8c9762002-08-19 11:57:05 +0000201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenk0f8c9762002-08-19 11:57:05 +0000203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk0f8c9762002-08-19 11:57:05 +0000205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk0f8c9762002-08-19 11:57:05 +0000207
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200208#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */
wdenk0f8c9762002-08-19 11:57:05 +0000209
210/*
211 * For booting Linux, the board info and command line data
212 * have to be in the first 8 MB of memory, since this is
213 * the maximum mapped by the Linux kernel during initialization.
214 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk0f8c9762002-08-19 11:57:05 +0000216
217/*-----------------------------------------------------------------------
218 * Flash configuration
219 */
220
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221#define CONFIG_SYS_BOOTROM_BASE 0xFF800000
222#define CONFIG_SYS_BOOTROM_SIZE 0x00080000
223#define CONFIG_SYS_FLASH_BASE 0xFF000000
224#define CONFIG_SYS_FLASH_SIZE 0x00800000
wdenk0f8c9762002-08-19 11:57:05 +0000225
226/*-----------------------------------------------------------------------
227 * FLASH organization
228 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
230#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
wdenk0f8c9762002-08-19 11:57:05 +0000231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
233#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenk0f8c9762002-08-19 11:57:05 +0000234
235/*-----------------------------------------------------------------------
236 * Other areas to be mapped
237 */
238
239/* CS3: Dual ported SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_DPSRAM_BASE 0x40000000
241#define CONFIG_SYS_DPSRAM_SIZE 0x00020000
wdenk0f8c9762002-08-19 11:57:05 +0000242
243/* CS4: DiskOnChip */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200244#define CONFIG_SYS_DOC_BASE 0xF4000000
245#define CONFIG_SYS_DOC_SIZE 0x00100000
wdenk0f8c9762002-08-19 11:57:05 +0000246
247/* CS5: FDC37C78 controller */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_FDC37C78_BASE 0xF1000000
249#define CONFIG_SYS_FDC37C78_SIZE 0x00100000
wdenk0f8c9762002-08-19 11:57:05 +0000250
251/* CS6: Board configuration registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_BCRS_BASE 0xF2000000
253#define CONFIG_SYS_BCRS_SIZE 0x00010000
wdenk0f8c9762002-08-19 11:57:05 +0000254
255/* CS7: VME Extended Access Range */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_VMEEAR_BASE 0x80000000
257#define CONFIG_SYS_VMEEAR_SIZE 0x01000000
wdenk0f8c9762002-08-19 11:57:05 +0000258
259/* CS8: VME Standard Access Range */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_VMESAR_BASE 0xFE000000
261#define CONFIG_SYS_VMESAR_SIZE 0x01000000
wdenk0f8c9762002-08-19 11:57:05 +0000262
263/* CS9: VME Short I/O Access Range */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_VMESIOAR_BASE 0xFD000000
265#define CONFIG_SYS_VMESIOAR_SIZE 0x01000000
wdenk0f8c9762002-08-19 11:57:05 +0000266
267/*-----------------------------------------------------------------------
268 * Hard Reset Configuration Words
269 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
wdenk0f8c9762002-08-19 11:57:05 +0000271 * defines for the various registers affected by the HRCW e.g. changing
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
wdenk0f8c9762002-08-19 11:57:05 +0000273 */
274#if defined(CONFIG_BOOT_ROM)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
wdenk0f8c9762002-08-19 11:57:05 +0000276 HRCW_BPS01 | HRCW_CS10PC01)
277#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
wdenk0f8c9762002-08-19 11:57:05 +0000279#endif
280
281/* no slaves so just fill with zeros */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_HRCW_SLAVE1 0
283#define CONFIG_SYS_HRCW_SLAVE2 0
284#define CONFIG_SYS_HRCW_SLAVE3 0
285#define CONFIG_SYS_HRCW_SLAVE4 0
286#define CONFIG_SYS_HRCW_SLAVE5 0
287#define CONFIG_SYS_HRCW_SLAVE6 0
288#define CONFIG_SYS_HRCW_SLAVE7 0
wdenk0f8c9762002-08-19 11:57:05 +0000289
290/*-----------------------------------------------------------------------
291 * Internal Memory Mapped Register
292 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_IMMR 0xF0000000
wdenk0f8c9762002-08-19 11:57:05 +0000294
295/*-----------------------------------------------------------------------
296 * Definitions for initial stack pointer and data area (in DPRAM)
297 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200299#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200300#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk0f8c9762002-08-19 11:57:05 +0000302
303/*-----------------------------------------------------------------------
304 * Start addresses for the final memory configuration
305 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk0f8c9762002-08-19 11:57:05 +0000307 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
wdenk0f8c9762002-08-19 11:57:05 +0000309 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_SDRAM_BASE 0x00000000
311#define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200312#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
314#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
wdenk0f8c9762002-08-19 11:57:05 +0000315
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
317# define CONFIG_SYS_RAMBOOT
wdenk0f8c9762002-08-19 11:57:05 +0000318#endif
319
320#if 0
321/* environment is in Flash */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200322#define CONFIG_ENV_IS_IN_FLASH 1
wdenk0f8c9762002-08-19 11:57:05 +0000323#ifdef CONFIG_BOOT_ROM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x70000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200325# define CONFIG_ENV_SIZE 0x10000
326# define CONFIG_ENV_SECT_SIZE 0x10000
wdenk0f8c9762002-08-19 11:57:05 +0000327#endif
328#else
329/* environment is in EEPROM */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200330#define CONFIG_ENV_IS_IN_EEPROM 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */
332#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
wdenk0f8c9762002-08-19 11:57:05 +0000333/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
335#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
336#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200337#define CONFIG_ENV_OFFSET 512
338#define CONFIG_ENV_SIZE (2048 - 512)
wdenk0f8c9762002-08-19 11:57:05 +0000339#endif
340
wdenk0f8c9762002-08-19 11:57:05 +0000341/*-----------------------------------------------------------------------
342 * Cache Configuration
343 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger49cf7e82007-07-05 19:52:35 -0500345#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk0f8c9762002-08-19 11:57:05 +0000347#endif
348
349/*-----------------------------------------------------------------------
350 * HIDx - Hardware Implementation-dependent Registers 2-11
351 *-----------------------------------------------------------------------
352 * HID0 also contains cache control - initially enable both caches and
353 * invalidate contents, then the final state leaves only the instruction
354 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
355 * but Soft reset does not.
356 *
357 * HID1 has only read-only information - nothing to set.
358 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
wdenk8bde7f72003-06-27 21:31:46 +0000360 HID0_DCI|HID0_IFEM|HID0_ABE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
362#define CONFIG_SYS_HID2 0
wdenk0f8c9762002-08-19 11:57:05 +0000363
364/*-----------------------------------------------------------------------
365 * RMR - Reset Mode Register 5-5
366 *-----------------------------------------------------------------------
367 * turn on Checkstop Reset Enable
368 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200369#define CONFIG_SYS_RMR RMR_CSRE
wdenk0f8c9762002-08-19 11:57:05 +0000370
371/*-----------------------------------------------------------------------
372 * BCR - Bus Configuration 4-25
373 *-----------------------------------------------------------------------
374 */
375#define BCR_APD01 0x10000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
wdenk0f8c9762002-08-19 11:57:05 +0000377
378/*-----------------------------------------------------------------------
379 * SIUMCR - SIU Module Configuration 4-31
380 *-----------------------------------------------------------------------
381 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200382#define CONFIG_SYS_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
wdenk0f8c9762002-08-19 11:57:05 +0000383 SIUMCR_CS10PC01|SIUMCR_BCTLC10)
384
385/*-----------------------------------------------------------------------
386 * SYPCR - System Protection Control 4-35
387 * SYPCR can only be written once after reset!
388 *-----------------------------------------------------------------------
389 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
390 */
391#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk8bde7f72003-06-27 21:31:46 +0000393 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
wdenk0f8c9762002-08-19 11:57:05 +0000394#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200395#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenk8bde7f72003-06-27 21:31:46 +0000396 SYPCR_SWRI|SYPCR_SWP)
wdenk0f8c9762002-08-19 11:57:05 +0000397#endif /* CONFIG_WATCHDOG */
398
399/*-----------------------------------------------------------------------
400 * TMCNTSC - Time Counter Status and Control 4-40
401 *-----------------------------------------------------------------------
402 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
403 * and enable Time Counter
404 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
wdenk0f8c9762002-08-19 11:57:05 +0000406
407/*-----------------------------------------------------------------------
408 * PISCR - Periodic Interrupt Status and Control 4-42
409 *-----------------------------------------------------------------------
410 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
411 * Periodic timer
412 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenk0f8c9762002-08-19 11:57:05 +0000414
415/*-----------------------------------------------------------------------
416 * SCCR - System Clock Control 9-8
417 *-----------------------------------------------------------------------
418 * Ensure DFBRG is Divide by 16
419 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_SCCR SCCR_DFBRG01
wdenk0f8c9762002-08-19 11:57:05 +0000421
422/*-----------------------------------------------------------------------
423 * RCCR - RISC Controller Configuration 13-7
424 *-----------------------------------------------------------------------
425 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200426#define CONFIG_SYS_RCCR 0
wdenk0f8c9762002-08-19 11:57:05 +0000427
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428#define CONFIG_SYS_MIN_AM_MASK 0xC0000000
wdenk0f8c9762002-08-19 11:57:05 +0000429/*-----------------------------------------------------------------------
430 * MPTPR - Memory Refresh Timer Prescaler Register 10-18
431 *-----------------------------------------------------------------------
432 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#define CONFIG_SYS_MPTPR 0x1F00
wdenk0f8c9762002-08-19 11:57:05 +0000434
435/*-----------------------------------------------------------------------
436 * PSRT - Refresh Timer Register 10-16
437 *-----------------------------------------------------------------------
438 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200439#define CONFIG_SYS_PSRT 0x0f
wdenk0f8c9762002-08-19 11:57:05 +0000440
441/*-----------------------------------------------------------------------
442 * PSRT - SDRAM Mode Register 10-10
443 *-----------------------------------------------------------------------
444 */
445
446 /* SDRAM initialization values for 8-column chips
447 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\
wdenk0f8c9762002-08-19 11:57:05 +0000449 ORxS_BPD_4 |\
450 ORxS_ROWST_PBI0_A9 |\
451 ORxS_NUMR_12)
452
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200453#define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
wdenk0f8c9762002-08-19 11:57:05 +0000454 PSDMR_BSMA_A14_A16 |\
455 PSDMR_SDA10_PBI0_A10 |\
456 PSDMR_RFRC_7_CLK |\
457 PSDMR_PRETOACT_2W |\
458 PSDMR_ACTTORW_1W |\
459 PSDMR_LDOTOPRE_1C |\
460 PSDMR_WRC_1C |\
461 PSDMR_CL_2)
462
463 /* SDRAM initialization values for 9-column chips
464 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\
wdenk0f8c9762002-08-19 11:57:05 +0000466 ORxS_BPD_4 |\
467 ORxS_ROWST_PBI0_A7 |\
468 ORxS_NUMR_13)
469
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
wdenk0f8c9762002-08-19 11:57:05 +0000471 PSDMR_BSMA_A13_A15 |\
472 PSDMR_SDA10_PBI0_A9 |\
473 PSDMR_RFRC_7_CLK |\
474 PSDMR_PRETOACT_2W |\
475 PSDMR_ACTTORW_1W |\
476 PSDMR_LDOTOPRE_1C |\
477 PSDMR_WRC_1C |\
478 PSDMR_CL_2)
479
480/*
481 * Init Memory Controller:
482 *
483 * Bank Bus Machine PortSz Device
484 * ---- --- ------- ------ ------
485 * 0 60x GPCM 8 bit Boot ROM
486 * 1 60x GPCM 64 bit FLASH
487 * 2 60x SDRAM 64 bit SDRAM
488 *
489 */
490
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200491#define CONFIG_SYS_MRS_OFFS 0x00000000
wdenk0f8c9762002-08-19 11:57:05 +0000492
493#ifdef CONFIG_BOOT_ROM
494/* Bank 0 - Boot ROM
495 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200496#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
wdenk8bde7f72003-06-27 21:31:46 +0000497 BRx_PS_8 |\
498 BRx_MS_GPCM_P |\
499 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000500
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200501#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000502 ORxG_CSNT |\
503 ORxG_ACS_DIV1 |\
504 ORxG_SCY_3_CLK |\
505 ORxU_EHTR_8IDLE)
wdenk0f8c9762002-08-19 11:57:05 +0000506
507/* Bank 1 - FLASH
508 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200509#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000510 BRx_PS_64 |\
511 BRx_MS_GPCM_P |\
512 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000513
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200514#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000515 ORxG_CSNT |\
516 ORxG_ACS_DIV1 |\
517 ORxG_SCY_3_CLK |\
518 ORxU_EHTR_8IDLE)
wdenk0f8c9762002-08-19 11:57:05 +0000519
520#else /* CONFIG_BOOT_ROM */
521/* Bank 0 - FLASH
522 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200523#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000524 BRx_PS_64 |\
525 BRx_MS_GPCM_P |\
526 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000527
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200528#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000529 ORxG_CSNT |\
530 ORxG_ACS_DIV1 |\
531 ORxG_SCY_3_CLK |\
532 ORxU_EHTR_8IDLE)
wdenk0f8c9762002-08-19 11:57:05 +0000533
534/* Bank 1 - Boot ROM
535 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200536#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
wdenk8bde7f72003-06-27 21:31:46 +0000537 BRx_PS_8 |\
538 BRx_MS_GPCM_P |\
539 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000540
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200541#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000542 ORxG_CSNT |\
543 ORxG_ACS_DIV1 |\
544 ORxG_SCY_3_CLK |\
545 ORxU_EHTR_8IDLE)
wdenk0f8c9762002-08-19 11:57:05 +0000546
547#endif /* CONFIG_BOOT_ROM */
548
549
550/* Bank 2 - 60x bus SDRAM
551 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200552#ifndef CONFIG_SYS_RAMBOOT
553#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000554 BRx_PS_64 |\
555 BRx_MS_SDRAM_P |\
556 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000557
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200558#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_9COL
wdenk0f8c9762002-08-19 11:57:05 +0000559
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200560#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_9COL
561#endif /* CONFIG_SYS_RAMBOOT */
wdenk0f8c9762002-08-19 11:57:05 +0000562
563/* Bank 3 - Dual Ported SRAM
564 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200565#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000566 BRx_PS_16 |\
567 BRx_MS_GPCM_P |\
568 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000569
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200570#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000571 ORxG_CSNT |\
572 ORxG_ACS_DIV1 |\
573 ORxG_SCY_5_CLK |\
574 ORxG_SETA)
wdenk0f8c9762002-08-19 11:57:05 +0000575
576/* Bank 4 - DiskOnChip
577 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200578#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000579 BRx_PS_8 |\
580 BRx_MS_GPCM_P |\
581 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000582
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200583#define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000584 ORxG_ACS_DIV2 |\
585 ORxG_SCY_5_CLK |\
586 ORxU_EHTR_8IDLE)
wdenk0f8c9762002-08-19 11:57:05 +0000587
588/* Bank 5 - FDC37C78 controller
589 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200590#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000591 BRx_PS_8 |\
592 BRx_MS_GPCM_P |\
593 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000594
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200595#define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000596 ORxG_ACS_DIV2 |\
597 ORxG_SCY_8_CLK |\
598 ORxU_EHTR_8IDLE)
wdenk0f8c9762002-08-19 11:57:05 +0000599
600/* Bank 6 - Board control registers
601 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200602#define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000603 BRx_PS_8 |\
604 BRx_MS_GPCM_P |\
605 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000606
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200607#define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000608 ORxG_CSNT |\
609 ORxG_SCY_5_CLK)
wdenk0f8c9762002-08-19 11:57:05 +0000610
611/* Bank 7 - VME Extended Access Range
612 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200613#define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000614 BRx_PS_32 |\
615 BRx_MS_GPCM_P |\
616 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000617
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200618#define CONFIG_SYS_OR7_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000619 ORxG_CSNT |\
620 ORxG_ACS_DIV1 |\
621 ORxG_SCY_5_CLK |\
622 ORxG_SETA)
wdenk0f8c9762002-08-19 11:57:05 +0000623
624/* Bank 8 - VME Standard Access Range
625 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200626#define CONFIG_SYS_BR8_PRELIM ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000627 BRx_PS_16 |\
628 BRx_MS_GPCM_P |\
629 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000630
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200631#define CONFIG_SYS_OR8_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000632 ORxG_CSNT |\
633 ORxG_ACS_DIV1 |\
634 ORxG_SCY_5_CLK |\
635 ORxG_SETA)
wdenk0f8c9762002-08-19 11:57:05 +0000636
637/* Bank 9 - VME Short I/O Access Range
638 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200639#define CONFIG_SYS_BR9_PRELIM ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
wdenk8bde7f72003-06-27 21:31:46 +0000640 BRx_PS_16 |\
641 BRx_MS_GPCM_P |\
642 BRx_V)
wdenk0f8c9762002-08-19 11:57:05 +0000643
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200644#define CONFIG_SYS_OR9_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE) |\
wdenk8bde7f72003-06-27 21:31:46 +0000645 ORxG_CSNT |\
646 ORxG_ACS_DIV1 |\
647 ORxG_SCY_5_CLK |\
648 ORxG_SETA)
wdenk0f8c9762002-08-19 11:57:05 +0000649
650#endif /* __CONFIG_H */