blob: 356fd46f933d3fb23716d735d7fdf6d31a816b9b [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001# SPDX-License-Identifier: GPL-2.0+
Albert ARIBAUD35629362015-10-23 18:06:43 +02002#
3# (C) Copyright 2009
4# Marvell Semiconductor <www.marvell.com>
5# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
Albert ARIBAUD35629362015-10-23 18:06:43 +02006# Refer doc/README.kwbimage for more details about how-to configure
7# and create kirkwood boot image
8#
9
10# Boot Media configurations
11BOOT_FROM nand
12NAND_ECC_MODE default
13NAND_PAGE_SIZE 0x0800
14
15# SOC registers configuration using bootrom header extension
16# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
17
18# Configure RGMII-0 interface pad voltage to 1.8V
19DATA 0xFFD100e0 0x1b1b1b9b
20
21#Dram initalization for SINGLE x16 CL=5 @ 400MHz
22DATA 0xFFD01400 0x43000c30 # DDR Configuration register
23# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
24# bit23-14: zero
25# bit24: 1= enable exit self refresh mode on DDR access
26# bit25: 1 required
27# bit29-26: zero
28# bit31-30: 01
29
30DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
31# bit 4: 0=addr/cmd in smame cycle
32# bit 5: 0=clk is driven during self refresh, we don't care for APX
33# bit 6: 0=use recommended falling edge of clk for addr/cmd
34# bit14: 0=input buffer always powered up
35# bit18: 1=cpu lock transaction enabled
36# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
37# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
38# bit30-28: 3 required
39# bit31: 0=no additional STARTBURST delay
40
41DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
42# bit3-0: TRAS lsbs
43# bit7-4: TRCD
44# bit11- 8: TRP
45# bit15-12: TWR
46# bit19-16: TWTR
47# bit20: TRAS msb
48# bit23-21: 0x0
49# bit27-24: TRRD
50# bit31-28: TRTP
51
52DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
53# bit6-0: TRFC
54# bit8-7: TR2R
55# bit10-9: TR2W
56# bit12-11: TW2W
57# bit31-13: zero required
58
59DATA 0xFFD01410 0x000000cc # DDR Address Control
60# bit1-0: 00, Cs0width=x8
61# bit3-2: 11, Cs0size=1Gb
62# bit5-4: 00, Cs1width=x8
63# bit7-6: 11, Cs1size=1Gb
64# bit9-8: 00, Cs2width=nonexistent
65# bit11-10: 00, Cs2size =nonexistent
66# bit13-12: 00, Cs3width=nonexistent
67# bit15-14: 00, Cs3size =nonexistent
68# bit16: 0, Cs0AddrSel
69# bit17: 0, Cs1AddrSel
70# bit18: 0, Cs2AddrSel
71# bit19: 0, Cs3AddrSel
72# bit31-20: 0 required
73
74DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
75# bit0: 0, OpenPage enabled
76# bit31-1: 0 required
77
78DATA 0xFFD01418 0x00000000 # DDR Operation
79# bit3-0: 0x0, DDR cmd
80# bit31-4: 0 required
81
82DATA 0xFFD0141C 0x00000C52 # DDR Mode
83# bit2-0: 2, BurstLen=2 required
84# bit3: 0, BurstType=0 required
85# bit6-4: 4, CL=5
86# bit7: 0, TestMode=0 normal
87# bit8: 0, DLL reset=0 normal
88# bit11-9: 6, auto-precharge write recovery ????????????
89# bit12: 0, PD must be zero
90# bit31-13: 0 required
91
92DATA 0xFFD01420 0x00000042 # DDR Extended Mode
93# bit0: 0, DDR DLL enabled
94# bit1: 1, DDR drive strength reduced
95# bit2: 0, DDR ODT control lsd (disabled)
96# bit5-3: 000, required
97# bit6: 1, DDR ODT control msb, (disabled)
98# bit9-7: 000, required
99# bit10: 0, differential DQS enabled
100# bit11: 0, required
101# bit12: 0, DDR output buffer enabled
102# bit31-13: 0 required
103
104DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
105# bit2-0: 111, required
106# bit3 : 1 , MBUS Burst Chop disabled
107# bit6-4: 111, required
108# bit7 : 0
109# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
110# bit9 : 0 , no half clock cycle addition to dataout
111# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
112# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
113# bit15-12: 1111 required
114# bit31-16: 0 required
115
116DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
117DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
118
119DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
120DATA 0xFFD01504 0x0FFFFFF1 # CS[0]n Size
121# bit0: 1, Window enabled
122# bit1: 0, Write Protect disabled
123# bit3-2: 00, CS0 hit selected
124# bit23-4: ones, required
125# bit31-24: 0x0F, Size (i.e. 256MB)
126
127DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
128DATA 0xFFD0150C 0x0FFFFFF5 # CS[1]n Size 256Mb Window enabled for CS1
129
130DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
131DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
132
133DATA 0xFFD01494 0x00120012 # DDR ODT Control (Low)
134# bit3-0: 0010, (read) M_ODT[0] is asserted during read from DRAM CS1
135# bit7-4: 0001, (read) M_ODT[1] is asserted during read from DRAM CS0
136# bit19-16: 0010, (write) M_ODT[0] is asserted during write to DRAM CS1.
137# bit23-20: 0001, (write) M_ODT[1] is asserted during write to DRAM CS0.
138DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
139
140DATA 0xFFD0149C 0x0000E40f # CPU ODT Control
141# bit3-0: 1111, internal ODT is asserted during read from DRAM bank 0-3
142# bit11-10: 01, M_DQ, M_DM, and M_DQS I/O buffer ODT Select: 150 ohm
143# bit13-12: 10, M_STARTBURST_IN I/O buffer ODT Select: 75 ohm
144# bit14: 1, M_STARTBURST_IN ODT: Enabled
145# bit15: 1, DDR IO ODT Unit: Use ODT block
146DATA 0xFFD01480 0x00000001 # DDR Initialization Control
147#bit0=1, enable DDR init upon this register write
148
149# End of Header extension
150DATA 0x0 0x0