blob: d817423a7ed3ee8ce98a3b8c3bb729dbf44dd7a9 [file] [log] [blame]
Stelian Pop8e429b32008-05-08 18:52:23 +02001/*
2 * (C) Copyright 2007-2008
3 * Stelian Pop <stelian.pop@leadtechdesign.com>
4 * Lead Tech Design <www.leadtechdesign.com>
5 *
6 * Configuation settings for the AT91SAM9263EK board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
Xu, Hongcd46b0f2011-06-10 21:31:26 +000030/*
31 * SoC must be defined first, before hardware.h is included.
32 * In this case SoC is defined in boards.cfg.
33 */
34#include <asm/hardware.h>
Stelian Pop8e429b32008-05-08 18:52:23 +020035
Xu, Hongcd46b0f2011-06-10 21:31:26 +000036#define CONFIG_SYS_TEXT_BASE 0x21F00000
37
38/* ARM asynchronous clock */
39#define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */
40#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
41#define CONFIG_SYS_HZ 1000
42
43#define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */
44
Jean-Christophe PLAGNIOL-VILLARDdc39ae92009-04-16 21:30:44 +020045#define CONFIG_ARCH_CPU_INIT
Stelian Pop8e429b32008-05-08 18:52:23 +020046#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
47
48#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
49#define CONFIG_SETUP_MEMORY_TAGS 1
50#define CONFIG_INITRD_TAG 1
51
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +020052#ifndef CONFIG_SYS_USE_BOOT_NORFLASH
Stelian Pop8e429b32008-05-08 18:52:23 +020053#define CONFIG_SKIP_LOWLEVEL_INIT
Xu, Hongcd46b0f2011-06-10 21:31:26 +000054#else
55#define CONFIG_SYS_USE_NORFLASH
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +020056#endif
Stelian Pop8e429b32008-05-08 18:52:23 +020057
Xu, Hongcd46b0f2011-06-10 21:31:26 +000058#define CONFIG_BOARD_EARLY_INIT_F
59
60#define CONFIG_DISPLAY_CPUINFO
61
Stelian Pop8e429b32008-05-08 18:52:23 +020062/*
63 * Hardware drivers
64 */
Xu, Hongcd46b0f2011-06-10 21:31:26 +000065#define CONFIG_ATMEL_LEGACY
66#define CONFIG_AT91_GPIO 1
67#define CONFIG_AT91_GPIO_PULLUP 1
68
69/* serial console */
70#define CONFIG_ATMEL_USART
71#define CONFIG_USART_BASE ATMEL_BASE_DBGU
72#define CONFIG_USART_ID ATMEL_ID_SYS
73#define CONFIG_BAUDRATE 115200
74#define CONFIG_SYS_BAUDRATE_TABLE {115200, 19200, 38400, 57600, 9600}
Stelian Pop8e429b32008-05-08 18:52:23 +020075
Stelian Pop56a24792008-05-08 14:52:31 +020076/* LCD */
77#define CONFIG_LCD 1
78#define LCD_BPP LCD_COLOR8
79#define CONFIG_LCD_LOGO 1
80#undef LCD_TEST_PATTERN
81#define CONFIG_LCD_INFO 1
82#define CONFIG_LCD_INFO_BELOW_LOGO 1
Xu, Hongcd46b0f2011-06-10 21:31:26 +000083#define CONFIG_SYS_WHITE_ON_BLACK 1
Stelian Pop56a24792008-05-08 14:52:31 +020084#define CONFIG_ATMEL_LCD 1
85#define CONFIG_ATMEL_LCD_BGR555 1
Xu, Hongcd46b0f2011-06-10 21:31:26 +000086#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
Stelian Pop56a24792008-05-08 14:52:31 +020087
Jean-Christophe PLAGNIOL-VILLARDa484b002009-03-21 21:08:00 +010088/* LED */
89#define CONFIG_AT91_LED
Xu, Hongcd46b0f2011-06-10 21:31:26 +000090#define CONFIG_RED_LED AT91_PIN_PB7 /* the power led */
91#define CONFIG_GREEN_LED AT91_PIN_PB8 /* the user1 led */
92#define CONFIG_YELLOW_LED AT91_PIN_PC29 /* the user2 led */
Jean-Christophe PLAGNIOL-VILLARDa484b002009-03-21 21:08:00 +010093
Stelian Pop8e429b32008-05-08 18:52:23 +020094#define CONFIG_BOOTDELAY 3
95
Stelian Pop8e429b32008-05-08 18:52:23 +020096/*
97 * BOOTP options
98 */
99#define CONFIG_BOOTP_BOOTFILESIZE 1
100#define CONFIG_BOOTP_BOOTPATH 1
101#define CONFIG_BOOTP_GATEWAY 1
102#define CONFIG_BOOTP_HOSTNAME 1
103
104/*
105 * Command line configuration.
106 */
107#include <config_cmd_default.h>
108#undef CONFIG_CMD_BDI
Stelian Pop8e429b32008-05-08 18:52:23 +0200109#undef CONFIG_CMD_FPGA
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200110#undef CONFIG_CMD_IMI
Stelian Pop8e429b32008-05-08 18:52:23 +0200111#undef CONFIG_CMD_IMLS
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200112#undef CONFIG_CMD_LOADS
113#undef CONFIG_CMD_SOURCE
Stelian Pop8e429b32008-05-08 18:52:23 +0200114
115#define CONFIG_CMD_PING 1
116#define CONFIG_CMD_DHCP 1
117#define CONFIG_CMD_NAND 1
118#define CONFIG_CMD_USB 1
119
120/* SDRAM */
121#define CONFIG_NR_DRAM_BANKS 1
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000122#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
123#define CONFIG_SYS_SDRAM_SIZE 0x04000000
124
125#define CONFIG_SYS_INIT_SP_ADDR \
126 (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE)
Stelian Pop8e429b32008-05-08 18:52:23 +0200127
128/* DataFlash */
Jean-Christophe PLAGNIOL-VILLARD4758ebd2009-03-27 23:26:44 +0100129#define CONFIG_ATMEL_DATAFLASH_SPI
Stelian Pop8e429b32008-05-08 18:52:23 +0200130#define CONFIG_HAS_DATAFLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
132#define CONFIG_SYS_MAX_DATAFLASH_BANKS 1
133#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
Stelian Pop8e429b32008-05-08 18:52:23 +0200134#define AT91_SPI_CLK 15000000
135#define DATAFLASH_TCSS (0x1a << 16)
136#define DATAFLASH_TCHS (0x1 << 24)
137
138/* NOR flash, if populated */
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200139#ifdef CONFIG_SYS_USE_NORFLASH
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_FLASH_CFI 1
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200141#define CONFIG_FLASH_CFI_DRIVER 1
142#define PHYS_FLASH_1 0x10000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
144#define CONFIG_SYS_MAX_FLASH_SECT 256
145#define CONFIG_SYS_MAX_FLASH_BANKS 1
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200146
147#define CONFIG_SYS_MONITOR_SEC 1:0-3
148#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
149#define CONFIG_SYS_MONITOR_LEN (256 << 10)
150#define CONFIG_ENV_IS_IN_FLASH 1
151#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007FE000)
152#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE)
153
154/* Address and size of Primary Environment Sector */
155#define CONFIG_ENV_SIZE 0x2000
156
157#define xstr(s) str(s)
158#define str(s) #s
159
160#define CONFIG_EXTRA_ENV_SETTINGS \
161 "monitor_base=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
162 "update=" \
163 "protect off ${monitor_base} +${filesize};" \
164 "erase ${monitor_base} +${filesize};" \
165 "cp.b ${load_addr} ${monitor_base} ${filesize};" \
166 "protect on ${monitor_base} +${filesize}\0"
167
168#ifndef CONFIG_SKIP_LOWLEVEL_INIT
169#define MASTER_PLL_MUL 171
170#define MASTER_PLL_DIV 14
Jens Scharsig1b34f002010-02-03 22:47:18 +0100171#define MASTER_PLL_OUT 3
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200172
173/* clocks */
174#define CONFIG_SYS_MOR_VAL \
Jens Scharsig1b34f002010-02-03 22:47:18 +0100175 (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255))
176#define CONFIG_SYS_PLLAR_VAL \
177 (AT91_PMC_PLLAR_29 | \
178 AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \
179 AT91_PMC_PLLXR_PLLCOUNT(63) | \
180 AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \
181 AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV))
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200182
183/* PCK/2 = MCK Master Clock from PLLA */
184#define CONFIG_SYS_MCKR1_VAL \
Jens Scharsig1b34f002010-02-03 22:47:18 +0100185 (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \
186 AT91_PMC_MCKR_MDIV_2)
187
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200188/* PCK/2 = MCK Master Clock from PLLA */
189#define CONFIG_SYS_MCKR2_VAL \
Jens Scharsig1b34f002010-02-03 22:47:18 +0100190 (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \
191 AT91_PMC_MCKR_MDIV_2)
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200192
193/* define PDC[31:16] as DATA[31:16] */
194#define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000
195/* no pull-up for D[31:16] */
196#define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000
197/* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */
Jens Scharsig1b34f002010-02-03 22:47:18 +0100198#define CONFIG_SYS_MATRIX_EBICSA_VAL \
199 (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \
200 AT91_MATRIX_CSA_EBI_CS1A)
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200201
202/* SDRAM */
203/* SDRAMC_MR Mode register */
204#define CONFIG_SYS_SDRC_MR_VAL1 0
205/* SDRAMC_TR - Refresh Timer register */
206#define CONFIG_SYS_SDRC_TR_VAL1 0x13C
207/* SDRAMC_CR - Configuration register*/
208#define CONFIG_SYS_SDRC_CR_VAL \
209 (AT91_SDRAMC_NC_9 | \
210 AT91_SDRAMC_NR_13 | \
211 AT91_SDRAMC_NB_4 | \
212 AT91_SDRAMC_CAS_3 | \
213 AT91_SDRAMC_DBW_32 | \
214 (1 << 8) | /* Write Recovery Delay */ \
215 (7 << 12) | /* Row Cycle Delay */ \
216 (2 << 16) | /* Row Precharge Delay */ \
217 (2 << 20) | /* Row to Column Delay */ \
218 (5 << 24) | /* Active to Precharge Delay */ \
219 (1 << 28)) /* Exit Self Refresh to Active Delay */
220
221/* Memory Device Register -> SDRAM */
222#define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM
223#define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE
224#define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */
225#define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH
226#define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */
227#define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */
228#define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */
229#define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */
230#define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */
231#define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */
232#define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */
233#define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */
234#define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR
235#define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */
236#define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL
237#define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */
238#define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */
239#define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */
240
241/* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */
Jens Scharsig1b34f002010-02-03 22:47:18 +0100242#define CONFIG_SYS_SMC0_SETUP0_VAL \
243 (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \
244 AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10))
245#define CONFIG_SYS_SMC0_PULSE0_VAL \
246 (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \
247 AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11))
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200248#define CONFIG_SYS_SMC0_CYCLE0_VAL \
Jens Scharsig1b34f002010-02-03 22:47:18 +0100249 (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22))
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200250#define CONFIG_SYS_SMC0_MODE0_VAL \
Jens Scharsig1b34f002010-02-03 22:47:18 +0100251 (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \
252 AT91_SMC_MODE_DBW_16 | \
253 AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6))
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200254
255/* user reset enable */
256#define CONFIG_SYS_RSTC_RMR_VAL \
257 (AT91_RSTC_KEY | \
Jens Scharsig1b34f002010-02-03 22:47:18 +0100258 AT91_RSTC_MR_URSTEN | \
259 AT91_RSTC_MR_ERSTL(15))
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200260
261/* Disable Watchdog */
262#define CONFIG_SYS_WDTC_WDMR_VAL \
Jens Scharsig1b34f002010-02-03 22:47:18 +0100263 (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \
264 AT91_WDT_MR_WDV(0xfff) | \
265 AT91_WDT_MR_WDDIS | \
266 AT91_WDT_MR_WDD(0xfff))
267
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200268#endif
269
270#else
271#define CONFIG_SYS_NO_FLASH 1
Stelian Pop8e429b32008-05-08 18:52:23 +0200272#endif
273
274/* NAND flash */
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +0100275#ifdef CONFIG_CMD_NAND
276#define CONFIG_NAND_ATMEL
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_MAX_NAND_DEVICE 1
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000278#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_NAND_DBW_8 1
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +0100280/* our ALE is AD21 */
281#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
282/* our CLE is AD22 */
283#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000284#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15
285#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22
Jens Scharsig1b34f002010-02-03 22:47:18 +0100286
287#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
Jean-Christophe PLAGNIOL-VILLARD74c076d2009-03-22 10:22:34 +0100288#endif
Stelian Pop8e429b32008-05-08 18:52:23 +0200289
290/* Ethernet */
291#define CONFIG_MACB 1
292#define CONFIG_RMII 1
293#define CONFIG_NET_MULTI 1
294#define CONFIG_NET_RETRY_COUNT 20
295#define CONFIG_RESET_PHY_R 1
296
297/* USB */
Jean-Christophe PLAGNIOL-VILLARD2b7178a2009-03-27 23:26:44 +0100298#define CONFIG_USB_ATMEL
Stelian Pop8e429b32008-05-08 18:52:23 +0200299#define CONFIG_USB_OHCI_NEW 1
Stelian Pop8e429b32008-05-08 18:52:23 +0200300#define CONFIG_DOS_PARTITION 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
302#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */
303#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263"
304#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Stelian Pop8e429b32008-05-08 18:52:23 +0200305#define CONFIG_USB_STORAGE 1
Stelian Pop3e0cda02008-11-09 00:14:46 +0100306#define CONFIG_CMD_FAT 1
Stelian Pop8e429b32008-05-08 18:52:23 +0200307
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
Stelian Pop8e429b32008-05-08 18:52:23 +0200309
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000310#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_MEMTEST_END 0x23e00000
Stelian Pop8e429b32008-05-08 18:52:23 +0200312
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#ifdef CONFIG_SYS_USE_DATAFLASH
Stelian Pop8e429b32008-05-08 18:52:23 +0200314
315/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Jean-Christophe PLAGNIOL-VILLARD057c8492008-09-10 22:47:58 +0200316#define CONFIG_ENV_IS_IN_DATAFLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200318#define CONFIG_ENV_OFFSET 0x4200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200320#define CONFIG_ENV_SIZE 0x4200
Stelian Pop8e429b32008-05-08 18:52:23 +0200321#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
322#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
323 "root=/dev/mtdblock0 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200324 "mtdparts=atmel_nand:-(root) "\
Stelian Pop8e429b32008-05-08 18:52:23 +0200325 "rw rootfstype=jffs2"
326
Jean-Christophe PLAGNIOL-VILLARD1b3b7c62009-06-13 12:48:36 +0200327#elif CONFIG_SYS_USE_NANDFLASH
Stelian Pop8e429b32008-05-08 18:52:23 +0200328
329/* bootstrap + u-boot + env + linux in nandflash */
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000330#define CONFIG_ENV_IS_IN_NAND 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200331#define CONFIG_ENV_OFFSET 0x60000
332#define CONFIG_ENV_OFFSET_REDUND 0x80000
333#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
Stelian Pop8e429b32008-05-08 18:52:23 +0200334#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
335#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
336 "root=/dev/mtdblock5 " \
Albin Tonnerre918319c2009-07-22 18:30:03 +0200337 "mtdparts=atmel_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \
Stelian Pop8e429b32008-05-08 18:52:23 +0200338 "rw rootfstype=jffs2"
339
340#endif
341
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_PROMPT "U-Boot> "
343#define CONFIG_SYS_CBSIZE 256
344#define CONFIG_SYS_MAXARGS 16
345#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
346#define CONFIG_SYS_LONGHELP 1
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000347#define CONFIG_CMDLINE_EDITING 1
Jean-Christophe PLAGNIOL-VILLARD03bab002009-03-30 16:51:40 +0200348#define CONFIG_AUTO_COMPLETE
349#define CONFIG_SYS_HUSH_PARSER
350#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Stelian Pop8e429b32008-05-08 18:52:23 +0200351
Stelian Pop8e429b32008-05-08 18:52:23 +0200352/*
353 * Size of malloc() pool
354 */
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000355#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
Stelian Pop8e429b32008-05-08 18:52:23 +0200356
357#define CONFIG_STACKSIZE (32*1024) /* regular stack */
358
Xu, Hongcd46b0f2011-06-10 21:31:26 +0000359#undef CONFIG_USE_IRQ
Stelian Pop8e429b32008-05-08 18:52:23 +0200360
361#endif