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wdenk54387ac2003-10-08 22:45:44 +00001/*
2 * Copyright (C) 2003 Arabella Software Ltd.
3 * Yuli Barcohen <yuli@arabellasw.com>
4 *
5 * U-Boot configuration for Zephyr Engineering ZPC.1900 board.
6 * This port was developed and tested on Revision C board.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
31#define CONFIG_ZPC1900 1 /* ...on Zephyr ZPC.1900 board */
32#define CPU_ID_STR "MPC8265"
33
34#undef DEBUG
35
wdenkc837dcb2004-01-20 23:12:12 +000036#undef CONFIG_BOARD_EARLY_INIT_F /* Don't call board_early_init_f */
wdenk54387ac2003-10-08 22:45:44 +000037
38/* Allow serial number (serial) and MAC address (ethaddr) to be overwritten */
39#define CONFIG_ENV_OVERWRITE
40
41/*
42 * Select serial console configuration
43 *
44 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
45 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
46 * for SCC).
47 */
48#define CONFIG_CONS_ON_SMC /* Console is on SMC */
49#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
50#undef CONFIG_CONS_NONE /* It's not on external UART */
51#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
52
53/*
54 * Select ethernet configuration
55 *
56 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
57 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
58 * SCC, 1-3 for FCC)
59 *
60 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
61 * must be defined elsewhere (as for the console), or CFG_CMD_NET must
62 * be removed from CONFIG_COMMANDS to remove support for networking.
63 */
64#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
65#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
66#undef CONFIG_ETHER_NONE /* No external Ethernet */
67
68#ifdef CONFIG_ETHER_ON_FCC
69
70#define CONFIG_ETHER_INDEX 2 /* FCC2 is used for Ethernet */
71
72#if (CONFIG_ETHER_INDEX == 2)
73/*
74 * - Rx clock is CLK13
75 * - Tx clock is CLK14
76 * - Select bus for bd/buffers (see 28-13)
77 * - Full duplex
78 */
79# define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
80# define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
81# define CFG_CPMFCR_RAMTYPE 0
82# define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
83
84#endif /* CONFIG_ETHER_INDEX */
85
86#define CONFIG_MII /* MII PHY management */
87#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
88/*
89 * GPIO pins used for bit-banged MII communications
90 */
91#define MDIO_PORT 2 /* Port C */
92#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
93#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
94#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
95
96#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
97 else iop->pdat &= ~0x00400000
98
99#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
100 else iop->pdat &= ~0x00200000
101
102#define MIIDELAY udelay(1)
103
104#endif /* CONFIG_ETHER_ON_FCC */
105
106#ifndef CONFIG_8260_CLKIN
107#define CONFIG_8260_CLKIN 66666666 /* in Hz */
108#endif
109
110#define CONFIG_BAUDRATE 9600
111
112#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
113 CFG_CMD_BEDBUG | \
114 CFG_CMD_BMP | \
115 CFG_CMD_BSP | \
116 CFG_CMD_DATE | \
117 CFG_CMD_DOC | \
118 CFG_CMD_DTT | \
119 CFG_CMD_EEPROM | \
120 CFG_CMD_ELF | \
121 CFG_CMD_FAT | \
122 CFG_CMD_FDC | \
123 CFG_CMD_FDOS | \
124 CFG_CMD_HWFLOW | \
125 CFG_CMD_I2C | \
126 CFG_CMD_IDE | \
127 CFG_CMD_JFFS2 | \
128 CFG_CMD_KGDB | \
129 CFG_CMD_MMC | \
130 CFG_CMD_NAND | \
131 CFG_CMD_PCI | \
132 CFG_CMD_PCMCIA | \
wdenkb79a11c2004-03-25 15:14:43 +0000133 CFG_CMD_REISER | \
wdenk54387ac2003-10-08 22:45:44 +0000134 CFG_CMD_SCSI | \
135 CFG_CMD_SPI | \
136 CFG_CMD_USB | \
137 CFG_CMD_VFD ) )
138
139/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
140#include <cmd_confdefs.h>
141
142#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
143#define CONFIG_BOOTCOMMAND "dhcp;bootm" /* autoboot command */
144#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=:::::eth0:dhcp"
145
146#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
147#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
148#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
149#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
150#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
151#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
152#endif
153
154#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
155#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
156
157/*
158 * Miscellaneous configurable options
159 */
160#define CFG_HUSH_PARSER
161#define CFG_PROMPT_HUSH_PS2 "> "
162#define CFG_LONGHELP /* undef to save memory */
163#define CFG_PROMPT "=> " /* Monitor Command Prompt */
164#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
165#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
166#else
167#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
168#endif
169#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
170#define CFG_MAXARGS 16 /* max number of command args */
171#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
172
173#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
174#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
175
176#define CFG_LOAD_ADDR 0x100000 /* default load address */
177
178#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
179
180#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
181
182#define CFG_FLASH_BASE 0xFFE00000
183#define CFG_FLASH_CFI
184#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
185#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
186
187#define CFG_DEFAULT_IMMR 0x0F010000
188
189#define CFG_IMMR 0xF0000000
190#define CFG_SDRAM_BASE 0x00000000
191#define CFG_SDRAM_SIZE 64
192#define CFG_FLSIMM_BASE 0xFC000000
193#define CFG_LSDRAM_BASE 0xFE000000
194#define CFG_BCSR 0xFEA00000
195#define CFG_EEPROM 0xFEB00000
196
197#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
198
199#define BCSR_PCI_MODE 0x01
200
201#define CFG_INIT_RAM_ADDR CFG_IMMR
202#define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
203#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
204#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
205#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
206
207/* Hard reset configuration word */
208#define CFG_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 |\
209 HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB010 |\
210 HRCW_APPC10 |\
211 HRCW_MODCK_H0101 \
212 ) /* 0x14820205 */
213/* No slaves */
214#define CFG_HRCW_SLAVE1 0
215#define CFG_HRCW_SLAVE2 0
216#define CFG_HRCW_SLAVE3 0
217#define CFG_HRCW_SLAVE4 0
218#define CFG_HRCW_SLAVE5 0
219#define CFG_HRCW_SLAVE6 0
220#define CFG_HRCW_SLAVE7 0
221
222#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
223#define BOOTFLAG_WARM 0x02 /* Software reboot */
224
225#define CFG_MONITOR_BASE TEXT_BASE
226#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
227#define CFG_RAMBOOT
228#endif
229
230#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
231#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
232#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
233
234#if !defined(CFG_ENV_IS_IN_FLASH) && !defined(CFG_ENV_IS_IN_NVRAM)
235#define CFG_ENV_IS_IN_NVRAM 1
236#endif
237
238#ifdef CFG_ENV_IS_IN_FLASH
239# define CFG_ENV_SECT_SIZE 0x10000
240# define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE)
241#else
242# define CFG_ENV_ADDR (CFG_EEPROM + 0x400)
243# define CFG_ENV_SIZE 0x200
244# define CFG_NVRAM_ACCESS_ROUTINE
245#endif
246
247#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */
248#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
249# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
250#endif
251
252#define CFG_HID0_INIT 0
253#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
254
255#define CFG_HID2 0
256
257#define CFG_SIUMCR 0x42200000
258#define CFG_SYPCR 0xFFFFFFC3
259#define CFG_BCR 0x90400000
260#define CFG_SCCR SCCR_DFBRG01
261
262#define CFG_RMR RMR_CSRE
263#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
264#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
265#define CFG_RCCR 0
266
267#define CFG_PSDMR 0x014EB45A
268#define CFG_PSRT 0x0C
269#define CFG_LSDMR 0x008AB552
270#define CFG_LSRT 0x0E
271#define CFG_MPTPR 0x4000
272
273#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00000801
274#define CFG_OR0_PRELIM 0xFFE00856
275#define CFG_BR5_PRELIM CFG_EEPROM | 0x00000801
276#define CFG_OR5_PRELIM 0xFFFF03F6
277#define CFG_BR6_PRELIM CFG_FLSIMM_BASE | 0x00000801
278#define CFG_OR6_PRELIM 0xFE000856
279#define CFG_BR7_PRELIM CFG_BCSR | 0x00000801
280#define CFG_OR7_PRELIM 0xFFFF83F6
281
282#define CFG_RESET_ADDRESS 0xC0000000
283
284#endif /* __CONFIG_H */