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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / b8bf55399273a7aba597b5687ef2180ec1d24122 / . / arch / arm / dts / zynqmp-ep108.dts
blob: ee9d0fe7a432a58f934733d6a1f44081aa0d7905 [file] [log] [blame]
Michal Simek44303df2015-10-30 15:39:18 +0100[diff] [blame]1/*
2 * dts file for Xilinx ZynqMP ep108 development board
3 *
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11/dts-v1/;
12
Alistair Francis02e782c2016-02-25 09:30:03 -0800[diff] [blame]13#include "zynqmp.dtsi"
14#include "zynqmp-ep108-clk.dtsi"
Michal Simek44303df2015-10-30 15:39:18 +0100[diff] [blame]15
16/ {
17 model = "ZynqMP EP108";
18
19 aliases {
Michal Simekbeaf7952016-02-23 09:30:15 +0100[diff] [blame]20 mmc0 = &sdhci0;
21 mmc1 = &sdhci1;
Michal Simek44303df2015-10-30 15:39:18 +0100[diff] [blame]22 serial0 = &uart0;
23 spi0 = &qspi;
24 spi1 = &spi0;
25 spi2 = &spi1;
26 };
27
28 chosen {
29 stdout-path = "serial0:115200n8";
30 };
31
32 memory {
33 device_type = "memory";
34 reg = <0x0 0x0 0x40000000>;
35 };
36};
37
38&can0 {
39 status = "okay";
40};
41
42&gem0 {
43 status = "okay";
44 phy-handle = <&phy0>;
45 phy-mode = "rgmii-id";
Michal Simekcb9dcc62016-01-14 13:11:51 +0100[diff] [blame]46 phy0: phy@0 {
Michal Simek44303df2015-10-30 15:39:18 +0100[diff] [blame]47 reg = <0>;
48 max-speed = <100>;
49 };
50};
51
52&gpio {
53 status = "okay";
54};
55
56&i2c0 {
57 status = "okay";
58 clock-frequency = <400000>;
59 eeprom@54 {
60 compatible = "at,24c64";
61 reg = <0x54>;
62 };
63};
64
65&i2c1 {
66 status = "okay";
67 clock-frequency = <400000>;
68 eeprom@55 {
69 compatible = "at,24c64";
70 reg = <0x55>;
71 };
72};
73
74&qspi {
75 status = "okay";
76 flash@0 {
Ranjit Waghmodeeaae2b52015-12-02 10:06:58 +0530[diff] [blame]77 compatible = "m25p80";
Michal Simek44303df2015-10-30 15:39:18 +0100[diff] [blame]78 #address-cells = <1>;
79 #size-cells = <1>;
80 reg = <0x0>;
81 spi-tx-bus-width = <1>;
82 spi-rx-bus-width = <4>;
83 spi-max-frequency = <10000000>;
84 partition@qspi-fsbl-uboot { /* for testing purpose */
85 label = "qspi-fsbl-uboot";
86 reg = <0x0 0x100000>;
87 };
88 partition@qspi-linux { /* for testing purpose */
89 label = "qspi-linux";
90 reg = <0x100000 0x500000>;
91 };
92 partition@qspi-device-tree { /* for testing purpose */
93 label = "qspi-device-tree";
94 reg = <0x600000 0x20000>;
95 };
96 partition@qspi-rootfs { /* for testing purpose */
97 label = "qspi-rootfs";
98 reg = <0x620000 0x5E0000>;
99 };
100 };
101};
102
103&sata {
104 status = "okay";
105 ceva,broken-gen2;
106};
107
108&sdhci0 {
109 status = "okay";
P L Sai Krishnab8bf5532016-01-07 14:57:27 +0530[diff] [blame^]110 bus-width = <8>;
Michal Simek44303df2015-10-30 15:39:18 +0100[diff] [blame]111};
112
113&sdhci1 {
114 status = "okay";
115};
116
117&spi0 {
118 status = "okay";
119 num-cs = <1>;
120 spi0_flash0: spi0_flash0@0 {
121 compatible = "m25p80";
122 #address-cells = <1>;
123 #size-cells = <1>;
124 spi-max-frequency = <50000000>;
125 reg = <0>;
126
127 spi0_flash0@00000000 {
128 label = "spi0_flash0";
129 reg = <0x0 0x100000>;
130 };
131 };
132};
133
134&spi1 {
135 status = "okay";
136 num-cs = <1>;
137 spi1_flash0: spi1_flash0@0 {
138 compatible = "m25p80";
139 #address-cells = <1>;
140 #size-cells = <1>;
141 spi-max-frequency = <50000000>;
142 reg = <0>;
143
144 spi1_flash0@00000000 {
145 label = "spi1_flash0";
146 reg = <0x0 0x100000>;
147 };
148 };
149};
150
151&uart0 {
152 status = "okay";
153};
154
155&usb0 {
156 status = "okay";
157 dr_mode = "peripheral";
158 maximum-speed = "high-speed";
159};
160
161&usb1 {
162 status = "okay";
163 dr_mode = "host";
164 maximum-speed = "high-speed";
165};
166
167&watchdog0 {
168 status = "okay";
169};
170
171&xlnx_dp {
172 xlnx,max-pclock-frequency = <200000>;
173};
174
175&xlnx_dpdma {
176 xlnx,axi-clock-freq = <200000000>;
177};