| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2003 Arabella Software Ltd. |
| 4 | * Yuli Barcohen <yuli@arabellasw.com> |
| 5 | * |
| 6 | * Serial Presence Detect (SPD) EEPROM format according to the |
| 7 | * Intel's PC SDRAM Serial Presence Detect (SPD) Specification, |
| 8 | * revision 1.2B, November 1999 |
| wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #ifndef _SPD_H_ |
| 12 | #define _SPD_H_ |
| 13 | |
| 14 | typedef struct spd_eeprom_s { |
| Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 15 | unsigned char info_size; /* 0 # bytes written into serial memory */ |
| 16 | unsigned char chip_size; /* 1 Total # bytes of SPD memory device */ |
| 17 | unsigned char mem_type; /* 2 Fundamental memory type */ |
| 18 | unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */ |
| 19 | unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */ |
| 20 | unsigned char nrows; /* 5 # of Module Rows on this assembly */ |
| 21 | unsigned char dataw_lsb; /* 6 Data Width of this assembly */ |
| 22 | unsigned char dataw_msb; /* 7 ... Data Width continuation */ |
| 23 | unsigned char voltage; /* 8 Voltage intf std of this assembly */ |
| 24 | unsigned char clk_cycle; /* 9 SDRAM Cycle time at CL=X */ |
| 25 | unsigned char clk_access; /* 10 SDRAM Access from Clock at CL=X */ |
| 26 | unsigned char config; /* 11 DIMM Configuration type */ |
| 27 | unsigned char refresh; /* 12 Refresh Rate/Type */ |
| 28 | unsigned char primw; /* 13 Primary SDRAM Width */ |
| 29 | unsigned char ecw; /* 14 Error Checking SDRAM width */ |
| 30 | unsigned char min_delay; /* 15 for Back to Back Random Address */ |
| 31 | unsigned char burstl; /* 16 Burst Lengths Supported */ |
| 32 | unsigned char nbanks; /* 17 # of Banks on Each SDRAM Device */ |
| 33 | unsigned char cas_lat; /* 18 CAS# Latencies Supported */ |
| 34 | unsigned char cs_lat; /* 19 CS# Latency */ |
| 35 | unsigned char write_lat; /* 20 Write Latency (aka Write Recovery) */ |
| 36 | unsigned char mod_attr; /* 21 SDRAM Module Attributes */ |
| 37 | unsigned char dev_attr; /* 22 SDRAM Device Attributes */ |
| 38 | unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time at CL=X-1 */ |
| 39 | unsigned char clk_access2; /* 24 SDRAM Access from Clock at CL=X-1 */ |
| 40 | unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time at CL=X-2 */ |
| 41 | unsigned char clk_access3; /* 26 Max Access from Clock at CL=X-2 */ |
| 42 | unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ |
| 43 | unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */ |
| 44 | unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ |
| 45 | unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */ |
| 46 | unsigned char row_dens; /* 31 Density of each row on module */ |
| 47 | unsigned char ca_setup; /* 32 Cmd + Addr signal input setup time */ |
| 48 | unsigned char ca_hold; /* 33 Cmd and Addr signal input hold time */ |
| 49 | unsigned char data_setup; /* 34 Data signal input setup time */ |
| 50 | unsigned char data_hold; /* 35 Data signal input hold time */ |
| 51 | unsigned char twr; /* 36 Write Recovery time tWR */ |
| 52 | unsigned char twtr; /* 37 Int write to read delay tWTR */ |
| 53 | unsigned char trtp; /* 38 Int read to precharge delay tRTP */ |
| 54 | unsigned char mem_probe; /* 39 Mem analysis probe characteristics */ |
| 55 | unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */ |
| 56 | unsigned char trc; /* 41 Min Active to Auto refresh time tRC */ |
| 57 | unsigned char trfc; /* 42 Min Auto to Active period tRFC */ |
| 58 | unsigned char tckmax; /* 43 Max device cycle time tCKmax */ |
| 59 | unsigned char tdqsq; /* 44 Max DQS to DQ skew */ |
| 60 | unsigned char tqhs; /* 45 Max Read DataHold skew tQHS */ |
| 61 | unsigned char pll_relock; /* 46 PLL Relock time */ |
| 62 | unsigned char res[15]; /* 47-xx IDD in SPD and Reserved space */ |
| 63 | unsigned char spd_rev; /* 62 SPD Data Revision Code */ |
| 64 | unsigned char cksum; /* 63 Checksum for bytes 0-62 */ |
| 65 | unsigned char mid[8]; /* 64 Mfr's JEDEC ID code per JEP-108E */ |
| 66 | unsigned char mloc; /* 72 Manufacturing Location */ |
| 67 | unsigned char mpart[18]; /* 73 Manufacturer's Part Number */ |
| 68 | unsigned char rev[2]; /* 91 Revision Code */ |
| 69 | unsigned char mdate[2]; /* 93 Manufacturing Date */ |
| 70 | unsigned char sernum[4]; /* 95 Assembly Serial Number */ |
| 71 | unsigned char mspec[27]; /* 99 Manufacturer Specific Data */ |
| 72 | |
| 73 | /* |
| 74 | * Open for Customer Use starting with byte 128. |
| 75 | */ |
| 76 | unsigned char freq; /* 128 Intel spec: frequency */ |
| 77 | unsigned char intel_cas; /* 129 Intel spec: CAS# Latency support */ |
| wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 78 | } spd_eeprom_t; |
| 79 | |
| Jon Loeliger | d9b94f2 | 2005-07-25 14:05:07 -0500 | [diff] [blame] | 80 | |
| 81 | /* |
| 82 | * Byte 2 Fundamental Memory Types. |
| 83 | */ |
| 84 | #define SPD_MEMTYPE_FPM (0x01) |
| 85 | #define SPD_MEMTYPE_EDO (0x02) |
| 86 | #define SPD_MEMTYPE_PIPE_NIBBLE (0x03) |
| 87 | #define SPD_MEMTYPE_SDRAM (0x04) |
| 88 | #define SPD_MEMTYPE_ROM (0x05) |
| 89 | #define SPD_MEMTYPE_SGRAM (0x06) |
| 90 | #define SPD_MEMTYPE_DDR (0x07) |
| 91 | #define SPD_MEMTYPE_DDR2 (0x08) |
| 92 | |
| wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 93 | #endif /* _SPD_H_ */ |