Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010 |
| 3 | * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com. |
| 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | /* |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 9 | * Designware ethernet IP driver for U-Boot |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #include <common.h> |
Patrice Chotard | ba1f966 | 2017-11-29 09:06:11 +0100 | [diff] [blame^] | 13 | #include <clk.h> |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 14 | #include <dm.h> |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 15 | #include <errno.h> |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 16 | #include <miiphy.h> |
| 17 | #include <malloc.h> |
Bin Meng | 8b7ee66 | 2015-09-11 03:24:35 -0700 | [diff] [blame] | 18 | #include <pci.h> |
Stefan Roese | ef76025 | 2012-05-07 12:04:25 +0200 | [diff] [blame] | 19 | #include <linux/compiler.h> |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 20 | #include <linux/err.h> |
| 21 | #include <asm/io.h> |
Jacob Chen | 6ec922f | 2017-03-27 16:54:17 +0800 | [diff] [blame] | 22 | #include <power/regulator.h> |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 23 | #include "designware.h" |
| 24 | |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 25 | DECLARE_GLOBAL_DATA_PTR; |
| 26 | |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 27 | static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) |
| 28 | { |
Sjoerd Simons | 90b7fc9 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 29 | #ifdef CONFIG_DM_ETH |
| 30 | struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); |
| 31 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
| 32 | #else |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 33 | struct eth_mac_regs *mac_p = bus->priv; |
Sjoerd Simons | 90b7fc9 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 34 | #endif |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 35 | ulong start; |
| 36 | u16 miiaddr; |
| 37 | int timeout = CONFIG_MDIO_TIMEOUT; |
| 38 | |
| 39 | miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | |
| 40 | ((reg << MIIREGSHIFT) & MII_REGMSK); |
| 41 | |
| 42 | writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); |
| 43 | |
| 44 | start = get_timer(0); |
| 45 | while (get_timer(start) < timeout) { |
| 46 | if (!(readl(&mac_p->miiaddr) & MII_BUSY)) |
| 47 | return readl(&mac_p->miidata); |
| 48 | udelay(10); |
| 49 | }; |
| 50 | |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 51 | return -ETIMEDOUT; |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 52 | } |
| 53 | |
| 54 | static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, |
| 55 | u16 val) |
| 56 | { |
Sjoerd Simons | 90b7fc9 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 57 | #ifdef CONFIG_DM_ETH |
| 58 | struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv); |
| 59 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
| 60 | #else |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 61 | struct eth_mac_regs *mac_p = bus->priv; |
Sjoerd Simons | 90b7fc9 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 62 | #endif |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 63 | ulong start; |
| 64 | u16 miiaddr; |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 65 | int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT; |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 66 | |
| 67 | writel(val, &mac_p->miidata); |
| 68 | miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) | |
| 69 | ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE; |
| 70 | |
| 71 | writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr); |
| 72 | |
| 73 | start = get_timer(0); |
| 74 | while (get_timer(start) < timeout) { |
| 75 | if (!(readl(&mac_p->miiaddr) & MII_BUSY)) { |
| 76 | ret = 0; |
| 77 | break; |
| 78 | } |
| 79 | udelay(10); |
| 80 | }; |
| 81 | |
| 82 | return ret; |
| 83 | } |
| 84 | |
Alexey Brodkin | 66d027e | 2016-06-27 13:17:51 +0300 | [diff] [blame] | 85 | #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) |
Sjoerd Simons | 90b7fc9 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 86 | static int dw_mdio_reset(struct mii_dev *bus) |
| 87 | { |
| 88 | struct udevice *dev = bus->priv; |
| 89 | struct dw_eth_dev *priv = dev_get_priv(dev); |
| 90 | struct dw_eth_pdata *pdata = dev_get_platdata(dev); |
| 91 | int ret; |
| 92 | |
| 93 | if (!dm_gpio_is_valid(&priv->reset_gpio)) |
| 94 | return 0; |
| 95 | |
| 96 | /* reset the phy */ |
| 97 | ret = dm_gpio_set_value(&priv->reset_gpio, 0); |
| 98 | if (ret) |
| 99 | return ret; |
| 100 | |
| 101 | udelay(pdata->reset_delays[0]); |
| 102 | |
| 103 | ret = dm_gpio_set_value(&priv->reset_gpio, 1); |
| 104 | if (ret) |
| 105 | return ret; |
| 106 | |
| 107 | udelay(pdata->reset_delays[1]); |
| 108 | |
| 109 | ret = dm_gpio_set_value(&priv->reset_gpio, 0); |
| 110 | if (ret) |
| 111 | return ret; |
| 112 | |
| 113 | udelay(pdata->reset_delays[2]); |
| 114 | |
| 115 | return 0; |
| 116 | } |
| 117 | #endif |
| 118 | |
| 119 | static int dw_mdio_init(const char *name, void *priv) |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 120 | { |
| 121 | struct mii_dev *bus = mdio_alloc(); |
| 122 | |
| 123 | if (!bus) { |
| 124 | printf("Failed to allocate MDIO bus\n"); |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 125 | return -ENOMEM; |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 126 | } |
| 127 | |
| 128 | bus->read = dw_mdio_read; |
| 129 | bus->write = dw_mdio_write; |
Ben Whitten | 192bc69 | 2015-12-30 13:05:58 +0000 | [diff] [blame] | 130 | snprintf(bus->name, sizeof(bus->name), "%s", name); |
Alexey Brodkin | 66d027e | 2016-06-27 13:17:51 +0300 | [diff] [blame] | 131 | #if defined(CONFIG_DM_ETH) && defined(CONFIG_DM_GPIO) |
Sjoerd Simons | 90b7fc9 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 132 | bus->reset = dw_mdio_reset; |
| 133 | #endif |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 134 | |
Sjoerd Simons | 90b7fc9 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 135 | bus->priv = priv; |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 136 | |
| 137 | return mdio_register(bus); |
| 138 | } |
Vipin Kumar | 13edd17 | 2012-03-26 00:09:56 +0000 | [diff] [blame] | 139 | |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 140 | static void tx_descs_init(struct dw_eth_dev *priv) |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 141 | { |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 142 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
| 143 | struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0]; |
| 144 | char *txbuffs = &priv->txbuffs[0]; |
| 145 | struct dmamacdescr *desc_p; |
| 146 | u32 idx; |
| 147 | |
| 148 | for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) { |
| 149 | desc_p = &desc_table_p[idx]; |
Beniamino Galvani | 0e1a3e3 | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 150 | desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE]; |
| 151 | desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 152 | |
| 153 | #if defined(CONFIG_DW_ALTDESCRIPTOR) |
| 154 | desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST | |
Marek Vasut | 2b26109 | 2015-12-20 03:59:23 +0100 | [diff] [blame] | 155 | DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS | |
| 156 | DESC_TXSTS_TXCHECKINSCTRL | |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 157 | DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS); |
| 158 | |
| 159 | desc_p->txrx_status |= DESC_TXSTS_TXCHAIN; |
| 160 | desc_p->dmamac_cntl = 0; |
| 161 | desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA); |
| 162 | #else |
| 163 | desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN; |
| 164 | desc_p->txrx_status = 0; |
| 165 | #endif |
| 166 | } |
| 167 | |
| 168 | /* Correcting the last pointer of the chain */ |
Beniamino Galvani | 0e1a3e3 | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 169 | desc_p->dmamac_next = (ulong)&desc_table_p[0]; |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 170 | |
Alexey Brodkin | 50b0df8 | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 171 | /* Flush all Tx buffer descriptors at once */ |
Beniamino Galvani | 0e1a3e3 | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 172 | flush_dcache_range((ulong)priv->tx_mac_descrtable, |
| 173 | (ulong)priv->tx_mac_descrtable + |
Alexey Brodkin | 50b0df8 | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 174 | sizeof(priv->tx_mac_descrtable)); |
| 175 | |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 176 | writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr); |
Alexey Brodkin | 74cb708 | 2014-01-13 13:28:38 +0400 | [diff] [blame] | 177 | priv->tx_currdescnum = 0; |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 178 | } |
| 179 | |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 180 | static void rx_descs_init(struct dw_eth_dev *priv) |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 181 | { |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 182 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
| 183 | struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0]; |
| 184 | char *rxbuffs = &priv->rxbuffs[0]; |
| 185 | struct dmamacdescr *desc_p; |
| 186 | u32 idx; |
| 187 | |
Alexey Brodkin | 50b0df8 | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 188 | /* Before passing buffers to GMAC we need to make sure zeros |
| 189 | * written there right after "priv" structure allocation were |
| 190 | * flushed into RAM. |
| 191 | * Otherwise there's a chance to get some of them flushed in RAM when |
| 192 | * GMAC is already pushing data to RAM via DMA. This way incoming from |
| 193 | * GMAC data will be corrupted. */ |
Beniamino Galvani | 0e1a3e3 | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 194 | flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE); |
Alexey Brodkin | 50b0df8 | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 195 | |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 196 | for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) { |
| 197 | desc_p = &desc_table_p[idx]; |
Beniamino Galvani | 0e1a3e3 | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 198 | desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE]; |
| 199 | desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1]; |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 200 | |
| 201 | desc_p->dmamac_cntl = |
Marek Vasut | 2b26109 | 2015-12-20 03:59:23 +0100 | [diff] [blame] | 202 | (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) | |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 203 | DESC_RXCTRL_RXCHAIN; |
| 204 | |
| 205 | desc_p->txrx_status = DESC_RXSTS_OWNBYDMA; |
| 206 | } |
| 207 | |
| 208 | /* Correcting the last pointer of the chain */ |
Beniamino Galvani | 0e1a3e3 | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 209 | desc_p->dmamac_next = (ulong)&desc_table_p[0]; |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 210 | |
Alexey Brodkin | 50b0df8 | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 211 | /* Flush all Rx buffer descriptors at once */ |
Beniamino Galvani | 0e1a3e3 | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 212 | flush_dcache_range((ulong)priv->rx_mac_descrtable, |
| 213 | (ulong)priv->rx_mac_descrtable + |
Alexey Brodkin | 50b0df8 | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 214 | sizeof(priv->rx_mac_descrtable)); |
| 215 | |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 216 | writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr); |
Alexey Brodkin | 74cb708 | 2014-01-13 13:28:38 +0400 | [diff] [blame] | 217 | priv->rx_currdescnum = 0; |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 218 | } |
| 219 | |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 220 | static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id) |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 221 | { |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 222 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
| 223 | u32 macid_lo, macid_hi; |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 224 | |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 225 | macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) + |
| 226 | (mac_id[3] << 24); |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 227 | macid_hi = mac_id[4] + (mac_id[5] << 8); |
| 228 | |
| 229 | writel(macid_hi, &mac_p->macaddr0hi); |
| 230 | writel(macid_lo, &mac_p->macaddr0lo); |
| 231 | |
| 232 | return 0; |
| 233 | } |
| 234 | |
Simon Glass | 0ea38db | 2017-01-11 11:46:08 +0100 | [diff] [blame] | 235 | static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, |
| 236 | struct phy_device *phydev) |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 237 | { |
| 238 | u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; |
| 239 | |
| 240 | if (!phydev->link) { |
| 241 | printf("%s: No link.\n", phydev->dev->name); |
Simon Glass | 0ea38db | 2017-01-11 11:46:08 +0100 | [diff] [blame] | 242 | return 0; |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 243 | } |
| 244 | |
| 245 | if (phydev->speed != 1000) |
| 246 | conf |= MII_PORTSELECT; |
Alexey Brodkin | b884c3f | 2016-01-13 16:59:36 +0300 | [diff] [blame] | 247 | else |
| 248 | conf &= ~MII_PORTSELECT; |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 249 | |
| 250 | if (phydev->speed == 100) |
| 251 | conf |= FES_100; |
| 252 | |
| 253 | if (phydev->duplex) |
| 254 | conf |= FULLDPLXMODE; |
| 255 | |
| 256 | writel(conf, &mac_p->conf); |
| 257 | |
| 258 | printf("Speed: %d, %s duplex%s\n", phydev->speed, |
| 259 | (phydev->duplex) ? "full" : "half", |
| 260 | (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); |
Simon Glass | 0ea38db | 2017-01-11 11:46:08 +0100 | [diff] [blame] | 261 | |
| 262 | return 0; |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 263 | } |
| 264 | |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 265 | static void _dw_eth_halt(struct dw_eth_dev *priv) |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 266 | { |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 267 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
| 268 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
| 269 | |
| 270 | writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf); |
| 271 | writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode); |
| 272 | |
| 273 | phy_shutdown(priv->phydev); |
| 274 | } |
| 275 | |
Simon Glass | e72ced2 | 2017-01-11 11:46:10 +0100 | [diff] [blame] | 276 | int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 277 | { |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 278 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
| 279 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 280 | unsigned int start; |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 281 | int ret; |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 282 | |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 283 | writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode); |
Vipin Kumar | 13edd17 | 2012-03-26 00:09:56 +0000 | [diff] [blame] | 284 | |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 285 | start = get_timer(0); |
| 286 | while (readl(&dma_p->busmode) & DMAMAC_SRST) { |
Alexey Brodkin | 875143f | 2015-01-13 17:10:24 +0300 | [diff] [blame] | 287 | if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) { |
| 288 | printf("DMA reset timeout\n"); |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 289 | return -ETIMEDOUT; |
Alexey Brodkin | 875143f | 2015-01-13 17:10:24 +0300 | [diff] [blame] | 290 | } |
Stefan Roese | ef76025 | 2012-05-07 12:04:25 +0200 | [diff] [blame] | 291 | |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 292 | mdelay(100); |
| 293 | }; |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 294 | |
Bin Meng | f3edfd3 | 2015-06-15 18:40:19 +0800 | [diff] [blame] | 295 | /* |
| 296 | * Soft reset above clears HW address registers. |
| 297 | * So we have to set it here once again. |
| 298 | */ |
| 299 | _dw_write_hwaddr(priv, enetaddr); |
| 300 | |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 301 | rx_descs_init(priv); |
| 302 | tx_descs_init(priv); |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 303 | |
Ian Campbell | 49692c5 | 2014-05-08 22:26:35 +0100 | [diff] [blame] | 304 | writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode); |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 305 | |
Sonic Zhang | d227922 | 2015-01-29 14:38:50 +0800 | [diff] [blame] | 306 | #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 307 | writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD, |
| 308 | &dma_p->opmode); |
Sonic Zhang | d227922 | 2015-01-29 14:38:50 +0800 | [diff] [blame] | 309 | #else |
| 310 | writel(readl(&dma_p->opmode) | FLUSHTXFIFO, |
| 311 | &dma_p->opmode); |
| 312 | #endif |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 313 | |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 314 | writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode); |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 315 | |
Sonic Zhang | 2ddaf13 | 2015-01-29 13:37:31 +0800 | [diff] [blame] | 316 | #ifdef CONFIG_DW_AXI_BURST_LEN |
| 317 | writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus); |
| 318 | #endif |
| 319 | |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 320 | /* Start up the PHY */ |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 321 | ret = phy_startup(priv->phydev); |
| 322 | if (ret) { |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 323 | printf("Could not initialize PHY %s\n", |
| 324 | priv->phydev->dev->name); |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 325 | return ret; |
Vipin Kumar | 9afc1af | 2012-05-07 13:06:44 +0530 | [diff] [blame] | 326 | } |
| 327 | |
Simon Glass | 0ea38db | 2017-01-11 11:46:08 +0100 | [diff] [blame] | 328 | ret = dw_adjust_link(priv, mac_p, priv->phydev); |
| 329 | if (ret) |
| 330 | return ret; |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 331 | |
Simon Glass | f63f28e | 2017-01-11 11:46:09 +0100 | [diff] [blame] | 332 | return 0; |
| 333 | } |
| 334 | |
Simon Glass | e72ced2 | 2017-01-11 11:46:10 +0100 | [diff] [blame] | 335 | int designware_eth_enable(struct dw_eth_dev *priv) |
Simon Glass | f63f28e | 2017-01-11 11:46:09 +0100 | [diff] [blame] | 336 | { |
| 337 | struct eth_mac_regs *mac_p = priv->mac_regs_p; |
| 338 | |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 339 | if (!priv->phydev->link) |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 340 | return -EIO; |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 341 | |
Armando Visconti | aa51005 | 2012-03-26 00:09:55 +0000 | [diff] [blame] | 342 | writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf); |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 343 | |
| 344 | return 0; |
| 345 | } |
| 346 | |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 347 | static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length) |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 348 | { |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 349 | struct eth_dma_regs *dma_p = priv->dma_regs_p; |
| 350 | u32 desc_num = priv->tx_currdescnum; |
| 351 | struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num]; |
Beniamino Galvani | 0e1a3e3 | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 352 | ulong desc_start = (ulong)desc_p; |
| 353 | ulong desc_end = desc_start + |
Marek Vasut | 96cec17 | 2014-09-15 01:05:23 +0200 | [diff] [blame] | 354 | roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); |
Beniamino Galvani | 0e1a3e3 | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 355 | ulong data_start = desc_p->dmamac_addr; |
| 356 | ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); |
Ian Campbell | 964ea7c | 2014-05-08 22:26:33 +0100 | [diff] [blame] | 357 | /* |
| 358 | * Strictly we only need to invalidate the "txrx_status" field |
| 359 | * for the following check, but on some platforms we cannot |
Marek Vasut | 96cec17 | 2014-09-15 01:05:23 +0200 | [diff] [blame] | 360 | * invalidate only 4 bytes, so we flush the entire descriptor, |
| 361 | * which is 16 bytes in total. This is safe because the |
| 362 | * individual descriptors in the array are each aligned to |
| 363 | * ARCH_DMA_MINALIGN and padded appropriately. |
Ian Campbell | 964ea7c | 2014-05-08 22:26:33 +0100 | [diff] [blame] | 364 | */ |
Marek Vasut | 96cec17 | 2014-09-15 01:05:23 +0200 | [diff] [blame] | 365 | invalidate_dcache_range(desc_start, desc_end); |
Alexey Brodkin | 50b0df8 | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 366 | |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 367 | /* Check if the descriptor is owned by CPU */ |
| 368 | if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) { |
| 369 | printf("CPU not owner of tx frame\n"); |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 370 | return -EPERM; |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 371 | } |
| 372 | |
Beniamino Galvani | 0e1a3e3 | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 373 | memcpy((void *)data_start, packet, length); |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 374 | |
Alexey Brodkin | 50b0df8 | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 375 | /* Flush data to be sent */ |
Marek Vasut | 96cec17 | 2014-09-15 01:05:23 +0200 | [diff] [blame] | 376 | flush_dcache_range(data_start, data_end); |
Alexey Brodkin | 50b0df8 | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 377 | |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 378 | #if defined(CONFIG_DW_ALTDESCRIPTOR) |
| 379 | desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST; |
Marek Vasut | 2b26109 | 2015-12-20 03:59:23 +0100 | [diff] [blame] | 380 | desc_p->dmamac_cntl |= (length << DESC_TXCTRL_SIZE1SHFT) & |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 381 | DESC_TXCTRL_SIZE1MASK; |
| 382 | |
| 383 | desc_p->txrx_status &= ~(DESC_TXSTS_MSK); |
| 384 | desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA; |
| 385 | #else |
Marek Vasut | 2b26109 | 2015-12-20 03:59:23 +0100 | [diff] [blame] | 386 | desc_p->dmamac_cntl |= ((length << DESC_TXCTRL_SIZE1SHFT) & |
| 387 | DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST | |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 388 | DESC_TXCTRL_TXFIRST; |
| 389 | |
| 390 | desc_p->txrx_status = DESC_TXSTS_OWNBYDMA; |
| 391 | #endif |
| 392 | |
Alexey Brodkin | 50b0df8 | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 393 | /* Flush modified buffer descriptor */ |
Marek Vasut | 96cec17 | 2014-09-15 01:05:23 +0200 | [diff] [blame] | 394 | flush_dcache_range(desc_start, desc_end); |
Alexey Brodkin | 50b0df8 | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 395 | |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 396 | /* Test the wrap-around condition. */ |
| 397 | if (++desc_num >= CONFIG_TX_DESCR_NUM) |
| 398 | desc_num = 0; |
| 399 | |
| 400 | priv->tx_currdescnum = desc_num; |
| 401 | |
| 402 | /* Start the transmission */ |
| 403 | writel(POLL_DATA, &dma_p->txpolldemand); |
| 404 | |
| 405 | return 0; |
| 406 | } |
| 407 | |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 408 | static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp) |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 409 | { |
Alexey Brodkin | 50b0df8 | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 410 | u32 status, desc_num = priv->rx_currdescnum; |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 411 | struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 412 | int length = -EAGAIN; |
Beniamino Galvani | 0e1a3e3 | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 413 | ulong desc_start = (ulong)desc_p; |
| 414 | ulong desc_end = desc_start + |
Marek Vasut | 96cec17 | 2014-09-15 01:05:23 +0200 | [diff] [blame] | 415 | roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); |
Beniamino Galvani | 0e1a3e3 | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 416 | ulong data_start = desc_p->dmamac_addr; |
| 417 | ulong data_end; |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 418 | |
Alexey Brodkin | 50b0df8 | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 419 | /* Invalidate entire buffer descriptor */ |
Marek Vasut | 96cec17 | 2014-09-15 01:05:23 +0200 | [diff] [blame] | 420 | invalidate_dcache_range(desc_start, desc_end); |
Alexey Brodkin | 50b0df8 | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 421 | |
| 422 | status = desc_p->txrx_status; |
| 423 | |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 424 | /* Check if the owner is the CPU */ |
| 425 | if (!(status & DESC_RXSTS_OWNBYDMA)) { |
| 426 | |
Marek Vasut | 2b26109 | 2015-12-20 03:59:23 +0100 | [diff] [blame] | 427 | length = (status & DESC_RXSTS_FRMLENMSK) >> |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 428 | DESC_RXSTS_FRMLENSHFT; |
| 429 | |
Alexey Brodkin | 50b0df8 | 2014-01-22 20:49:09 +0400 | [diff] [blame] | 430 | /* Invalidate received data */ |
Marek Vasut | 96cec17 | 2014-09-15 01:05:23 +0200 | [diff] [blame] | 431 | data_end = data_start + roundup(length, ARCH_DMA_MINALIGN); |
| 432 | invalidate_dcache_range(data_start, data_end); |
Beniamino Galvani | 0e1a3e3 | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 433 | *packetp = (uchar *)(ulong)desc_p->dmamac_addr; |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 434 | } |
| 435 | |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 436 | return length; |
| 437 | } |
| 438 | |
| 439 | static int _dw_free_pkt(struct dw_eth_dev *priv) |
| 440 | { |
| 441 | u32 desc_num = priv->rx_currdescnum; |
| 442 | struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num]; |
Beniamino Galvani | 0e1a3e3 | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 443 | ulong desc_start = (ulong)desc_p; |
| 444 | ulong desc_end = desc_start + |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 445 | roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN); |
| 446 | |
| 447 | /* |
| 448 | * Make the current descriptor valid again and go to |
| 449 | * the next one |
| 450 | */ |
| 451 | desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA; |
| 452 | |
| 453 | /* Flush only status field - others weren't changed */ |
| 454 | flush_dcache_range(desc_start, desc_end); |
| 455 | |
| 456 | /* Test the wrap-around condition. */ |
| 457 | if (++desc_num >= CONFIG_RX_DESCR_NUM) |
| 458 | desc_num = 0; |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 459 | priv->rx_currdescnum = desc_num; |
| 460 | |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 461 | return 0; |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 462 | } |
| 463 | |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 464 | static int dw_phy_init(struct dw_eth_dev *priv, void *dev) |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 465 | { |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 466 | struct phy_device *phydev; |
Alexey Brodkin | 6968ec9 | 2016-01-13 16:59:37 +0300 | [diff] [blame] | 467 | int mask = 0xffffffff, ret; |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 468 | |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 469 | #ifdef CONFIG_PHY_ADDR |
| 470 | mask = 1 << CONFIG_PHY_ADDR; |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 471 | #endif |
| 472 | |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 473 | phydev = phy_find_by_mask(priv->bus, mask, priv->interface); |
| 474 | if (!phydev) |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 475 | return -ENODEV; |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 476 | |
Ian Campbell | 15e82e5 | 2014-04-28 20:14:05 +0100 | [diff] [blame] | 477 | phy_connect_dev(phydev, dev); |
| 478 | |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 479 | phydev->supported &= PHY_GBIT_FEATURES; |
Alexey Brodkin | 6968ec9 | 2016-01-13 16:59:37 +0300 | [diff] [blame] | 480 | if (priv->max_speed) { |
| 481 | ret = phy_set_supported(phydev, priv->max_speed); |
| 482 | if (ret) |
| 483 | return ret; |
| 484 | } |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 485 | phydev->advertising = phydev->supported; |
| 486 | |
| 487 | priv->phydev = phydev; |
| 488 | phy_config(phydev); |
| 489 | |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 490 | return 0; |
| 491 | } |
| 492 | |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 493 | #ifndef CONFIG_DM_ETH |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 494 | static int dw_eth_init(struct eth_device *dev, bd_t *bis) |
| 495 | { |
Simon Glass | f63f28e | 2017-01-11 11:46:09 +0100 | [diff] [blame] | 496 | int ret; |
| 497 | |
Simon Glass | e72ced2 | 2017-01-11 11:46:10 +0100 | [diff] [blame] | 498 | ret = designware_eth_init(dev->priv, dev->enetaddr); |
Simon Glass | f63f28e | 2017-01-11 11:46:09 +0100 | [diff] [blame] | 499 | if (!ret) |
| 500 | ret = designware_eth_enable(dev->priv); |
| 501 | |
| 502 | return ret; |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 503 | } |
| 504 | |
| 505 | static int dw_eth_send(struct eth_device *dev, void *packet, int length) |
| 506 | { |
| 507 | return _dw_eth_send(dev->priv, packet, length); |
| 508 | } |
| 509 | |
| 510 | static int dw_eth_recv(struct eth_device *dev) |
| 511 | { |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 512 | uchar *packet; |
| 513 | int length; |
| 514 | |
| 515 | length = _dw_eth_recv(dev->priv, &packet); |
| 516 | if (length == -EAGAIN) |
| 517 | return 0; |
| 518 | net_process_received_packet(packet, length); |
| 519 | |
| 520 | _dw_free_pkt(dev->priv); |
| 521 | |
| 522 | return 0; |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 523 | } |
| 524 | |
| 525 | static void dw_eth_halt(struct eth_device *dev) |
| 526 | { |
| 527 | return _dw_eth_halt(dev->priv); |
| 528 | } |
| 529 | |
| 530 | static int dw_write_hwaddr(struct eth_device *dev) |
| 531 | { |
| 532 | return _dw_write_hwaddr(dev->priv, dev->enetaddr); |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 533 | } |
| 534 | |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 535 | int designware_initialize(ulong base_addr, u32 interface) |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 536 | { |
| 537 | struct eth_device *dev; |
| 538 | struct dw_eth_dev *priv; |
| 539 | |
| 540 | dev = (struct eth_device *) malloc(sizeof(struct eth_device)); |
| 541 | if (!dev) |
| 542 | return -ENOMEM; |
| 543 | |
| 544 | /* |
| 545 | * Since the priv structure contains the descriptors which need a strict |
| 546 | * buswidth alignment, memalign is used to allocate memory |
| 547 | */ |
Ian Campbell | 1c848a2 | 2014-05-08 22:26:32 +0100 | [diff] [blame] | 548 | priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN, |
| 549 | sizeof(struct dw_eth_dev)); |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 550 | if (!priv) { |
| 551 | free(dev); |
| 552 | return -ENOMEM; |
| 553 | } |
| 554 | |
Beniamino Galvani | 0e1a3e3 | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 555 | if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) { |
| 556 | printf("designware: buffers are outside DMA memory\n"); |
| 557 | return -EINVAL; |
| 558 | } |
| 559 | |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 560 | memset(dev, 0, sizeof(struct eth_device)); |
| 561 | memset(priv, 0, sizeof(struct dw_eth_dev)); |
| 562 | |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 563 | sprintf(dev->name, "dwmac.%lx", base_addr); |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 564 | dev->iobase = (int)base_addr; |
| 565 | dev->priv = priv; |
| 566 | |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 567 | priv->dev = dev; |
| 568 | priv->mac_regs_p = (struct eth_mac_regs *)base_addr; |
| 569 | priv->dma_regs_p = (struct eth_dma_regs *)(base_addr + |
| 570 | DW_DMA_BASE_OFFSET); |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 571 | |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 572 | dev->init = dw_eth_init; |
| 573 | dev->send = dw_eth_send; |
| 574 | dev->recv = dw_eth_recv; |
| 575 | dev->halt = dw_eth_halt; |
| 576 | dev->write_hwaddr = dw_write_hwaddr; |
| 577 | |
| 578 | eth_register(dev); |
| 579 | |
Alexey Brodkin | 92a190a | 2014-01-22 20:54:06 +0400 | [diff] [blame] | 580 | priv->interface = interface; |
| 581 | |
| 582 | dw_mdio_init(dev->name, priv->mac_regs_p); |
| 583 | priv->bus = miiphy_get_dev_by_name(dev->name); |
| 584 | |
Simon Glass | 64dcd25 | 2015-04-05 16:07:40 -0600 | [diff] [blame] | 585 | return dw_phy_init(priv, dev); |
Vipin KUMAR | 5b1b188 | 2010-06-29 10:53:34 +0530 | [diff] [blame] | 586 | } |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 587 | #endif |
| 588 | |
| 589 | #ifdef CONFIG_DM_ETH |
| 590 | static int designware_eth_start(struct udevice *dev) |
| 591 | { |
| 592 | struct eth_pdata *pdata = dev_get_platdata(dev); |
Simon Glass | f63f28e | 2017-01-11 11:46:09 +0100 | [diff] [blame] | 593 | struct dw_eth_dev *priv = dev_get_priv(dev); |
| 594 | int ret; |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 595 | |
Simon Glass | e72ced2 | 2017-01-11 11:46:10 +0100 | [diff] [blame] | 596 | ret = designware_eth_init(priv, pdata->enetaddr); |
Simon Glass | f63f28e | 2017-01-11 11:46:09 +0100 | [diff] [blame] | 597 | if (ret) |
| 598 | return ret; |
| 599 | ret = designware_eth_enable(priv); |
| 600 | if (ret) |
| 601 | return ret; |
| 602 | |
| 603 | return 0; |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 604 | } |
| 605 | |
Simon Glass | e72ced2 | 2017-01-11 11:46:10 +0100 | [diff] [blame] | 606 | int designware_eth_send(struct udevice *dev, void *packet, int length) |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 607 | { |
| 608 | struct dw_eth_dev *priv = dev_get_priv(dev); |
| 609 | |
| 610 | return _dw_eth_send(priv, packet, length); |
| 611 | } |
| 612 | |
Simon Glass | e72ced2 | 2017-01-11 11:46:10 +0100 | [diff] [blame] | 613 | int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp) |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 614 | { |
| 615 | struct dw_eth_dev *priv = dev_get_priv(dev); |
| 616 | |
| 617 | return _dw_eth_recv(priv, packetp); |
| 618 | } |
| 619 | |
Simon Glass | e72ced2 | 2017-01-11 11:46:10 +0100 | [diff] [blame] | 620 | int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length) |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 621 | { |
| 622 | struct dw_eth_dev *priv = dev_get_priv(dev); |
| 623 | |
| 624 | return _dw_free_pkt(priv); |
| 625 | } |
| 626 | |
Simon Glass | e72ced2 | 2017-01-11 11:46:10 +0100 | [diff] [blame] | 627 | void designware_eth_stop(struct udevice *dev) |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 628 | { |
| 629 | struct dw_eth_dev *priv = dev_get_priv(dev); |
| 630 | |
| 631 | return _dw_eth_halt(priv); |
| 632 | } |
| 633 | |
Simon Glass | e72ced2 | 2017-01-11 11:46:10 +0100 | [diff] [blame] | 634 | int designware_eth_write_hwaddr(struct udevice *dev) |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 635 | { |
| 636 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 637 | struct dw_eth_dev *priv = dev_get_priv(dev); |
| 638 | |
| 639 | return _dw_write_hwaddr(priv, pdata->enetaddr); |
| 640 | } |
| 641 | |
Bin Meng | 8b7ee66 | 2015-09-11 03:24:35 -0700 | [diff] [blame] | 642 | static int designware_eth_bind(struct udevice *dev) |
| 643 | { |
| 644 | #ifdef CONFIG_DM_PCI |
| 645 | static int num_cards; |
| 646 | char name[20]; |
| 647 | |
| 648 | /* Create a unique device name for PCI type devices */ |
| 649 | if (device_is_on_pci_bus(dev)) { |
| 650 | sprintf(name, "eth_designware#%u", num_cards++); |
| 651 | device_set_name(dev, name); |
| 652 | } |
| 653 | #endif |
| 654 | |
| 655 | return 0; |
| 656 | } |
| 657 | |
Sjoerd Simons | b9e08d0 | 2017-01-11 11:46:07 +0100 | [diff] [blame] | 658 | int designware_eth_probe(struct udevice *dev) |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 659 | { |
| 660 | struct eth_pdata *pdata = dev_get_platdata(dev); |
| 661 | struct dw_eth_dev *priv = dev_get_priv(dev); |
Bin Meng | f0dc73c | 2015-09-03 05:37:29 -0700 | [diff] [blame] | 662 | u32 iobase = pdata->iobase; |
Beniamino Galvani | 0e1a3e3 | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 663 | ulong ioaddr; |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 664 | int ret; |
Patrice Chotard | ba1f966 | 2017-11-29 09:06:11 +0100 | [diff] [blame^] | 665 | #ifdef CONFIG_CLK |
| 666 | int i, err, clock_nb; |
| 667 | |
| 668 | priv->clock_count = 0; |
| 669 | clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells"); |
| 670 | if (clock_nb > 0) { |
| 671 | priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk), |
| 672 | GFP_KERNEL); |
| 673 | if (!priv->clocks) |
| 674 | return -ENOMEM; |
| 675 | |
| 676 | for (i = 0; i < clock_nb; i++) { |
| 677 | err = clk_get_by_index(dev, i, &priv->clocks[i]); |
| 678 | if (err < 0) |
| 679 | break; |
| 680 | |
| 681 | err = clk_enable(&priv->clocks[i]); |
| 682 | if (err) { |
| 683 | pr_err("failed to enable clock %d\n", i); |
| 684 | clk_free(&priv->clocks[i]); |
| 685 | goto clk_err; |
| 686 | } |
| 687 | priv->clock_count++; |
| 688 | } |
| 689 | } else if (clock_nb != -ENOENT) { |
| 690 | pr_err("failed to get clock phandle(%d)\n", clock_nb); |
| 691 | return clock_nb; |
| 692 | } |
| 693 | #endif |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 694 | |
Jacob Chen | 6ec922f | 2017-03-27 16:54:17 +0800 | [diff] [blame] | 695 | #if defined(CONFIG_DM_REGULATOR) |
| 696 | struct udevice *phy_supply; |
| 697 | |
| 698 | ret = device_get_supply_regulator(dev, "phy-supply", |
| 699 | &phy_supply); |
| 700 | if (ret) { |
| 701 | debug("%s: No phy supply\n", dev->name); |
| 702 | } else { |
| 703 | ret = regulator_set_enable(phy_supply, true); |
| 704 | if (ret) { |
| 705 | puts("Error enabling phy supply\n"); |
| 706 | return ret; |
| 707 | } |
| 708 | } |
| 709 | #endif |
| 710 | |
Bin Meng | 8b7ee66 | 2015-09-11 03:24:35 -0700 | [diff] [blame] | 711 | #ifdef CONFIG_DM_PCI |
| 712 | /* |
| 713 | * If we are on PCI bus, either directly attached to a PCI root port, |
| 714 | * or via a PCI bridge, fill in platdata before we probe the hardware. |
| 715 | */ |
| 716 | if (device_is_on_pci_bus(dev)) { |
Bin Meng | 8b7ee66 | 2015-09-11 03:24:35 -0700 | [diff] [blame] | 717 | dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase); |
| 718 | iobase &= PCI_BASE_ADDRESS_MEM_MASK; |
Bin Meng | 6758a6c | 2016-02-02 05:58:00 -0800 | [diff] [blame] | 719 | iobase = dm_pci_mem_to_phys(dev, iobase); |
Bin Meng | 8b7ee66 | 2015-09-11 03:24:35 -0700 | [diff] [blame] | 720 | |
| 721 | pdata->iobase = iobase; |
| 722 | pdata->phy_interface = PHY_INTERFACE_MODE_RMII; |
| 723 | } |
| 724 | #endif |
| 725 | |
Bin Meng | f0dc73c | 2015-09-03 05:37:29 -0700 | [diff] [blame] | 726 | debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv); |
Beniamino Galvani | 0e1a3e3 | 2016-05-08 08:30:15 +0200 | [diff] [blame] | 727 | ioaddr = iobase; |
| 728 | priv->mac_regs_p = (struct eth_mac_regs *)ioaddr; |
| 729 | priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET); |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 730 | priv->interface = pdata->phy_interface; |
Alexey Brodkin | 6968ec9 | 2016-01-13 16:59:37 +0300 | [diff] [blame] | 731 | priv->max_speed = pdata->max_speed; |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 732 | |
Sjoerd Simons | 90b7fc9 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 733 | dw_mdio_init(dev->name, dev); |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 734 | priv->bus = miiphy_get_dev_by_name(dev->name); |
| 735 | |
| 736 | ret = dw_phy_init(priv, dev); |
| 737 | debug("%s, ret=%d\n", __func__, ret); |
| 738 | |
| 739 | return ret; |
Patrice Chotard | ba1f966 | 2017-11-29 09:06:11 +0100 | [diff] [blame^] | 740 | |
| 741 | #ifdef CONFIG_CLK |
| 742 | clk_err: |
| 743 | ret = clk_release_all(priv->clocks, priv->clock_count); |
| 744 | if (ret) |
| 745 | pr_err("failed to disable all clocks\n"); |
| 746 | |
| 747 | return err; |
| 748 | #endif |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 749 | } |
| 750 | |
Bin Meng | 5d2459f | 2015-10-07 21:32:38 -0700 | [diff] [blame] | 751 | static int designware_eth_remove(struct udevice *dev) |
| 752 | { |
| 753 | struct dw_eth_dev *priv = dev_get_priv(dev); |
| 754 | |
| 755 | free(priv->phydev); |
| 756 | mdio_unregister(priv->bus); |
| 757 | mdio_free(priv->bus); |
| 758 | |
Patrice Chotard | ba1f966 | 2017-11-29 09:06:11 +0100 | [diff] [blame^] | 759 | #ifdef CONFIG_CLK |
| 760 | return clk_release_all(priv->clocks, priv->clock_count); |
| 761 | #else |
Bin Meng | 5d2459f | 2015-10-07 21:32:38 -0700 | [diff] [blame] | 762 | return 0; |
Patrice Chotard | ba1f966 | 2017-11-29 09:06:11 +0100 | [diff] [blame^] | 763 | #endif |
Bin Meng | 5d2459f | 2015-10-07 21:32:38 -0700 | [diff] [blame] | 764 | } |
| 765 | |
Sjoerd Simons | b9e08d0 | 2017-01-11 11:46:07 +0100 | [diff] [blame] | 766 | const struct eth_ops designware_eth_ops = { |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 767 | .start = designware_eth_start, |
| 768 | .send = designware_eth_send, |
| 769 | .recv = designware_eth_recv, |
| 770 | .free_pkt = designware_eth_free_pkt, |
| 771 | .stop = designware_eth_stop, |
| 772 | .write_hwaddr = designware_eth_write_hwaddr, |
| 773 | }; |
| 774 | |
Sjoerd Simons | b9e08d0 | 2017-01-11 11:46:07 +0100 | [diff] [blame] | 775 | int designware_eth_ofdata_to_platdata(struct udevice *dev) |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 776 | { |
Sjoerd Simons | 90b7fc9 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 777 | struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); |
Alexey Brodkin | 66d027e | 2016-06-27 13:17:51 +0300 | [diff] [blame] | 778 | #ifdef CONFIG_DM_GPIO |
Sjoerd Simons | 90b7fc9 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 779 | struct dw_eth_dev *priv = dev_get_priv(dev); |
Alexey Brodkin | 66d027e | 2016-06-27 13:17:51 +0300 | [diff] [blame] | 780 | #endif |
Sjoerd Simons | 90b7fc9 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 781 | struct eth_pdata *pdata = &dw_pdata->eth_pdata; |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 782 | const char *phy_mode; |
Alexey Brodkin | 66d027e | 2016-06-27 13:17:51 +0300 | [diff] [blame] | 783 | #ifdef CONFIG_DM_GPIO |
Sjoerd Simons | 90b7fc9 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 784 | int reset_flags = GPIOD_IS_OUT; |
Alexey Brodkin | 66d027e | 2016-06-27 13:17:51 +0300 | [diff] [blame] | 785 | #endif |
Sjoerd Simons | 90b7fc9 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 786 | int ret = 0; |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 787 | |
Philipp Tomsich | 15050f1 | 2017-09-11 22:04:13 +0200 | [diff] [blame] | 788 | pdata->iobase = dev_read_addr(dev); |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 789 | pdata->phy_interface = -1; |
Philipp Tomsich | 15050f1 | 2017-09-11 22:04:13 +0200 | [diff] [blame] | 790 | phy_mode = dev_read_string(dev, "phy-mode"); |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 791 | if (phy_mode) |
| 792 | pdata->phy_interface = phy_get_interface_by_name(phy_mode); |
| 793 | if (pdata->phy_interface == -1) { |
| 794 | debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode); |
| 795 | return -EINVAL; |
| 796 | } |
| 797 | |
Philipp Tomsich | 15050f1 | 2017-09-11 22:04:13 +0200 | [diff] [blame] | 798 | pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0); |
Alexey Brodkin | 6968ec9 | 2016-01-13 16:59:37 +0300 | [diff] [blame] | 799 | |
Alexey Brodkin | 66d027e | 2016-06-27 13:17:51 +0300 | [diff] [blame] | 800 | #ifdef CONFIG_DM_GPIO |
Philipp Tomsich | 7ad326a | 2017-06-07 18:46:01 +0200 | [diff] [blame] | 801 | if (dev_read_bool(dev, "snps,reset-active-low")) |
Sjoerd Simons | 90b7fc9 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 802 | reset_flags |= GPIOD_ACTIVE_LOW; |
| 803 | |
| 804 | ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, |
| 805 | &priv->reset_gpio, reset_flags); |
| 806 | if (ret == 0) { |
Philipp Tomsich | 7ad326a | 2017-06-07 18:46:01 +0200 | [diff] [blame] | 807 | ret = dev_read_u32_array(dev, "snps,reset-delays-us", |
| 808 | dw_pdata->reset_delays, 3); |
Sjoerd Simons | 90b7fc9 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 809 | } else if (ret == -ENOENT) { |
| 810 | ret = 0; |
| 811 | } |
Alexey Brodkin | 66d027e | 2016-06-27 13:17:51 +0300 | [diff] [blame] | 812 | #endif |
Sjoerd Simons | 90b7fc9 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 813 | |
| 814 | return ret; |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 815 | } |
| 816 | |
| 817 | static const struct udevice_id designware_eth_ids[] = { |
| 818 | { .compatible = "allwinner,sun7i-a20-gmac" }, |
Marek Vasut | b962859 | 2015-07-25 18:38:44 +0200 | [diff] [blame] | 819 | { .compatible = "altr,socfpga-stmmac" }, |
Beniamino Galvani | cfe2556 | 2016-08-16 11:49:50 +0200 | [diff] [blame] | 820 | { .compatible = "amlogic,meson6-dwmac" }, |
Heiner Kallweit | 655217d | 2017-01-27 21:25:59 +0100 | [diff] [blame] | 821 | { .compatible = "amlogic,meson-gx-dwmac" }, |
Michael Kurz | b20b70f | 2017-01-22 16:04:27 +0100 | [diff] [blame] | 822 | { .compatible = "st,stm32-dwmac" }, |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 823 | { } |
| 824 | }; |
| 825 | |
Marek Vasut | 9f76f10 | 2015-07-25 18:42:34 +0200 | [diff] [blame] | 826 | U_BOOT_DRIVER(eth_designware) = { |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 827 | .name = "eth_designware", |
| 828 | .id = UCLASS_ETH, |
| 829 | .of_match = designware_eth_ids, |
| 830 | .ofdata_to_platdata = designware_eth_ofdata_to_platdata, |
Bin Meng | 8b7ee66 | 2015-09-11 03:24:35 -0700 | [diff] [blame] | 831 | .bind = designware_eth_bind, |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 832 | .probe = designware_eth_probe, |
Bin Meng | 5d2459f | 2015-10-07 21:32:38 -0700 | [diff] [blame] | 833 | .remove = designware_eth_remove, |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 834 | .ops = &designware_eth_ops, |
| 835 | .priv_auto_alloc_size = sizeof(struct dw_eth_dev), |
Sjoerd Simons | 90b7fc9 | 2016-02-28 22:24:55 +0100 | [diff] [blame] | 836 | .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata), |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 837 | .flags = DM_FLAG_ALLOC_PRIV_DMA, |
| 838 | }; |
Bin Meng | 8b7ee66 | 2015-09-11 03:24:35 -0700 | [diff] [blame] | 839 | |
| 840 | static struct pci_device_id supported[] = { |
| 841 | { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) }, |
| 842 | { } |
| 843 | }; |
| 844 | |
| 845 | U_BOOT_PCI_DEVICE(eth_designware, supported); |
Simon Glass | 75577ba | 2015-04-05 16:07:41 -0600 | [diff] [blame] | 846 | #endif |