blob: bd5ebfde2bd6cc2a66891c00de80e98b5b2329fd [file] [log] [blame]
Simon Glass281aea42015-02-07 11:51:41 -07001/*
2 * Device Tree Source for AMCC Arches (dual 460GT board)
3 *
4 * (C) Copyright 2008 Applied Micro Circuits Corporation
5 * Victor Gallardo <vgallardo@amcc.com>
6 * Adam Graham <agraham@amcc.com>
7 *
8 * Based on the glacier.dts file
9 * Stefan Roese <sr@denx.de>
10 * Copyright 2008 DENX Software Engineering
11 *
12 * SPDX-License-Identifier: GPL-2.0+
13 */
14
15/dts-v1/;
16
17/ {
18 #address-cells = <2>;
19 #size-cells = <1>;
20 model = "amcc,arches";
21 compatible = "amcc,arches";
22 dcr-parent = <&{/cpus/cpu@0}>;
23
24 aliases {
25 ethernet0 = &EMAC0;
26 ethernet1 = &EMAC1;
27 ethernet2 = &EMAC2;
28 serial0 = &UART0;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 device_type = "cpu";
37 model = "PowerPC,460GT";
38 reg = <0x00000000>;
39 clock-frequency = <0>; /* Filled in by U-Boot */
40 timebase-frequency = <0>; /* Filled in by U-Boot */
41 i-cache-line-size = <32>;
42 d-cache-line-size = <32>;
43 i-cache-size = <32768>;
44 d-cache-size = <32768>;
45 dcr-controller;
46 dcr-access-method = "native";
47 next-level-cache = <&L2C0>;
48 };
49 };
50
51 memory {
52 device_type = "memory";
53 reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
54 };
55
56 UIC0: interrupt-controller0 {
57 compatible = "ibm,uic-460gt","ibm,uic";
58 interrupt-controller;
59 cell-index = <0>;
60 dcr-reg = <0x0c0 0x009>;
61 #address-cells = <0>;
62 #size-cells = <0>;
63 #interrupt-cells = <2>;
64 };
65
66 UIC1: interrupt-controller1 {
67 compatible = "ibm,uic-460gt","ibm,uic";
68 interrupt-controller;
69 cell-index = <1>;
70 dcr-reg = <0x0d0 0x009>;
71 #address-cells = <0>;
72 #size-cells = <0>;
73 #interrupt-cells = <2>;
74 interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
75 interrupt-parent = <&UIC0>;
76 };
77
78 UIC2: interrupt-controller2 {
79 compatible = "ibm,uic-460gt","ibm,uic";
80 interrupt-controller;
81 cell-index = <2>;
82 dcr-reg = <0x0e0 0x009>;
83 #address-cells = <0>;
84 #size-cells = <0>;
85 #interrupt-cells = <2>;
86 interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
87 interrupt-parent = <&UIC0>;
88 };
89
90 UIC3: interrupt-controller3 {
91 compatible = "ibm,uic-460gt","ibm,uic";
92 interrupt-controller;
93 cell-index = <3>;
94 dcr-reg = <0x0f0 0x009>;
95 #address-cells = <0>;
96 #size-cells = <0>;
97 #interrupt-cells = <2>;
98 interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
99 interrupt-parent = <&UIC0>;
100 };
101
102 SDR0: sdr {
103 compatible = "ibm,sdr-460gt";
104 dcr-reg = <0x00e 0x002>;
105 };
106
107 CPR0: cpr {
108 compatible = "ibm,cpr-460gt";
109 dcr-reg = <0x00c 0x002>;
110 };
111
112 L2C0: l2c {
113 compatible = "ibm,l2-cache-460gt", "ibm,l2-cache";
114 dcr-reg = <0x020 0x008 /* Internal SRAM DCR's */
115 0x030 0x008>; /* L2 cache DCR's */
116 cache-line-size = <32>; /* 32 bytes */
117 cache-size = <262144>; /* L2, 256K */
118 interrupt-parent = <&UIC1>;
119 interrupts = <11 1>;
120 };
121
122 plb {
123 compatible = "ibm,plb-460gt", "ibm,plb4";
124 #address-cells = <2>;
125 #size-cells = <1>;
126 ranges;
127 clock-frequency = <0>; /* Filled in by U-Boot */
128
129 SDRAM0: sdram {
130 compatible = "ibm,sdram-460gt", "ibm,sdram-405gp";
131 dcr-reg = <0x010 0x002>;
132 };
133
134 CRYPTO: crypto@180000 {
135 compatible = "amcc,ppc460gt-crypto", "amcc,ppc4xx-crypto";
136 reg = <4 0x00180000 0x80400>;
137 interrupt-parent = <&UIC0>;
138 interrupts = <0x1d 0x4>;
139 };
140
141 MAL0: mcmal {
142 compatible = "ibm,mcmal-460gt", "ibm,mcmal2";
143 dcr-reg = <0x180 0x062>;
144 num-tx-chans = <3>;
145 num-rx-chans = <24>;
146 #address-cells = <0>;
147 #size-cells = <0>;
148 interrupt-parent = <&UIC2>;
149 interrupts = < /*TXEOB*/ 0x6 0x4
150 /*RXEOB*/ 0x7 0x4
151 /*SERR*/ 0x3 0x4
152 /*TXDE*/ 0x4 0x4
153 /*RXDE*/ 0x5 0x4>;
154 desc-base-addr-high = <0x8>;
155 };
156
157 POB0: opb {
158 compatible = "ibm,opb-460gt", "ibm,opb";
159 #address-cells = <1>;
160 #size-cells = <1>;
161 ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
162 clock-frequency = <0>; /* Filled in by U-Boot */
163
164 EBC0: ebc {
165 compatible = "ibm,ebc-460gt", "ibm,ebc";
166 dcr-reg = <0x012 0x002>;
167 #address-cells = <2>;
168 #size-cells = <1>;
169 clock-frequency = <0>; /* Filled in by U-Boot */
170 /* ranges property is supplied by U-Boot */
171 interrupts = <0x6 0x4>;
172 interrupt-parent = <&UIC1>;
173
174 nor_flash@0,0 {
175 compatible = "amd,s29gl256n", "cfi-flash";
176 bank-width = <2>;
177 reg = <0x00000000 0x00000000 0x02000000>;
178 #address-cells = <1>;
179 #size-cells = <1>;
180 partition@0 {
181 label = "kernel";
182 reg = <0x00000000 0x001e0000>;
183 };
184 partition@1e0000 {
185 label = "dtb";
186 reg = <0x001e0000 0x00020000>;
187 };
188 partition@200000 {
189 label = "root";
190 reg = <0x00200000 0x00200000>;
191 };
192 partition@400000 {
193 label = "user";
194 reg = <0x00400000 0x01b60000>;
195 };
196 partition@1f60000 {
197 label = "env";
198 reg = <0x01f60000 0x00040000>;
199 };
200 partition@1fa0000 {
201 label = "u-boot";
202 reg = <0x01fa0000 0x00060000>;
203 };
204 };
205 };
206
207 UART0: serial@ef600300 {
208 device_type = "serial";
209 compatible = "ns16550";
210 reg = <0xef600300 0x00000008>;
211 virtual-reg = <0xef600300>;
212 clock-frequency = <0>; /* Filled in by U-Boot */
213 current-speed = <0>; /* Filled in by U-Boot */
214 interrupt-parent = <&UIC1>;
215 interrupts = <0x1 0x4>;
216 };
217
218 IIC0: i2c@ef600700 {
219 compatible = "ibm,iic-460gt", "ibm,iic";
220 reg = <0xef600700 0x00000014>;
221 interrupt-parent = <&UIC0>;
222 interrupts = <0x2 0x4>;
223 #address-cells = <1>;
224 #size-cells = <0>;
225 sttm@4a {
226 compatible = "ad,ad7414";
227 reg = <0x4a>;
228 interrupt-parent = <&UIC1>;
229 interrupts = <0x0 0x8>;
230 };
231 };
232
233 IIC1: i2c@ef600800 {
234 compatible = "ibm,iic-460gt", "ibm,iic";
235 reg = <0xef600800 0x00000014>;
236 interrupt-parent = <&UIC0>;
237 interrupts = <0x3 0x4>;
238 };
239
240 TAH0: emac-tah@ef601350 {
241 compatible = "ibm,tah-460gt", "ibm,tah";
242 reg = <0xef601350 0x00000030>;
243 };
244
245 TAH1: emac-tah@ef601450 {
246 compatible = "ibm,tah-460gt", "ibm,tah";
247 reg = <0xef601450 0x00000030>;
248 };
249
250 EMAC0: ethernet@ef600e00 {
251 device_type = "network";
252 compatible = "ibm,emac-460gt", "ibm,emac4sync";
253 interrupt-parent = <&EMAC0>;
254 interrupts = <0x0 0x1>;
255 #interrupt-cells = <1>;
256 #address-cells = <0>;
257 #size-cells = <0>;
258 interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
259 /*Wake*/ 0x1 &UIC2 0x14 0x4>;
260 reg = <0xef600e00 0x000000c4>;
261 local-mac-address = [000000000000]; /* Filled in by U-Boot */
262 mal-device = <&MAL0>;
263 mal-tx-channel = <0>;
264 mal-rx-channel = <0>;
265 cell-index = <0>;
266 max-frame-size = <9000>;
267 rx-fifo-size = <4096>;
268 tx-fifo-size = <2048>;
269 rx-fifo-size-gige = <16384>;
270 phy-mode = "sgmii";
271 phy-map = <0xffffffff>;
272 gpcs-address = <0x0000000a>;
273 tah-device = <&TAH0>;
274 tah-channel = <0>;
275 has-inverted-stacr-oc;
276 has-new-stacr-staopc;
277 };
278
279 EMAC1: ethernet@ef600f00 {
280 device_type = "network";
281 compatible = "ibm,emac-460gt", "ibm,emac4sync";
282 interrupt-parent = <&EMAC1>;
283 interrupts = <0x0 0x1>;
284 #interrupt-cells = <1>;
285 #address-cells = <0>;
286 #size-cells = <0>;
287 interrupt-map = </*Status*/ 0x0 &UIC2 0x11 0x4
288 /*Wake*/ 0x1 &UIC2 0x15 0x4>;
289 reg = <0xef600f00 0x000000c4>;
290 local-mac-address = [000000000000]; /* Filled in by U-Boot */
291 mal-device = <&MAL0>;
292 mal-tx-channel = <1>;
293 mal-rx-channel = <8>;
294 cell-index = <1>;
295 max-frame-size = <9000>;
296 rx-fifo-size = <4096>;
297 tx-fifo-size = <2048>;
298 rx-fifo-size-gige = <16384>;
299 phy-mode = "sgmii";
300 phy-map = <0x00000000>;
301 gpcs-address = <0x0000000b>;
302 tah-device = <&TAH1>;
303 tah-channel = <1>;
304 has-inverted-stacr-oc;
305 has-new-stacr-staopc;
306 mdio-device = <&EMAC0>;
307 };
308
309 EMAC2: ethernet@ef601100 {
310 device_type = "network";
311 compatible = "ibm,emac-460gt", "ibm,emac4sync";
312 interrupt-parent = <&EMAC2>;
313 interrupts = <0x0 0x1>;
314 #interrupt-cells = <1>;
315 #address-cells = <0>;
316 #size-cells = <0>;
317 interrupt-map = </*Status*/ 0x0 &UIC2 0x12 0x4
318 /*Wake*/ 0x1 &UIC2 0x16 0x4>;
319 reg = <0xef601100 0x000000c4>;
320 local-mac-address = [000000000000]; /* Filled in by U-Boot */
321 mal-device = <&MAL0>;
322 mal-tx-channel = <2>;
323 mal-rx-channel = <16>;
324 cell-index = <2>;
325 max-frame-size = <9000>;
326 rx-fifo-size = <4096>;
327 tx-fifo-size = <2048>;
328 rx-fifo-size-gige = <16384>;
329 tx-fifo-size-gige = <16384>; /* emac2&3 only */
330 phy-mode = "sgmii";
331 phy-map = <0x00000001>;
332 gpcs-address = <0x0000000C>;
333 has-inverted-stacr-oc;
334 has-new-stacr-staopc;
335 mdio-device = <&EMAC0>;
336 };
337 };
338 };
339};