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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +02002/*
3 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01004 * Stelian Pop <stelian@popies.net>
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +02005 * Lead Tech Design <www.leadtechdesign.com>
6 *
Daniel Gorsulowski83bf0052015-11-02 07:59:49 +01007 * (C) Copyright 2009-2015
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +02008 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
9 * esd electronic system design gmbh <www.esd.eu>
10 *
11 * Configuation settings for the esd MEESC board.
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +020012 */
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
Matthias Fuchs0cb77bf2011-07-19 01:56:06 +000017/*
18 * SoC must be defined first, before hardware.h is included.
19 * In this case SoC is defined in boards.cfg.
20 */
21#include <asm/hardware.h>
22
23/*
24 * Warning: changing CONFIG_SYS_TEXT_BASE requires
25 * adapting the initial boot program.
26 * Since the linker has to swallow that define, we must use a pure
27 * hex number here!
28 */
Matthias Fuchs0cb77bf2011-07-19 01:56:06 +000029
30/* ARM asynchronous clock */
31#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* 32.768 kHz crystal */
Daniel Gorsulowski9f07ded2010-08-09 11:17:13 +020032#define CONFIG_SYS_AT91_MAIN_CLOCK 16000000/* 16.0 MHz crystal */
Matthias Fuchs0cb77bf2011-07-19 01:56:06 +000033
34/* Misc CPU related */
35#define CONFIG_SKIP_LOWLEVEL_INIT
Matthias Fuchs0cb77bf2011-07-19 01:56:06 +000036#define CONFIG_SETUP_MEMORY_TAGS
37#define CONFIG_INITRD_TAG
38#define CONFIG_SERIAL_TAG
39#define CONFIG_REVISION_TAG
40#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +020041
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +020042/*
43 * Hardware drivers
44 */
45
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +020046/*
47 * BOOTP options
48 */
Matthias Fuchs0cb77bf2011-07-19 01:56:06 +000049#define CONFIG_BOOTP_BOOTFILESIZE
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +020050
Matthias Fuchs0cb77bf2011-07-19 01:56:06 +000051/*
52 * SDRAM: 1 bank, min 32, max 128 MB
53 * Initialized before u-boot gets started.
54 */
Daniel Gorsulowski83bf0052015-11-02 07:59:49 +010055#define PHYS_SDRAM ATMEL_BASE_CS1 /* 0x20000000 */
56#define PHYS_SDRAM_SIZE 0x02000000 /* 32 MByte */
57
Daniel Gorsulowski83bf0052015-11-02 07:59:49 +010058#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
59#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_SIZE
Matthias Fuchs0cb77bf2011-07-19 01:56:06 +000060
61#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x00100000)
62#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x01E00000)
63#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x00100000)
64
65/*
66 * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
67 * leaving the correct space for initial global data structure above
68 * that address while providing maximum stack area below.
69 */
70#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou.Yang@microchip.coma8187042017-07-21 17:06:40 +080071 (ATMEL_BASE_SRAM0 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +020072
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +020073/* NAND flash */
74#ifdef CONFIG_CMD_NAND
Matthias Fuchs0cb77bf2011-07-19 01:56:06 +000075# define CONFIG_SYS_MAX_NAND_DEVICE 1
Daniel Gorsulowski83bf0052015-11-02 07:59:49 +010076# define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */
Matthias Fuchs0cb77bf2011-07-19 01:56:06 +000077# define CONFIG_SYS_NAND_DBW_8
78# define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
79# define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Andreas Bießmannac45bb12013-11-29 12:13:45 +010080# define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(15)
81# define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PA(22)
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +020082#endif
83
84/* Ethernet */
Matthias Fuchs0cb77bf2011-07-19 01:56:06 +000085#define CONFIG_MACB
86#define CONFIG_RMII
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +020087#define CONFIG_NET_RETRY_COUNT 20
88#undef CONFIG_RESET_PHY_R
89
Daniel Gorsulowskia3802792009-09-29 08:03:12 +020090/* hw-controller addresses */
Matthias Fuchs0cb77bf2011-07-19 01:56:06 +000091#define CONFIG_ET1100_BASE 0x70000000
92
93#ifdef CONFIG_SYS_USE_DATAFLASH
Daniel Gorsulowskia3802792009-09-29 08:03:12 +020094
95/* bootstrap + u-boot + env in dataflash on CS0 */
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +020096
Matthias Fuchs0cb77bf2011-07-19 01:56:06 +000097#elif CONFIG_SYS_USE_NANDFLASH
98
99/* bootstrap + u-boot + env + linux in nandflash */
Matthias Fuchs0cb77bf2011-07-19 01:56:06 +0000100
101#endif
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +0200102
Matthias Fuchs0cb77bf2011-07-19 01:56:06 +0000103#define CONFIG_SYS_CBSIZE 512
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +0200104
105/*
106 * Size of malloc() pool
107 */
Daniel Gorsulowskia3802792009-09-29 08:03:12 +0200108#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + \
109 128*1024, 0x1000)
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +0200110
Daniel Gorsulowski33b1d3f2009-06-30 21:03:37 +0200111#endif