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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * arch/ppc/kernel/pci_auto.c
3 *
4 * PCI autoconfiguration library
5 *
6 * Author: Matt Porter <mporter@mvista.com>
7 *
8 * Copyright 2000 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#include <common.h>
17
wdenkc6097192002-11-03 00:24:07 +000018#include <pci.h>
19
20#undef DEBUG
21#ifdef DEBUG
22#define DEBUGF(x...) printf(x)
23#else
24#define DEBUGF(x...)
25#endif /* DEBUG */
26
27#define PCIAUTO_IDE_MODE_MASK 0x05
28
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020029/* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
30#ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
31#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
Gary Jennejohn81b73de2007-08-31 15:21:46 +020032#endif
33
wdenkc6097192002-11-03 00:24:07 +000034/*
35 *
36 */
37
38void pciauto_region_init(struct pci_region* res)
39{
Sergei Shtylyovb7598a42007-04-23 15:30:39 +020040 /*
41 * Avoid allocating PCI resources from address 0 -- this is illegal
42 * according to PCI 2.1 and moreover, this is known to cause Linux IDE
43 * drivers to fail. Use a reasonable starting value of 0x1000 instead.
44 */
45 res->bus_lower = res->bus_start ? res->bus_start : 0x1000;
wdenkc6097192002-11-03 00:24:07 +000046}
47
Kumar Gala30e76d52008-10-21 08:36:08 -050048void pciauto_region_align(struct pci_region *res, pci_size_t size)
wdenkc6097192002-11-03 00:24:07 +000049{
50 res->bus_lower = ((res->bus_lower - 1) | (size - 1)) + 1;
51}
52
Kumar Gala30e76d52008-10-21 08:36:08 -050053int pciauto_region_allocate(struct pci_region* res, pci_size_t size, pci_addr_t *bar)
wdenkc6097192002-11-03 00:24:07 +000054{
Kumar Gala30e76d52008-10-21 08:36:08 -050055 pci_addr_t addr;
wdenkc6097192002-11-03 00:24:07 +000056
wdenk3c74e322004-02-22 23:46:08 +000057 if (!res) {
wdenkc6097192002-11-03 00:24:07 +000058 DEBUGF("No resource");
59 goto error;
60 }
61
62 addr = ((res->bus_lower - 1) | (size - 1)) + 1;
63
wdenk3c74e322004-02-22 23:46:08 +000064 if (addr - res->bus_start + size > res->size) {
wdenkc6097192002-11-03 00:24:07 +000065 DEBUGF("No room in resource");
66 goto error;
67 }
68
69 res->bus_lower = addr + size;
70
Kumar Gala30e76d52008-10-21 08:36:08 -050071 DEBUGF("address=0x%llx bus_lower=0x%llx", (u64)addr, (u64)res->bus_lower);
wdenkc6097192002-11-03 00:24:07 +000072
73 *bar = addr;
74 return 0;
75
76 error:
Kumar Gala30e76d52008-10-21 08:36:08 -050077 *bar = (pci_addr_t)-1;
wdenkc6097192002-11-03 00:24:07 +000078 return -1;
79}
80
81/*
82 *
83 */
84
85void pciauto_setup_device(struct pci_controller *hose,
86 pci_dev_t dev, int bars_num,
87 struct pci_region *mem,
Kumar Galaa1790122006-01-11 13:24:15 -060088 struct pci_region *prefetch,
wdenkc6097192002-11-03 00:24:07 +000089 struct pci_region *io)
90{
Kumar Gala30e76d52008-10-21 08:36:08 -050091 unsigned int bar_response;
92 pci_addr_t bar_value;
93 pci_size_t bar_size;
wdenkc6097192002-11-03 00:24:07 +000094 unsigned int cmdstat = 0;
95 struct pci_region *bar_res;
96 int bar, bar_nr = 0;
97 int found_mem64 = 0;
98
99 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
100 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) | PCI_COMMAND_MASTER;
101
Ed Swarthout936b3e62007-07-27 01:50:44 -0500102 for (bar = PCI_BASE_ADDRESS_0; bar < PCI_BASE_ADDRESS_0 + (bars_num*4); bar += 4) {
wdenkc6097192002-11-03 00:24:07 +0000103 /* Tickle the BAR and get the response */
104 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
105 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
106
107 /* If BAR is not implemented go to the next BAR */
108 if (!bar_response)
109 continue;
110
111 found_mem64 = 0;
112
113 /* Check the BAR type and set our address mask */
wdenk3c74e322004-02-22 23:46:08 +0000114 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
Jin Zhengxiong-R64188bd22c2b2006-06-27 18:12:02 +0800115 bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
116 & 0xffff) + 1;
wdenkc6097192002-11-03 00:24:07 +0000117 bar_res = io;
118
Kumar Gala30e76d52008-10-21 08:36:08 -0500119 DEBUGF("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ", bar_nr, (u64)bar_size);
wdenk3c74e322004-02-22 23:46:08 +0000120 } else {
wdenkc6097192002-11-03 00:24:07 +0000121 if ( (bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
Kumar Gala30e76d52008-10-21 08:36:08 -0500122 PCI_BASE_ADDRESS_MEM_TYPE_64) {
123 u32 bar_response_upper;
124 u64 bar64;
125 pci_hose_write_config_dword(hose, dev, bar+4, 0xffffffff);
126 pci_hose_read_config_dword(hose, dev, bar+4, &bar_response_upper);
wdenkc6097192002-11-03 00:24:07 +0000127
Kumar Gala30e76d52008-10-21 08:36:08 -0500128 bar64 = ((u64)bar_response_upper << 32) | bar_response;
129
130 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
131 found_mem64 = 1;
132 } else {
133 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
134 }
Kumar Galaa1790122006-01-11 13:24:15 -0600135 if (prefetch && (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
136 bar_res = prefetch;
137 else
138 bar_res = mem;
wdenkc6097192002-11-03 00:24:07 +0000139
Kumar Gala30e76d52008-10-21 08:36:08 -0500140 DEBUGF("PCI Autoconfig: BAR %d, Mem, size=0x%llx, ", bar_nr, (u64)bar_size);
wdenkc6097192002-11-03 00:24:07 +0000141 }
142
wdenk3c74e322004-02-22 23:46:08 +0000143 if (pciauto_region_allocate(bar_res, bar_size, &bar_value) == 0) {
wdenkc6097192002-11-03 00:24:07 +0000144 /* Write it out and update our limit */
Kumar Gala30e76d52008-10-21 08:36:08 -0500145 pci_hose_write_config_dword(hose, dev, bar, (u32)bar_value);
wdenkc6097192002-11-03 00:24:07 +0000146
wdenk3c74e322004-02-22 23:46:08 +0000147 if (found_mem64) {
wdenkc6097192002-11-03 00:24:07 +0000148 bar += 4;
Kumar Gala30e76d52008-10-21 08:36:08 -0500149#ifdef CONFIG_SYS_PCI_64BIT
150 pci_hose_write_config_dword(hose, dev, bar, (u32)(bar_value>>32));
151#else
152 /*
153 * If we are a 64-bit decoder then increment to the
154 * upper 32 bits of the bar and force it to locate
155 * in the lower 4GB of memory.
156 */
wdenkc6097192002-11-03 00:24:07 +0000157 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
Kumar Gala30e76d52008-10-21 08:36:08 -0500158#endif
wdenkc6097192002-11-03 00:24:07 +0000159 }
160
161 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
162 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
163 }
164
165 DEBUGF("\n");
166
167 bar_nr++;
168 }
169
170 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
Gary Jennejohn81b73de2007-08-31 15:21:46 +0200171 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE,
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
wdenkc6097192002-11-03 00:24:07 +0000173 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
174}
175
Ed Swarthoutba5feb12007-07-11 14:51:48 -0500176void pciauto_prescan_setup_bridge(struct pci_controller *hose,
wdenkc6097192002-11-03 00:24:07 +0000177 pci_dev_t dev, int sub_bus)
178{
179 struct pci_region *pci_mem = hose->pci_mem;
Kumar Galaa1790122006-01-11 13:24:15 -0600180 struct pci_region *pci_prefetch = hose->pci_prefetch;
wdenkc6097192002-11-03 00:24:07 +0000181 struct pci_region *pci_io = hose->pci_io;
182 unsigned int cmdstat;
183
184 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
185
186 /* Configure bus number registers */
Ed Swarthoute8b85f32007-07-11 14:52:08 -0500187 pci_hose_write_config_byte(hose, dev, PCI_PRIMARY_BUS,
188 PCI_BUS(dev) - hose->first_busno);
189 pci_hose_write_config_byte(hose, dev, PCI_SECONDARY_BUS,
190 sub_bus - hose->first_busno);
wdenkc6097192002-11-03 00:24:07 +0000191 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS, 0xff);
192
wdenk3c74e322004-02-22 23:46:08 +0000193 if (pci_mem) {
wdenkc6097192002-11-03 00:24:07 +0000194 /* Round memory allocator to 1MB boundary */
195 pciauto_region_align(pci_mem, 0x100000);
196
197 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
198 pci_hose_write_config_word(hose, dev, PCI_MEMORY_BASE,
199 (pci_mem->bus_lower & 0xfff00000) >> 16);
200
201 cmdstat |= PCI_COMMAND_MEMORY;
202 }
203
Kumar Galaa1790122006-01-11 13:24:15 -0600204 if (pci_prefetch) {
205 /* Round memory allocator to 1MB boundary */
206 pciauto_region_align(pci_prefetch, 0x100000);
207
208 /* Set up memory and I/O filter limits, assume 32-bit I/O space */
209 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE,
210 (pci_prefetch->bus_lower & 0xfff00000) >> 16);
211
212 cmdstat |= PCI_COMMAND_MEMORY;
213 } else {
214 /* We don't support prefetchable memory for now, so disable */
215 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_BASE, 0x1000);
Matthew McClintocka4e11552006-06-28 10:44:23 -0500216 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT, 0x0);
Kumar Galaa1790122006-01-11 13:24:15 -0600217 }
218
wdenk3c74e322004-02-22 23:46:08 +0000219 if (pci_io) {
wdenkc6097192002-11-03 00:24:07 +0000220 /* Round I/O allocator to 4KB boundary */
221 pciauto_region_align(pci_io, 0x1000);
222
223 pci_hose_write_config_byte(hose, dev, PCI_IO_BASE,
224 (pci_io->bus_lower & 0x0000f000) >> 8);
225 pci_hose_write_config_word(hose, dev, PCI_IO_BASE_UPPER16,
226 (pci_io->bus_lower & 0xffff0000) >> 16);
227
228 cmdstat |= PCI_COMMAND_IO;
229 }
230
wdenkc6097192002-11-03 00:24:07 +0000231 /* Enable memory and I/O accesses, enable bus master */
232 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
233}
234
Ed Swarthoutba5feb12007-07-11 14:51:48 -0500235void pciauto_postscan_setup_bridge(struct pci_controller *hose,
wdenkc6097192002-11-03 00:24:07 +0000236 pci_dev_t dev, int sub_bus)
237{
238 struct pci_region *pci_mem = hose->pci_mem;
Kumar Galaa1790122006-01-11 13:24:15 -0600239 struct pci_region *pci_prefetch = hose->pci_prefetch;
wdenkc6097192002-11-03 00:24:07 +0000240 struct pci_region *pci_io = hose->pci_io;
241
242 /* Configure bus number registers */
Ed Swarthoute8b85f32007-07-11 14:52:08 -0500243 pci_hose_write_config_byte(hose, dev, PCI_SUBORDINATE_BUS,
244 sub_bus - hose->first_busno);
wdenkc6097192002-11-03 00:24:07 +0000245
wdenk3c74e322004-02-22 23:46:08 +0000246 if (pci_mem) {
wdenkc6097192002-11-03 00:24:07 +0000247 /* Round memory allocator to 1MB boundary */
248 pciauto_region_align(pci_mem, 0x100000);
249
250 pci_hose_write_config_word(hose, dev, PCI_MEMORY_LIMIT,
251 (pci_mem->bus_lower-1) >> 16);
252 }
253
Kumar Galaa1790122006-01-11 13:24:15 -0600254 if (pci_prefetch) {
255 /* Round memory allocator to 1MB boundary */
256 pciauto_region_align(pci_prefetch, 0x100000);
257
258 pci_hose_write_config_word(hose, dev, PCI_PREF_MEMORY_LIMIT,
259 (pci_prefetch->bus_lower-1) >> 16);
260 }
261
wdenk3c74e322004-02-22 23:46:08 +0000262 if (pci_io) {
wdenkc6097192002-11-03 00:24:07 +0000263 /* Round I/O allocator to 4KB boundary */
264 pciauto_region_align(pci_io, 0x1000);
265
266 pci_hose_write_config_byte(hose, dev, PCI_IO_LIMIT,
267 ((pci_io->bus_lower-1) & 0x0000f000) >> 8);
268 pci_hose_write_config_word(hose, dev, PCI_IO_LIMIT_UPPER16,
269 ((pci_io->bus_lower-1) & 0xffff0000) >> 16);
270 }
271}
272
273/*
274 *
275 */
276
277void pciauto_config_init(struct pci_controller *hose)
278{
279 int i;
280
281 hose->pci_io = hose->pci_mem = NULL;
282
wdenk3c74e322004-02-22 23:46:08 +0000283 for (i=0; i<hose->region_count; i++) {
284 switch(hose->regions[i].flags) {
wdenkc6097192002-11-03 00:24:07 +0000285 case PCI_REGION_IO:
286 if (!hose->pci_io ||
287 hose->pci_io->size < hose->regions[i].size)
288 hose->pci_io = hose->regions + i;
289 break;
290 case PCI_REGION_MEM:
291 if (!hose->pci_mem ||
292 hose->pci_mem->size < hose->regions[i].size)
293 hose->pci_mem = hose->regions + i;
294 break;
Kumar Galaa1790122006-01-11 13:24:15 -0600295 case (PCI_REGION_MEM | PCI_REGION_PREFETCH):
296 if (!hose->pci_prefetch ||
297 hose->pci_prefetch->size < hose->regions[i].size)
298 hose->pci_prefetch = hose->regions + i;
299 break;
wdenkc6097192002-11-03 00:24:07 +0000300 }
301 }
302
303
wdenk3c74e322004-02-22 23:46:08 +0000304 if (hose->pci_mem) {
wdenkc6097192002-11-03 00:24:07 +0000305 pciauto_region_init(hose->pci_mem);
306
Kumar Gala30e76d52008-10-21 08:36:08 -0500307 DEBUGF("PCI Autoconfig: Bus Memory region: [0x%llx-0x%llx],\n"
308 "\t\tPhysical Memory [%llx-%llxx]\n",
309 (u64)hose->pci_mem->bus_start,
310 (u64)(hose->pci_mem->bus_start + hose->pci_mem->size - 1),
311 (u64)hose->pci_mem->phys_start,
312 (u64)(hose->pci_mem->phys_start + hose->pci_mem->size - 1));
wdenkc6097192002-11-03 00:24:07 +0000313 }
314
Kumar Galaa1790122006-01-11 13:24:15 -0600315 if (hose->pci_prefetch) {
316 pciauto_region_init(hose->pci_prefetch);
317
Kumar Gala30e76d52008-10-21 08:36:08 -0500318 DEBUGF("PCI Autoconfig: Bus Prefetchable Mem: [0x%llx-0x%llx],\n"
319 "\t\tPhysical Memory [%llx-%llx]\n",
320 (u64)hose->pci_prefetch->bus_start,
321 (u64)(hose->pci_prefetch->bus_start +
322 hose->pci_prefetch->size - 1),
323 (u64)hose->pci_prefetch->phys_start,
324 (u64)(hose->pci_prefetch->phys_start +
325 hose->pci_prefetch->size - 1));
Kumar Galaa1790122006-01-11 13:24:15 -0600326 }
327
wdenk3c74e322004-02-22 23:46:08 +0000328 if (hose->pci_io) {
wdenkc6097192002-11-03 00:24:07 +0000329 pciauto_region_init(hose->pci_io);
330
Kumar Gala30e76d52008-10-21 08:36:08 -0500331 DEBUGF("PCI Autoconfig: Bus I/O region: [0x%llx-0x%llx],\n"
332 "\t\tPhysical Memory: [%llx-%llx]\n",
333 (u64)hose->pci_io->bus_start,
334 (u64)(hose->pci_io->bus_start + hose->pci_io->size - 1),
335 (u64)hose->pci_io->phys_start,
336 (u64)(hose->pci_io->phys_start + hose->pci_io->size - 1));
Ed Swarthoutba5feb12007-07-11 14:51:48 -0500337
wdenkc6097192002-11-03 00:24:07 +0000338 }
339}
340
wdenkc7de8292002-11-19 11:04:11 +0000341/* HJF: Changed this to return int. I think this is required
342 * to get the correct result when scanning bridges
343 */
344int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev)
wdenkc6097192002-11-03 00:24:07 +0000345{
wdenkc7de8292002-11-19 11:04:11 +0000346 unsigned int sub_bus = PCI_BUS(dev);
wdenkc6097192002-11-03 00:24:07 +0000347 unsigned short class;
348 unsigned char prg_iface;
wdenk5653fc32004-02-08 22:55:38 +0000349 int n;
wdenkc6097192002-11-03 00:24:07 +0000350
351 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
352
wdenk3c74e322004-02-22 23:46:08 +0000353 switch(class) {
Ed Swarthout5dc210d2007-07-11 14:52:16 -0500354 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
355 DEBUGF("PCI AutoConfig: Found PowerPC device\n");
356 pciauto_setup_device(hose, dev, 6, hose->pci_mem,
357 hose->pci_prefetch, hose->pci_io);
358 break;
359
wdenkc6097192002-11-03 00:24:07 +0000360 case PCI_CLASS_BRIDGE_PCI:
wdenkdb2f721f2003-03-06 00:58:30 +0000361 hose->current_busno++;
Kumar Galaa1790122006-01-11 13:24:15 -0600362 pciauto_setup_device(hose, dev, 2, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
wdenkc6097192002-11-03 00:24:07 +0000363
wdenkdb2f721f2003-03-06 00:58:30 +0000364 DEBUGF("PCI Autoconfig: Found P2P bridge, device %d\n", PCI_DEV(dev));
wdenkcd37d9e2004-02-10 00:03:41 +0000365
wdenk3c74e322004-02-22 23:46:08 +0000366 /* Passing in current_busno allows for sibling P2P bridges */
wdenk5653fc32004-02-08 22:55:38 +0000367 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
wdenkcd37d9e2004-02-10 00:03:41 +0000368 /*
wdenk3c74e322004-02-22 23:46:08 +0000369 * need to figure out if this is a subordinate bridge on the bus
wdenk5653fc32004-02-08 22:55:38 +0000370 * to be able to properly set the pri/sec/sub bridge registers.
371 */
372 n = pci_hose_scan_bus(hose, hose->current_busno);
wdenk8bde7f72003-06-27 21:31:46 +0000373
wdenk3c74e322004-02-22 23:46:08 +0000374 /* figure out the deepest we've gone for this leg */
wdenk5653fc32004-02-08 22:55:38 +0000375 sub_bus = max(n, sub_bus);
wdenkdb2f721f2003-03-06 00:58:30 +0000376 pciauto_postscan_setup_bridge(hose, dev, sub_bus);
wdenk5653fc32004-02-08 22:55:38 +0000377
wdenkdb2f721f2003-03-06 00:58:30 +0000378 sub_bus = hose->current_busno;
wdenkc6097192002-11-03 00:24:07 +0000379 break;
380
381 case PCI_CLASS_STORAGE_IDE:
382 pci_hose_read_config_byte(hose, dev, PCI_CLASS_PROG, &prg_iface);
wdenk3c74e322004-02-22 23:46:08 +0000383 if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
384 DEBUGF("PCI Autoconfig: Skipping legacy mode IDE controller\n");
385 return sub_bus;
386 }
wdenkc6097192002-11-03 00:24:07 +0000387
Kumar Galaa1790122006-01-11 13:24:15 -0600388 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
wdenkc6097192002-11-03 00:24:07 +0000389 break;
390
wdenk1cb8e982003-03-06 21:55:29 +0000391 case PCI_CLASS_BRIDGE_CARDBUS:
392 /* just do a minimal setup of the bridge, let the OS take care of the rest */
Kumar Galaa1790122006-01-11 13:24:15 -0600393 pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
wdenk1cb8e982003-03-06 21:55:29 +0000394
wdenk3c74e322004-02-22 23:46:08 +0000395 DEBUGF("PCI Autoconfig: Found P2CardBus bridge, device %d\n", PCI_DEV(dev));
wdenk1cb8e982003-03-06 21:55:29 +0000396
397 hose->current_busno++;
398 break;
399
TsiChung Liewf33fca22008-03-30 01:19:06 -0500400#if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
wdenke0ac62d2003-08-17 18:55:18 +0000401 case PCI_CLASS_BRIDGE_OTHER:
402 DEBUGF("PCI Autoconfig: Skipping bridge device %d\n",
403 PCI_DEV(dev));
404 break;
405#endif
Reinhard Arltc2e49f72009-07-25 06:19:12 +0200406#if defined(CONFIG_MPC834x) && !defined(CONFIG_VME8349)
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200407 case PCI_CLASS_BRIDGE_OTHER:
408 /*
409 * The host/PCI bridge 1 seems broken in 8349 - it presents
410 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
411 * device claiming resources io/mem/irq.. we only allow for
412 * the PIMMR window to be allocated (BAR0 - 1MB size)
413 */
414 DEBUGF("PCI Autoconfig: Broken bridge found, only minimal config\n");
Kumar Galaa1790122006-01-11 13:24:15 -0600415 pciauto_setup_device(hose, dev, 0, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200416 break;
417#endif
wdenkc6097192002-11-03 00:24:07 +0000418 default:
Kumar Galaa1790122006-01-11 13:24:15 -0600419 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
wdenkc6097192002-11-03 00:24:07 +0000420 break;
421 }
wdenkc7de8292002-11-19 11:04:11 +0000422
423 return sub_bus;
wdenkc6097192002-11-03 00:24:07 +0000424}