blob: 33c6d52bfe950ec3fe2739288690baa31beb0bf2 [file] [log] [blame]
Yangbo Lufa33d202019-06-21 11:42:27 +08001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * FSL SD/MMC Defines
4 *-------------------------------------------------------------------
5 *
6 * Copyright 2019 NXP
7 * Yangbo Lu <yangbo.lu@nxp.com>
8 *
9 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
10 */
11
12#ifndef __FSL_ESDHC_IMX_H__
13#define __FSL_ESDHC_IMX_H__
14
15#include <linux/bitops.h>
16#include <linux/errno.h>
17#include <asm/byteorder.h>
18
19/* needed for the mmc_cfg definition */
20#include <mmc.h>
21
Yangbo Lufa33d202019-06-21 11:42:27 +080022/* FSL eSDHC-specific constants */
23#define SYSCTL 0x0002e02c
24#define SYSCTL_INITA 0x08000000
25#define SYSCTL_TIMEOUT_MASK 0x000f0000
26#define SYSCTL_CLOCK_MASK 0x0000fff0
27#if !defined(CONFIG_FSL_USDHC)
28#define SYSCTL_CKEN 0x00000008
29#define SYSCTL_PEREN 0x00000004
30#define SYSCTL_HCKEN 0x00000002
31#define SYSCTL_IPGEN 0x00000001
32#endif
33#define SYSCTL_RSTA 0x01000000
34#define SYSCTL_RSTC 0x02000000
35#define SYSCTL_RSTD 0x04000000
36
37#define VENDORSPEC_CKEN 0x00004000
38#define VENDORSPEC_PEREN 0x00002000
39#define VENDORSPEC_HCKEN 0x00001000
40#define VENDORSPEC_IPGEN 0x00000800
41#define VENDORSPEC_INIT 0x20007809
42
43#define IRQSTAT 0x0002e030
44#define IRQSTAT_DMAE (0x10000000)
45#define IRQSTAT_AC12E (0x01000000)
46#define IRQSTAT_DEBE (0x00400000)
47#define IRQSTAT_DCE (0x00200000)
48#define IRQSTAT_DTOE (0x00100000)
49#define IRQSTAT_CIE (0x00080000)
50#define IRQSTAT_CEBE (0x00040000)
51#define IRQSTAT_CCE (0x00020000)
52#define IRQSTAT_CTOE (0x00010000)
53#define IRQSTAT_CINT (0x00000100)
54#define IRQSTAT_CRM (0x00000080)
55#define IRQSTAT_CINS (0x00000040)
56#define IRQSTAT_BRR (0x00000020)
57#define IRQSTAT_BWR (0x00000010)
58#define IRQSTAT_DINT (0x00000008)
59#define IRQSTAT_BGE (0x00000004)
60#define IRQSTAT_TC (0x00000002)
61#define IRQSTAT_CC (0x00000001)
62
63#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
64#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
65 IRQSTAT_DMAE)
66#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT)
67
68#define IRQSTATEN 0x0002e034
69#define IRQSTATEN_DMAE (0x10000000)
70#define IRQSTATEN_AC12E (0x01000000)
71#define IRQSTATEN_DEBE (0x00400000)
72#define IRQSTATEN_DCE (0x00200000)
73#define IRQSTATEN_DTOE (0x00100000)
74#define IRQSTATEN_CIE (0x00080000)
75#define IRQSTATEN_CEBE (0x00040000)
76#define IRQSTATEN_CCE (0x00020000)
77#define IRQSTATEN_CTOE (0x00010000)
78#define IRQSTATEN_CINT (0x00000100)
79#define IRQSTATEN_CRM (0x00000080)
80#define IRQSTATEN_CINS (0x00000040)
81#define IRQSTATEN_BRR (0x00000020)
82#define IRQSTATEN_BWR (0x00000010)
83#define IRQSTATEN_DINT (0x00000008)
84#define IRQSTATEN_BGE (0x00000004)
85#define IRQSTATEN_TC (0x00000002)
86#define IRQSTATEN_CC (0x00000001)
87
88#define ESDHCCTL 0x0002e40c
89#define ESDHCCTL_PCS (0x00080000)
90
91#define PRSSTAT 0x0002e024
92#define PRSSTAT_DAT0 (0x01000000)
93#define PRSSTAT_CLSL (0x00800000)
94#define PRSSTAT_WPSPL (0x00080000)
95#define PRSSTAT_CDPL (0x00040000)
96#define PRSSTAT_CINS (0x00010000)
97#define PRSSTAT_BREN (0x00000800)
98#define PRSSTAT_BWEN (0x00000400)
99#define PRSSTAT_SDSTB (0X00000008)
100#define PRSSTAT_DLA (0x00000004)
101#define PRSSTAT_CICHB (0x00000002)
102#define PRSSTAT_CIDHB (0x00000001)
103
104#define PROCTL 0x0002e028
105#define PROCTL_INIT 0x00000020
106#define PROCTL_DTW_4 0x00000002
107#define PROCTL_DTW_8 0x00000004
108#define PROCTL_D3CD 0x00000008
109
110#define CMDARG 0x0002e008
111
112#define XFERTYP 0x0002e00c
113#define XFERTYP_CMD(x) ((x & 0x3f) << 24)
114#define XFERTYP_CMDTYP_NORMAL 0x0
115#define XFERTYP_CMDTYP_SUSPEND 0x00400000
116#define XFERTYP_CMDTYP_RESUME 0x00800000
117#define XFERTYP_CMDTYP_ABORT 0x00c00000
118#define XFERTYP_DPSEL 0x00200000
119#define XFERTYP_CICEN 0x00100000
120#define XFERTYP_CCCEN 0x00080000
121#define XFERTYP_RSPTYP_NONE 0
122#define XFERTYP_RSPTYP_136 0x00010000
123#define XFERTYP_RSPTYP_48 0x00020000
124#define XFERTYP_RSPTYP_48_BUSY 0x00030000
125#define XFERTYP_MSBSEL 0x00000020
126#define XFERTYP_DTDSEL 0x00000010
127#define XFERTYP_DDREN 0x00000008
128#define XFERTYP_AC12EN 0x00000004
129#define XFERTYP_BCEN 0x00000002
130#define XFERTYP_DMAEN 0x00000001
131
132#define CINS_TIMEOUT 1000
133#define PIO_TIMEOUT 500
134
135#define DSADDR 0x2e004
136
137#define CMDRSP0 0x2e010
138#define CMDRSP1 0x2e014
139#define CMDRSP2 0x2e018
140#define CMDRSP3 0x2e01c
141
142#define DATPORT 0x2e020
143
144#define WML 0x2e044
145#define WML_WRITE 0x00010000
146#ifdef CONFIG_FSL_SDHC_V2_3
147#define WML_RD_WML_MAX 0x80
148#define WML_WR_WML_MAX 0x80
149#define WML_RD_WML_MAX_VAL 0x0
150#define WML_WR_WML_MAX_VAL 0x0
151#define WML_RD_WML_MASK 0x7f
152#define WML_WR_WML_MASK 0x7f0000
153#else
154#define WML_RD_WML_MAX 0x10
155#define WML_WR_WML_MAX 0x80
156#define WML_RD_WML_MAX_VAL 0x10
157#define WML_WR_WML_MAX_VAL 0x80
158#define WML_RD_WML_MASK 0xff
159#define WML_WR_WML_MASK 0xff0000
160#endif
161
162#define BLKATTR 0x2e004
163#define BLKATTR_CNT(x) ((x & 0xffff) << 16)
164#define BLKATTR_SIZE(x) (x & 0x1fff)
165#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
166
167#define ESDHC_HOSTCAPBLT_VS18 0x04000000
168#define ESDHC_HOSTCAPBLT_VS30 0x02000000
169#define ESDHC_HOSTCAPBLT_VS33 0x01000000
170#define ESDHC_HOSTCAPBLT_SRS 0x00800000
171#define ESDHC_HOSTCAPBLT_DMAS 0x00400000
172#define ESDHC_HOSTCAPBLT_HSS 0x00200000
173
174#define ESDHC_VENDORSPEC_VSELECT 0x00000002 /* Use 1.8V */
175
176/* Imported from Linux Kernel drivers/mmc/host/sdhci-esdhc-imx.c */
177#define MIX_CTRL_DDREN BIT(3)
178#define MIX_CTRL_DTDSEL_READ BIT(4)
179#define MIX_CTRL_AC23EN BIT(7)
180#define MIX_CTRL_EXE_TUNE BIT(22)
181#define MIX_CTRL_SMPCLK_SEL BIT(23)
182#define MIX_CTRL_AUTO_TUNE_EN BIT(24)
183#define MIX_CTRL_FBCLK_SEL BIT(25)
184#define MIX_CTRL_HS400_EN BIT(26)
185#define MIX_CTRL_HS400_ES BIT(27)
186/* Bits 3 and 6 are not SDHCI standard definitions */
187#define MIX_CTRL_SDHCI_MASK 0xb7
188/* Tuning bits */
189#define MIX_CTRL_TUNING_MASK 0x03c00000
190
191/* strobe dll register */
192#define ESDHC_STROBE_DLL_CTRL 0x70
193#define ESDHC_STROBE_DLL_CTRL_ENABLE BIT(0)
194#define ESDHC_STROBE_DLL_CTRL_RESET BIT(1)
195#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7
196#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
197
198#define ESDHC_STROBE_DLL_STATUS 0x74
199#define ESDHC_STROBE_DLL_STS_REF_LOCK BIT(1)
200#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
201#define ESDHC_STROBE_DLL_CLK_FREQ 100000000
202
203#define ESDHC_STD_TUNING_EN BIT(24)
204/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
205#define ESDHC_TUNING_START_TAP_DEFAULT 0x1
206#define ESDHC_TUNING_START_TAP_MASK 0xff
207#define ESDHC_TUNING_STEP_MASK 0x00070000
208#define ESDHC_TUNING_STEP_SHIFT 16
209
210#define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1)
211#define ESDHC_FLAG_ENGCM07207 BIT(2)
212#define ESDHC_FLAG_USDHC BIT(3)
213#define ESDHC_FLAG_MAN_TUNING BIT(4)
214#define ESDHC_FLAG_STD_TUNING BIT(5)
215#define ESDHC_FLAG_HAVE_CAP1 BIT(6)
216#define ESDHC_FLAG_ERR004536 BIT(7)
217#define ESDHC_FLAG_HS200 BIT(8)
218#define ESDHC_FLAG_HS400 BIT(9)
219#define ESDHC_FLAG_ERR010450 BIT(10)
220#define ESDHC_FLAG_HS400_ES BIT(11)
221
222struct fsl_esdhc_cfg {
223 phys_addr_t esdhc_base;
224 u32 sdhc_clk;
225 u8 max_bus_width;
226 int wp_enable;
227 int vs18_enable; /* Use 1.8V if set to 1 */
228 struct mmc_config cfg;
229};
230
231/* Select the correct accessors depending on endianess */
232#if defined CONFIG_SYS_FSL_ESDHC_LE
233#define esdhc_read32 in_le32
234#define esdhc_write32 out_le32
235#define esdhc_clrsetbits32 clrsetbits_le32
236#define esdhc_clrbits32 clrbits_le32
237#define esdhc_setbits32 setbits_le32
238#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
239#define esdhc_read32 in_be32
240#define esdhc_write32 out_be32
241#define esdhc_clrsetbits32 clrsetbits_be32
242#define esdhc_clrbits32 clrbits_be32
243#define esdhc_setbits32 setbits_be32
244#elif __BYTE_ORDER == __LITTLE_ENDIAN
245#define esdhc_read32 in_le32
246#define esdhc_write32 out_le32
247#define esdhc_clrsetbits32 clrsetbits_le32
248#define esdhc_clrbits32 clrbits_le32
249#define esdhc_setbits32 setbits_le32
250#elif __BYTE_ORDER == __BIG_ENDIAN
251#define esdhc_read32 in_be32
252#define esdhc_write32 out_be32
253#define esdhc_clrsetbits32 clrsetbits_be32
254#define esdhc_clrbits32 clrbits_be32
255#define esdhc_setbits32 setbits_be32
256#else
257#error "Endianess is not defined: please fix to continue"
258#endif
259
260#ifdef CONFIG_FSL_ESDHC_IMX
261int fsl_esdhc_mmc_init(bd_t *bis);
262int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
263void fdt_fixup_esdhc(void *blob, bd_t *bd);
264#else
265static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
266static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
267#endif /* CONFIG_FSL_ESDHC_IMX */
268void __noreturn mmc_boot(void);
269void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
270
271#endif /* __FSL_ESDHC_IMX_H__ */