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wdenk1c437712004-01-16 00:30:56 +00001/***********************************************************************
2 *
3 * (C) Copyright 2004
4 * DENX Software Engineering
5 * Wolfgang Denk, wd@denx.de
6 * All rights reserved.
7 *
8 * Simple 16550A serial driver
9 *
10 * Originally from linux source (drivers/char/ps2ser.c)
11 *
12 * Used by the PS/2 multiplexer driver (ps2mult.c)
13 *
14 ***********************************************************************/
15
16#include <common.h>
17
18#ifdef CONFIG_PS2SERIAL
19
20#include <asm/io.h>
21#include <asm/atomic.h>
22#include <ps2mult.h>
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +020023#ifdef CFG_NS16550
24#include <ns16550.h>
25#endif
wdenk1c437712004-01-16 00:30:56 +000026
Wolfgang Denkd87080b2006-03-31 18:32:53 +020027DECLARE_GLOBAL_DATA_PTR;
28
wdenk1c437712004-01-16 00:30:56 +000029/* #define DEBUG */
30
31#define PS2SER_BAUD 57600
32
wdenk7e6bf352004-12-12 22:06:17 +000033#ifdef CONFIG_MPC5xxx
34#if CONFIG_PS2SERIAL == 1
35#define PSC_BASE MPC5XXX_PSC1
36#elif CONFIG_PS2SERIAL == 2
37#define PSC_BASE MPC5XXX_PSC2
38#elif CONFIG_PS2SERIAL == 3
39#define PSC_BASE MPC5XXX_PSC3
40#elif defined(CONFIG_MGT5100)
41#error CONFIG_PS2SERIAL must be in 1, 2 or 3
42#elif CONFIG_PS2SERIAL == 4
43#define PSC_BASE MPC5XXX_PSC4
44#elif CONFIG_PS2SERIAL == 5
45#define PSC_BASE MPC5XXX_PSC5
46#elif CONFIG_PS2SERIAL == 6
47#define PSC_BASE MPC5XXX_PSC6
48#else
49#error CONFIG_PS2SERIAL must be in 1 ... 6
50#endif
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +020051
52#elif defined(CONFIG_MPC85xx)
53
54#if CONFIG_PS2SERIAL == 1
55#define COM_BASE (CFG_CCSRBAR+0x4500)
56#elif CONFIG_PS2SERIAL == 2
57#define COM_BASE (CFG_CCSRBAR+0x4600)
58#else
59#error CONFIG_PS2SERIAL must be in 1 ... 2
60#endif
61
62#endif /* CONFIG_MPC5xxx / CONFIG_MPC85xx */
wdenk7e6bf352004-12-12 22:06:17 +000063
wdenk1c437712004-01-16 00:30:56 +000064static int ps2ser_getc_hw(void);
65static void ps2ser_interrupt(void *dev_id);
66
67extern struct serial_state rs_table[]; /* in serial.c */
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +020068#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC85xx)
wdenkef978732004-01-21 20:46:28 +000069static struct serial_state *state;
wdenk7e6bf352004-12-12 22:06:17 +000070#endif
wdenk1c437712004-01-16 00:30:56 +000071
72static u_char ps2buf[PS2BUF_SIZE];
73static atomic_t ps2buf_cnt;
74static int ps2buf_in_idx;
75static int ps2buf_out_idx;
76
wdenk7e6bf352004-12-12 22:06:17 +000077#ifdef CONFIG_MPC5xxx
78int ps2ser_init(void)
79{
wdenk7e6bf352004-12-12 22:06:17 +000080 volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
81 unsigned long baseclk;
82 int div;
83
84 /* reset PSC */
85 psc->command = PSC_SEL_MODE_REG_1;
86
87 /* select clock sources */
88#if defined(CONFIG_MGT5100)
89 psc->psc_clock_select = 0xdd00;
90 baseclk = (CFG_MPC5XXX_CLKIN + 16) / 32;
91#elif defined(CONFIG_MPC5200)
92 psc->psc_clock_select = 0;
93 baseclk = (gd->ipb_clk + 16) / 32;
94#endif
95
96 /* switch to UART mode */
97 psc->sicr = 0;
98
99 /* configure parity, bit length and so on */
100#if defined(CONFIG_MGT5100)
101 psc->mode = PSC_MODE_ERR | PSC_MODE_8_BITS | PSC_MODE_PARNONE;
102#elif defined(CONFIG_MPC5200)
103 psc->mode = PSC_MODE_8_BITS | PSC_MODE_PARNONE;
104#endif
105 psc->mode = PSC_MODE_ONE_STOP;
106
107 /* set up UART divisor */
108 div = (baseclk + (PS2SER_BAUD/2)) / PS2SER_BAUD;
109 psc->ctur = (div >> 8) & 0xff;
110 psc->ctlr = div & 0xff;
111
112 /* disable all interrupts */
113 psc->psc_imr = 0;
114
115 /* reset and enable Rx/Tx */
116 psc->command = PSC_RST_RX;
117 psc->command = PSC_RST_TX;
118 psc->command = PSC_RX_ENABLE | PSC_TX_ENABLE;
119
120 return (0);
121}
122
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +0200123#elif defined(CONFIG_MPC85xx)
124int ps2ser_init(void)
125{
126 NS16550_t com_port = (NS16550_t)COM_BASE;
127
128 com_port->ier = 0x00;
129 com_port->lcr = LCR_BKSE | LCR_8N1;
130 com_port->dll = (CFG_NS16550_CLK / 16 / PS2SER_BAUD) & 0xff;
131 com_port->dlm = ((CFG_NS16550_CLK / 16 / PS2SER_BAUD) >> 8) & 0xff;
132 com_port->lcr = LCR_8N1;
133 com_port->mcr = (MCR_DTR | MCR_RTS);
134 com_port->fcr = (FCR_FIFO_EN | FCR_RXSR | FCR_TXSR);
135
136 return (0);
137}
138
139#else /* !CONFIG_MPC5xxx && !CONFIG_MPC85xx */
wdenk1c437712004-01-16 00:30:56 +0000140
141static inline unsigned int ps2ser_in(int offset)
142{
143 return readb((unsigned long) state->iomem_base + offset);
144}
145
146static inline void ps2ser_out(int offset, int value)
147{
148 writeb(value, (unsigned long) state->iomem_base + offset);
149}
150
151int ps2ser_init(void)
152{
wdenkef978732004-01-21 20:46:28 +0000153 int quot;
154 unsigned cval;
155
156 state = rs_table + CONFIG_PS2SERIAL;
157
158 quot = state->baud_base / PS2SER_BAUD;
159 cval = 0x3; /* 8N1 - 8 data bits, no parity bits, 1 stop bit */
wdenk1c437712004-01-16 00:30:56 +0000160
161 /* Set speed, enable interrupts, enable FIFO
162 */
163 ps2ser_out(UART_LCR, cval | UART_LCR_DLAB);
164 ps2ser_out(UART_DLL, quot & 0xff);
165 ps2ser_out(UART_DLM, quot >> 8);
166 ps2ser_out(UART_LCR, cval);
167 ps2ser_out(UART_IER, UART_IER_RDI);
168 ps2ser_out(UART_MCR, UART_MCR_OUT2 | UART_MCR_DTR | UART_MCR_RTS);
169 ps2ser_out(UART_FCR,
170 UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
171
172 /* If we read 0xff from the LSR, there is no UART here
173 */
174 if (ps2ser_in(UART_LSR) == 0xff) {
175 printf ("ps2ser.c: no UART found\n");
176 return -1;
177 }
178
179 irq_install_handler(state->irq, ps2ser_interrupt, NULL);
180
181 return 0;
182}
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +0200183#endif /* CONFIG_MPC5xxx / CONFIG_MPC85xx / other */
wdenk1c437712004-01-16 00:30:56 +0000184
185void ps2ser_putc(int chr)
186{
wdenk7e6bf352004-12-12 22:06:17 +0000187#ifdef CONFIG_MPC5xxx
188 volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +0200189#elif defined(CONFIG_MPC85xx)
190 NS16550_t com_port = (NS16550_t)COM_BASE;
wdenk7e6bf352004-12-12 22:06:17 +0000191#endif
wdenk1c437712004-01-16 00:30:56 +0000192#ifdef DEBUG
193 printf(">>>> 0x%02x\n", chr);
194#endif
195
wdenk7e6bf352004-12-12 22:06:17 +0000196#ifdef CONFIG_MPC5xxx
197 while (!(psc->psc_status & PSC_SR_TXRDY));
wdenkefe2a4d2004-12-16 21:44:03 +0000198
wdenk7e6bf352004-12-12 22:06:17 +0000199 psc->psc_buffer_8 = chr;
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +0200200#elif defined(CONFIG_MPC85xx)
201 while ((com_port->lsr & LSR_THRE) == 0);
202 com_port->thr = chr;
wdenk7e6bf352004-12-12 22:06:17 +0000203#else
wdenk1c437712004-01-16 00:30:56 +0000204 while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE));
205
206 ps2ser_out(UART_TX, chr);
wdenk7e6bf352004-12-12 22:06:17 +0000207#endif
wdenk1c437712004-01-16 00:30:56 +0000208}
209
210static int ps2ser_getc_hw(void)
211{
wdenk7e6bf352004-12-12 22:06:17 +0000212#ifdef CONFIG_MPC5xxx
213 volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +0200214#elif defined(CONFIG_MPC85xx)
215 NS16550_t com_port = (NS16550_t)COM_BASE;
wdenk7e6bf352004-12-12 22:06:17 +0000216#endif
wdenk1c437712004-01-16 00:30:56 +0000217 int res = -1;
218
wdenk7e6bf352004-12-12 22:06:17 +0000219#ifdef CONFIG_MPC5xxx
220 if (psc->psc_status & PSC_SR_RXRDY) {
221 res = (psc->psc_buffer_8);
222 }
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +0200223#elif defined(CONFIG_MPC85xx)
224 if (com_port->lsr & LSR_DR) {
225 res = com_port->rbr;
226 }
wdenk7e6bf352004-12-12 22:06:17 +0000227#else
wdenk1c437712004-01-16 00:30:56 +0000228 if (ps2ser_in(UART_LSR) & UART_LSR_DR) {
229 res = (ps2ser_in(UART_RX));
230 }
wdenk7e6bf352004-12-12 22:06:17 +0000231#endif
wdenk1c437712004-01-16 00:30:56 +0000232
233 return res;
234}
235
236int ps2ser_getc(void)
237{
238 volatile int chr;
239 int flags;
240
241#ifdef DEBUG
242 printf("<< ");
243#endif
244
245 flags = disable_interrupts();
246
247 do {
248 if (atomic_read(&ps2buf_cnt) != 0) {
249 chr = ps2buf[ps2buf_out_idx++];
250 ps2buf_out_idx &= (PS2BUF_SIZE - 1);
251 atomic_dec(&ps2buf_cnt);
252 } else {
253 chr = ps2ser_getc_hw();
254 }
255 }
256 while (chr < 0);
257
258 if (flags) enable_interrupts();
259
260#ifdef DEBUG
261 printf("0x%02x\n", chr);
262#endif
263
264 return chr;
265}
266
267int ps2ser_check(void)
268{
269 int flags;
270
271 flags = disable_interrupts();
272 ps2ser_interrupt(NULL);
273 if (flags) enable_interrupts();
274
275 return atomic_read(&ps2buf_cnt);
276}
277
278static void ps2ser_interrupt(void *dev_id)
279{
wdenk7e6bf352004-12-12 22:06:17 +0000280#ifdef CONFIG_MPC5xxx
281 volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +0200282#elif defined(CONFIG_MPC85xx)
283 NS16550_t com_port = (NS16550_t)COM_BASE;
wdenk7e6bf352004-12-12 22:06:17 +0000284#endif
wdenk1c437712004-01-16 00:30:56 +0000285 int chr;
wdenk7e6bf352004-12-12 22:06:17 +0000286 int status;
wdenk1c437712004-01-16 00:30:56 +0000287
288 do {
289 chr = ps2ser_getc_hw();
wdenk7e6bf352004-12-12 22:06:17 +0000290#ifdef CONFIG_MPC5xxx
291 status = psc->psc_status;
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +0200292#elif defined(CONFIG_MPC85xx)
293 status = com_port->lsr;
wdenk7e6bf352004-12-12 22:06:17 +0000294#else
295 status = ps2ser_in(UART_IIR);
296#endif
wdenk1c437712004-01-16 00:30:56 +0000297 if (chr < 0) continue;
298
299 if (atomic_read(&ps2buf_cnt) < PS2BUF_SIZE) {
300 ps2buf[ps2buf_in_idx++] = chr;
301 ps2buf_in_idx &= (PS2BUF_SIZE - 1);
302 atomic_inc(&ps2buf_cnt);
303 } else {
304 printf ("ps2ser.c: buffer overflow\n");
305 }
wdenk7e6bf352004-12-12 22:06:17 +0000306#ifdef CONFIG_MPC5xxx
wdenkefe2a4d2004-12-16 21:44:03 +0000307 } while (status & PSC_SR_RXRDY);
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +0200308#elif defined(CONFIG_MPC85xx)
309 } while (status & LSR_DR);
wdenk7e6bf352004-12-12 22:06:17 +0000310#else
311 } while (status & UART_IIR_RDI);
312#endif
wdenk1c437712004-01-16 00:30:56 +0000313
314 if (atomic_read(&ps2buf_cnt)) {
315 ps2mult_callback(atomic_read(&ps2buf_cnt));
316 }
317}
318
319#endif /* CONFIG_PS2SERIAL */