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wdenk0f8c9762002-08-19 11:57:05 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
37#define CONFIG_ESTEEM192E 1 /* ...on a EST ESTEEM192E */
38
39#define CONFIG_FLASH_16BIT 1 /* Rom 16 bit data bus */
40
41#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
42#undef CONFIG_8xx_CONS_SMC2
43#undef CONFIG_8xx_CONS_NONE
44
45#define MPC8XX_FACT 10 /* Multiply by 10 */
46#define MPC8XX_XIN 4915200 /* 4.915200 MHz in - ??? - XXX */
47#define CFG_PLPRCR_MF ((MPC8XX_FACT-1) << 20)
48#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT)) /* 49,152,000 Hz */
49
50#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ /* Force it - dont measure it */
51
52#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
53
54#define CONFIG_BAUDRATE 9600
55#if 0
56#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
57#else
58#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
59#endif
60#define CONFIG_BOOTCOMMAND "bootm 40030000" /* autoboot command */
61
62#define CONFIG_BOOTARGS "root=/dev/ram rw ramdisk=8192 " \
63 "ip=100.100.100.21:100.100.100.14:100.100.100.1:255.0.0.0 "
64/*
65 * Miscellaneous configurable options
66 */
67
68#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
69#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
70
71#undef CONFIG_WATCHDOG /* watchdog disabled */
72
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050073/*
74 * BOOTP options
75 */
76#define CONFIG_BOOTP_SUBNETMASK
77#define CONFIG_BOOTP_GATEWAY
78#define CONFIG_BOOTP_HOSTNAME
79#define CONFIG_BOOTP_BOOTPATH
80#define CONFIG_BOOTP_BOOTFILESIZE
81
wdenk0f8c9762002-08-19 11:57:05 +000082
Jon Loeligerdcaa7152007-07-07 20:56:05 -050083/*
84 * Command line configuration.
85 */
86#include <config_cmd_default.h>
87
wdenk0f8c9762002-08-19 11:57:05 +000088
89#define CFG_LONGHELP /* undef to save memory */
90#define CFG_PROMPT "BOOT: " /* Monitor Command Prompt */
91#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
92#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
93#define CFG_MAXARGS 8 /* max number of command args */
94#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
95
96#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
97#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
98
99#define CFG_LOAD_ADDR 0x100000 /* default load address */
100
101#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
102
103
104#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
105
106
107/*
108 * Low Level Configuration Settings
109 * (address mappings, register initial values, etc.)
110 * You should know what you are doing if you make changes here.
111 */
112/*-----------------------------------------------------------------------
113 * Internal Memory Mapped Register
114 */
115#define CFG_IMMR 0xFF000000
116
117 /*-----------------------------------------------------------------------
118 * Definitions for initial stack pointer and data area (in DPRAM)
119 */
120#define CFG_INIT_RAM_ADDR CFG_IMMR
121#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
122#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
123#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
124#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
125
126
wdenk0f8c9762002-08-19 11:57:05 +0000127/*-----------------------------------------------------------------------
128 * Start addresses for the final memory configuration
129 * (Set up by the startup code)
130 * Please note that CFG_SDRAM_BASE _must_ start at 0
131 */
132#define CFG_SDRAM_BASE 0x00000000
133#define CFG_FLASH_BASE 0x40000000
134#ifdef DEBUG
135#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
136#else
137#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
138#endif
139#define CFG_MONITOR_BASE CFG_FLASH_BASE
140#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
141
142/*
143 * For booting Linux, the board info and command line data
144 * have to be in the first 8 MB of memory, since this is
145 * the maximum mapped by the Linux kernel during initialization.
146 */
147#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
148/*-----------------------------------------------------------------------
149 * FLASH organization
150 */
151#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
152#define CFG_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
153
154#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
155#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
156
157#define CFG_ENV_IS_IN_FLASH 1
158#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
159#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
160/*-----------------------------------------------------------------------
161 * Cache Configuration
162 */
163#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
164
165/*-----------------------------------------------------------------------
166 * SYPCR - System Protection Control 11-9
167 * SYPCR can only be written once after reset!
168 *-----------------------------------------------------------------------
169 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
170 */
171#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
172
173/*-----------------------------------------------------------------------
174 * SUMCR - SIU Module Configuration 11-6
175 *-----------------------------------------------------------------------
176 * PCMCIA config., multi-function pin tri-state
177 */
178#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) /* DBGC00 */
179
180/*-----------------------------------------------------------------------
181 * TBSCR - Time Base Status and Control 11-26
182 *-----------------------------------------------------------------------
183 * Clear Reference Interrupt Status, Timebase freezing enabled
184 */
185#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
186
187/* (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) */
188
189
190/*-----------------------------------------------------------------------
191 * PISCR - Periodic Interrupt Status and Control 11-31
192 *-----------------------------------------------------------------------
193 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
194 */
195#define CFG_PISCR (PISCR_PS | PISCR_PITF)
196
197/*-----------------------------------------------------------------------
198 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
199 *-----------------------------------------------------------------------
200 * Reset PLL lock status sticky bit, timer expired status bit and timer
201 * interrupt status bit - leave PLL multiplication factor unchanged !
202 */
203#define CFG_PLPRCR (CFG_PLPRCR_MF | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
204
205/*-----------------------------------------------------------------------
206 * SCCR - System Clock and reset Control Register 15-27
207 *-----------------------------------------------------------------------
208 * Set clock output, timebase and RTC source and divider,
209 * power management and some other internal clocks
210 */
211#define SCCR_MASK SCCR_EBDF11
212#define CFG_SCCR (SCCR_TBS | \
213 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
214 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
215 SCCR_DFALCD00)
216
217/*-----------------------------------------------------------------------
218 * PCMCIA stuff
219 *-----------------------------------------------------------------------
220 *
221 */
222#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
223#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
224#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
225#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
226#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
227#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
228#define CFG_PCMCIA_IO_ADDR (0xEC000000)
229#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
230
231#define CFG_PCMCIA_INTERRUPT SIU_LEVEL6
232
233/*-----------------------------------------------------------------------
234 *
235 *-----------------------------------------------------------------------
236 *
237 */
238/*#define CFG_DER 0x2002000F*/
239#define CFG_DER 0
240/*#define CFG_DER 0x02002000 */
241
242
243/*
244 * Init Memory Controller:
245 *
246 * BR0/1 and OR0/1 (FLASH)
247 */
248
249#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
250#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
251
252/* used to re-map FLASH both when starting from SRAM or FLASH:
253 * restrict access enough to keep SRAM working (if any)
254 * but not too much to meddle with FLASH accesses
255 */
256#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
257#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
258
259/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
260#define CFG_OR_TIMING_FLASH 0x00000160
261 /*(OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
262 OR_SCY_5_CLK | OR_EHTR) */
263
264#define CFG_OR0_REMAP 0x80000160 /*(CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)*/
265#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
266#define CFG_BR0_PRELIM ( FLASH_BASE0_PRELIM | 0x00000801 )
267
268#define CFG_OR1_REMAP CFG_OR0_REMAP
269#define CFG_OR1_PRELIM CFG_OR0_PRELIM
270#define CFG_BR1_PRELIM ( FLASH_BASE1_PRELIM | 0x00000801 )
271
272/*
273 * BR2/3 and OR2/3 (SDRAM)
274 *
275 */
276#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
277#define SDRAM_BASE3_PRELIM 0x04000000 /* SDRAM bank #1 */
278#define SDRAM_MAX_SIZE 0x02000000 /* max 32 MB per bank */
279
280/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
281#define CFG_OR_TIMING_SDRAM 0x00000A00
282
283#define CFG_OR2_PRELIM 0xFC000E00
284#define CFG_BR2_PRELIM (SDRAM_BASE2_PRELIM | 0x00000081)
285
286#define CFG_OR3_PRELIM CFG_OR2_PRELIM
287#define CFG_BR3_PRELIM (SDRAM_BASE3_PRELIM | 0x00000081)
288
289
290/*
291 * Memory Periodic Timer Prescaler
292 */
293
294/* periodic timer for refresh */
295#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
296
297/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
298#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
299#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
300
301/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
302#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
303#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
304
305/*
306 * MAMR settings for SDRAM
307 */
308
309/* 8 column SDRAM */
310#define CFG_MAMR_8COL 0x18803112
311#define CFG_MAMR_9COL 0x18803112 /* same as 8 column because its just easier to port with*/
312
313
wdenk0f8c9762002-08-19 11:57:05 +0000314/*
315 * Internal Definitions
316 *
317 * Boot Flags
318 */
319
320#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
321#define BOOTFLAG_WARM 0x02 /* Software reboot */
322
323/*
324 * Internal Definitions
325 *
326 * Boot Flags
327 */
328#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
329#define BOOTFLAG_WARM 0x02 /* Software reboot */
330
331#endif /* __CONFIG_H */