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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / bf8d2dab385b0e85bf041abb004bf484546e2059 / . / drivers / pinctrl / renesas / pfc-r8a7795.c
blob: a6ecc0cabe2beead1398f8a4451854cd0a27a659 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]2/*
3 * R8A7795 ES2.0+ processor support - PFC hardware block.
4 *
5 * Copyright (C) 2015-2016 Renesas Electronics Corporation
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]6 */
7
8#include <common.h>
9#include <dm.h>
10#include <errno.h>
11#include <dm/pinctrl.h>
12#include <linux/kernel.h>
13
14#include "sh_pfc.h"
15
16#define CFG_FLAGS (SH_PFC_PIN_CFG_DRIVE_STRENGTH | \
17 SH_PFC_PIN_CFG_PULL_UP | \
18 SH_PFC_PIN_CFG_PULL_DOWN)
19
20#define CPU_ALL_PORT(fn, sfx) \
21 PORT_GP_CFG_16(0, fn, sfx, CFG_FLAGS), \
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]22 PORT_GP_CFG_29(1, fn, sfx, CFG_FLAGS), \
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]23 PORT_GP_CFG_15(2, fn, sfx, CFG_FLAGS), \
24 PORT_GP_CFG_12(3, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
25 PORT_GP_CFG_1(3, 12, fn, sfx, CFG_FLAGS), \
26 PORT_GP_CFG_1(3, 13, fn, sfx, CFG_FLAGS), \
27 PORT_GP_CFG_1(3, 14, fn, sfx, CFG_FLAGS), \
28 PORT_GP_CFG_1(3, 15, fn, sfx, CFG_FLAGS), \
29 PORT_GP_CFG_18(4, fn, sfx, CFG_FLAGS | SH_PFC_PIN_CFG_IO_VOLTAGE), \
30 PORT_GP_CFG_26(5, fn, sfx, CFG_FLAGS), \
31 PORT_GP_CFG_32(6, fn, sfx, CFG_FLAGS), \
32 PORT_GP_CFG_4(7, fn, sfx, CFG_FLAGS)
33/*
34 * F_() : just information
35 * FM() : macro for FN_xxx / xxx_MARK
36 */
37
38/* GPSR0 */
39#define GPSR0_15 F_(D15, IP7_11_8)
40#define GPSR0_14 F_(D14, IP7_7_4)
41#define GPSR0_13 F_(D13, IP7_3_0)
42#define GPSR0_12 F_(D12, IP6_31_28)
43#define GPSR0_11 F_(D11, IP6_27_24)
44#define GPSR0_10 F_(D10, IP6_23_20)
45#define GPSR0_9 F_(D9, IP6_19_16)
46#define GPSR0_8 F_(D8, IP6_15_12)
47#define GPSR0_7 F_(D7, IP6_11_8)
48#define GPSR0_6 F_(D6, IP6_7_4)
49#define GPSR0_5 F_(D5, IP6_3_0)
50#define GPSR0_4 F_(D4, IP5_31_28)
51#define GPSR0_3 F_(D3, IP5_27_24)
52#define GPSR0_2 F_(D2, IP5_23_20)
53#define GPSR0_1 F_(D1, IP5_19_16)
54#define GPSR0_0 F_(D0, IP5_15_12)
55
56/* GPSR1 */
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]57#define GPSR1_28 FM(CLKOUT)
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]58#define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
59#define GPSR1_26 F_(WE1_N, IP5_7_4)
60#define GPSR1_25 F_(WE0_N, IP5_3_0)
61#define GPSR1_24 F_(RD_WR_N, IP4_31_28)
62#define GPSR1_23 F_(RD_N, IP4_27_24)
63#define GPSR1_22 F_(BS_N, IP4_23_20)
64#define GPSR1_21 F_(CS1_N, IP4_19_16)
65#define GPSR1_20 F_(CS0_N, IP4_15_12)
66#define GPSR1_19 F_(A19, IP4_11_8)
67#define GPSR1_18 F_(A18, IP4_7_4)
68#define GPSR1_17 F_(A17, IP4_3_0)
69#define GPSR1_16 F_(A16, IP3_31_28)
70#define GPSR1_15 F_(A15, IP3_27_24)
71#define GPSR1_14 F_(A14, IP3_23_20)
72#define GPSR1_13 F_(A13, IP3_19_16)
73#define GPSR1_12 F_(A12, IP3_15_12)
74#define GPSR1_11 F_(A11, IP3_11_8)
75#define GPSR1_10 F_(A10, IP3_7_4)
76#define GPSR1_9 F_(A9, IP3_3_0)
77#define GPSR1_8 F_(A8, IP2_31_28)
78#define GPSR1_7 F_(A7, IP2_27_24)
79#define GPSR1_6 F_(A6, IP2_23_20)
80#define GPSR1_5 F_(A5, IP2_19_16)
81#define GPSR1_4 F_(A4, IP2_15_12)
82#define GPSR1_3 F_(A3, IP2_11_8)
83#define GPSR1_2 F_(A2, IP2_7_4)
84#define GPSR1_1 F_(A1, IP2_3_0)
85#define GPSR1_0 F_(A0, IP1_31_28)
86
87/* GPSR2 */
88#define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
89#define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
90#define GPSR2_12 F_(AVB_LINK, IP0_15_12)
91#define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
92#define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
93#define GPSR2_9 F_(AVB_MDC, IP0_3_0)
94#define GPSR2_8 F_(PWM2_A, IP1_27_24)
95#define GPSR2_7 F_(PWM1_A, IP1_23_20)
96#define GPSR2_6 F_(PWM0, IP1_19_16)
97#define GPSR2_5 F_(IRQ5, IP1_15_12)
98#define GPSR2_4 F_(IRQ4, IP1_11_8)
99#define GPSR2_3 F_(IRQ3, IP1_7_4)
100#define GPSR2_2 F_(IRQ2, IP1_3_0)
101#define GPSR2_1 F_(IRQ1, IP0_31_28)
102#define GPSR2_0 F_(IRQ0, IP0_27_24)
103
104/* GPSR3 */
105#define GPSR3_15 F_(SD1_WP, IP11_23_20)
106#define GPSR3_14 F_(SD1_CD, IP11_19_16)
107#define GPSR3_13 F_(SD0_WP, IP11_15_12)
108#define GPSR3_12 F_(SD0_CD, IP11_11_8)
109#define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
110#define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
111#define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
112#define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
113#define GPSR3_7 F_(SD1_CMD, IP8_15_12)
114#define GPSR3_6 F_(SD1_CLK, IP8_11_8)
115#define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
116#define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
117#define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
118#define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
119#define GPSR3_1 F_(SD0_CMD, IP7_23_20)
120#define GPSR3_0 F_(SD0_CLK, IP7_19_16)
121
122/* GPSR4 */
123#define GPSR4_17 F_(SD3_DS, IP11_7_4)
124#define GPSR4_16 F_(SD3_DAT7, IP11_3_0)
125#define GPSR4_15 F_(SD3_DAT6, IP10_31_28)
126#define GPSR4_14 F_(SD3_DAT5, IP10_27_24)
127#define GPSR4_13 F_(SD3_DAT4, IP10_23_20)
128#define GPSR4_12 F_(SD3_DAT3, IP10_19_16)
129#define GPSR4_11 F_(SD3_DAT2, IP10_15_12)
130#define GPSR4_10 F_(SD3_DAT1, IP10_11_8)
131#define GPSR4_9 F_(SD3_DAT0, IP10_7_4)
132#define GPSR4_8 F_(SD3_CMD, IP10_3_0)
133#define GPSR4_7 F_(SD3_CLK, IP9_31_28)
134#define GPSR4_6 F_(SD2_DS, IP9_27_24)
135#define GPSR4_5 F_(SD2_DAT3, IP9_23_20)
136#define GPSR4_4 F_(SD2_DAT2, IP9_19_16)
137#define GPSR4_3 F_(SD2_DAT1, IP9_15_12)
138#define GPSR4_2 F_(SD2_DAT0, IP9_11_8)
139#define GPSR4_1 F_(SD2_CMD, IP9_7_4)
140#define GPSR4_0 F_(SD2_CLK, IP9_3_0)
141
142/* GPSR5 */
143#define GPSR5_25 F_(MLB_DAT, IP14_19_16)
144#define GPSR5_24 F_(MLB_SIG, IP14_15_12)
145#define GPSR5_23 F_(MLB_CLK, IP14_11_8)
146#define GPSR5_22 FM(MSIOF0_RXD)
147#define GPSR5_21 F_(MSIOF0_SS2, IP14_7_4)
148#define GPSR5_20 FM(MSIOF0_TXD)
149#define GPSR5_19 F_(MSIOF0_SS1, IP14_3_0)
150#define GPSR5_18 F_(MSIOF0_SYNC, IP13_31_28)
151#define GPSR5_17 FM(MSIOF0_SCK)
152#define GPSR5_16 F_(HRTS0_N, IP13_27_24)
153#define GPSR5_15 F_(HCTS0_N, IP13_23_20)
154#define GPSR5_14 F_(HTX0, IP13_19_16)
155#define GPSR5_13 F_(HRX0, IP13_15_12)
156#define GPSR5_12 F_(HSCK0, IP13_11_8)
157#define GPSR5_11 F_(RX2_A, IP13_7_4)
158#define GPSR5_10 F_(TX2_A, IP13_3_0)
159#define GPSR5_9 F_(SCK2, IP12_31_28)
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]160#define GPSR5_8 F_(RTS1_N, IP12_27_24)
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]161#define GPSR5_7 F_(CTS1_N, IP12_23_20)
162#define GPSR5_6 F_(TX1_A, IP12_19_16)
163#define GPSR5_5 F_(RX1_A, IP12_15_12)
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]164#define GPSR5_4 F_(RTS0_N, IP12_11_8)
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]165#define GPSR5_3 F_(CTS0_N, IP12_7_4)
166#define GPSR5_2 F_(TX0, IP12_3_0)
167#define GPSR5_1 F_(RX0, IP11_31_28)
168#define GPSR5_0 F_(SCK0, IP11_27_24)
169
170/* GPSR6 */
171#define GPSR6_31 F_(USB2_CH3_OVC, IP18_7_4)
172#define GPSR6_30 F_(USB2_CH3_PWEN, IP18_3_0)
173#define GPSR6_29 F_(USB30_OVC, IP17_31_28)
174#define GPSR6_28 F_(USB30_PWEN, IP17_27_24)
175#define GPSR6_27 F_(USB1_OVC, IP17_23_20)
176#define GPSR6_26 F_(USB1_PWEN, IP17_19_16)
177#define GPSR6_25 F_(USB0_OVC, IP17_15_12)
178#define GPSR6_24 F_(USB0_PWEN, IP17_11_8)
179#define GPSR6_23 F_(AUDIO_CLKB_B, IP17_7_4)
180#define GPSR6_22 F_(AUDIO_CLKA_A, IP17_3_0)
181#define GPSR6_21 F_(SSI_SDATA9_A, IP16_31_28)
182#define GPSR6_20 F_(SSI_SDATA8, IP16_27_24)
183#define GPSR6_19 F_(SSI_SDATA7, IP16_23_20)
184#define GPSR6_18 F_(SSI_WS78, IP16_19_16)
185#define GPSR6_17 F_(SSI_SCK78, IP16_15_12)
186#define GPSR6_16 F_(SSI_SDATA6, IP16_11_8)
187#define GPSR6_15 F_(SSI_WS6, IP16_7_4)
188#define GPSR6_14 F_(SSI_SCK6, IP16_3_0)
189#define GPSR6_13 FM(SSI_SDATA5)
190#define GPSR6_12 FM(SSI_WS5)
191#define GPSR6_11 FM(SSI_SCK5)
192#define GPSR6_10 F_(SSI_SDATA4, IP15_31_28)
193#define GPSR6_9 F_(SSI_WS4, IP15_27_24)
194#define GPSR6_8 F_(SSI_SCK4, IP15_23_20)
195#define GPSR6_7 F_(SSI_SDATA3, IP15_19_16)
196#define GPSR6_6 F_(SSI_WS349, IP15_15_12)
197#define GPSR6_5 F_(SSI_SCK349, IP15_11_8)
198#define GPSR6_4 F_(SSI_SDATA2_A, IP15_7_4)
199#define GPSR6_3 F_(SSI_SDATA1_A, IP15_3_0)
200#define GPSR6_2 F_(SSI_SDATA0, IP14_31_28)
201#define GPSR6_1 F_(SSI_WS01239, IP14_27_24)
202#define GPSR6_0 F_(SSI_SCK01239, IP14_23_20)
203
204/* GPSR7 */
205#define GPSR7_3 FM(HDMI1_CEC)
206#define GPSR7_2 FM(HDMI0_CEC)
207#define GPSR7_1 FM(AVS2)
208#define GPSR7_0 FM(AVS1)
209
210
211/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
212#define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213#define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214#define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215#define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216#define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) FM(FSCLKST2_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]217#define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]218#define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) FM(MSIOF3_SS2_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219#define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) FM(MSIOF3_SS1_E) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220#define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SYNC_E) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]221#define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222#define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) F_(0, 0) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) FM(MSIOF3_RXD_E) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
223#define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) F_(0, 0) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) FM(FSCLKST2_N_B) F_(0, 0) FM(MSIOF3_TXD_E) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
224#define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)F_(0, 0) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225#define IP1_23_20 FM(PWM1_A) F_(0, 0) F_(0, 0) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226#define IP1_27_24 FM(PWM2_A) F_(0, 0) F_(0, 0) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]227#define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228#define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229#define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230#define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231
232/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
233#define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234#define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235#define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236#define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237#define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238#define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]239#define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]240#define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241#define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242#define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243#define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244#define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245#define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246#define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247#define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248#define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249#define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250#define IP4_19_16 FM(CS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251#define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252#define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253#define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254#define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]255#define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]256#define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257#define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258#define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259#define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260#define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261#define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262#define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263#define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264#define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265#define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266#define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
267#define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]268#define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_C) FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]269#define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270#define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271#define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272#define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273#define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274
275/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
276#define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277#define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278#define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279#define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280#define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281#define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282#define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) FM(NFCE_N_B) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283#define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) FM(NFWP_N_B) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284#define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) FM(NFDATA14_B) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285#define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) FM(NFDATA15_B) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286#define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) FM(NFRB_N_B) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287#define IP9_3_0 FM(SD2_CLK) F_(0, 0) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288#define IP9_7_4 FM(SD2_CMD) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289#define IP9_11_8 FM(SD2_DAT0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290#define IP9_15_12 FM(SD2_DAT1) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291#define IP9_19_16 FM(SD2_DAT2) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292#define IP9_23_20 FM(SD2_DAT3) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293#define IP9_27_24 FM(SD2_DS) F_(0, 0) FM(NFALE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294#define IP9_31_28 FM(SD3_CLK) F_(0, 0) FM(NFWE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295#define IP10_3_0 FM(SD3_CMD) F_(0, 0) FM(NFRE_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296#define IP10_7_4 FM(SD3_DAT0) F_(0, 0) FM(NFDATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297#define IP10_11_8 FM(SD3_DAT1) F_(0, 0) FM(NFDATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298#define IP10_15_12 FM(SD3_DAT2) F_(0, 0) FM(NFDATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299#define IP10_19_16 FM(SD3_DAT3) F_(0, 0) FM(NFDATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300#define IP10_23_20 FM(SD3_DAT4) FM(SD2_CD_A) FM(NFDATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301#define IP10_27_24 FM(SD3_DAT5) FM(SD2_WP_A) FM(NFDATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302#define IP10_31_28 FM(SD3_DAT6) FM(SD3_CD) FM(NFDATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303#define IP11_3_0 FM(SD3_DAT7) FM(SD3_WP) FM(NFDATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304#define IP11_7_4 FM(SD3_DS) F_(0, 0) FM(NFCLE) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305#define IP11_11_8 FM(SD0_CD) F_(0, 0) FM(NFDATA14_A) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306
307/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
308#define IP11_15_12 FM(SD0_WP) F_(0, 0) FM(NFDATA15_A) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309#define IP11_19_16 FM(SD1_CD) F_(0, 0) FM(NFRB_N_A) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310#define IP11_23_20 FM(SD1_WP) F_(0, 0) FM(NFCE_N_A) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
311#define IP11_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
312#define IP11_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313#define IP12_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314#define IP12_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]315#define IP12_11_8 FM(RTS0_N) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]316#define IP12_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317#define IP12_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318#define IP12_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]319#define IP12_27_24 FM(RTS1_N) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]320#define IP12_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321#define IP13_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322#define IP13_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323#define IP13_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324#define IP13_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325#define IP13_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326#define IP13_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327#define IP13_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328#define IP13_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) FM(TX5_B) F_(0, 0) F_(0, 0) FM(BPFCLK_D) F_(0, 0) F_(0, 0)
329#define IP14_3_0 FM(MSIOF0_SS1) FM(RX5_A) FM(NFWP_N_A) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330#define IP14_7_4 FM(MSIOF0_SS2) FM(TX5_A) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331#define IP14_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332#define IP14_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333#define IP14_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334#define IP14_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335#define IP14_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336
337/* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
338#define IP14_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339#define IP15_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340#define IP15_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341#define IP15_11_8 FM(SSI_SCK349) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342#define IP15_15_12 FM(SSI_WS349) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343#define IP15_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344#define IP15_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345#define IP15_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346#define IP15_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347#define IP16_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
348#define IP16_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
349#define IP16_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
350#define IP16_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
351#define IP16_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
352#define IP16_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
353#define IP16_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
354#define IP16_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
355#define IP17_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
356#define IP17_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
357#define IP17_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HSCK2_C) F_(0, 0) F_(0, 0)
358#define IP17_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(HRX2_C) F_(0, 0) F_(0, 0)
359#define IP17_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) FM(HTX2_C) F_(0, 0) F_(0, 0)
360#define IP17_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) FM(HCTS2_N_C) F_(0, 0) F_(0, 0)
361#define IP17_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) FM(BPFCLK_C) FM(HRTS2_N_C) F_(0, 0) F_(0, 0)
362#define IP17_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_N) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
363#define IP18_3_0 FM(USB2_CH3_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) FM(FMCLK_C) FM(FMCLK_D) F_(0, 0) F_(0, 0)
364#define IP18_7_4 FM(USB2_CH3_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) FM(FMIN_C) FM(FMIN_D) F_(0, 0) F_(0, 0)
365
366#define PINMUX_GPSR \
367\
368 GPSR6_31 \
369 GPSR6_30 \
370 GPSR6_29 \
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]371 GPSR1_28 GPSR6_28 \
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]372 GPSR1_27 GPSR6_27 \
373 GPSR1_26 GPSR6_26 \
374 GPSR1_25 GPSR5_25 GPSR6_25 \
375 GPSR1_24 GPSR5_24 GPSR6_24 \
376 GPSR1_23 GPSR5_23 GPSR6_23 \
377 GPSR1_22 GPSR5_22 GPSR6_22 \
378 GPSR1_21 GPSR5_21 GPSR6_21 \
379 GPSR1_20 GPSR5_20 GPSR6_20 \
380 GPSR1_19 GPSR5_19 GPSR6_19 \
381 GPSR1_18 GPSR5_18 GPSR6_18 \
382 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
383 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
384GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
385GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
386GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
387GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
388GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
389GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
390GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
391GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
392GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
393GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
394GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
395GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
396GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
397GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
398GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
399GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
400
401#define PINMUX_IPSR \
402\
403FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
404FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
405FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
406FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
407FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
408FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
409FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
410FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
411\
412FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
413FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
414FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
415FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 \
416FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
417FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
418FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
419FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
420\
421FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
422FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
423FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
424FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
425FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
426FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
427FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
428FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
429\
430FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
431FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
432FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
433FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
434FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
435FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
436FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
437FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
438\
439FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 FM(IP18_3_0) IP18_3_0 \
440FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 FM(IP18_7_4) IP18_7_4 \
441FM(IP16_11_8) IP16_11_8 FM(IP17_11_8) IP17_11_8 \
442FM(IP16_15_12) IP16_15_12 FM(IP17_15_12) IP17_15_12 \
443FM(IP16_19_16) IP16_19_16 FM(IP17_19_16) IP17_19_16 \
444FM(IP16_23_20) IP16_23_20 FM(IP17_23_20) IP17_23_20 \
445FM(IP16_27_24) IP16_27_24 FM(IP17_27_24) IP17_27_24 \
446FM(IP16_31_28) IP16_31_28 FM(IP17_31_28) IP17_31_28
447
448/* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
449#define MOD_SEL0_31_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3) FM(SEL_MSIOF3_4) F_(0, 0) F_(0, 0) F_(0, 0)
450#define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
451#define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
452#define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
453#define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
454#define MOD_SEL0_21 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
455#define MOD_SEL0_20 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
456#define MOD_SEL0_19 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
457#define MOD_SEL0_18_17 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
458#define MOD_SEL0_16 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
459#define MOD_SEL0_14_13 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1) FM(SEL_HSCIF2_2) F_(0, 0)
460#define MOD_SEL0_12 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
461#define MOD_SEL0_11 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
462#define MOD_SEL0_10 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
463#define MOD_SEL0_9_8 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
464#define MOD_SEL0_7_6 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
465#define MOD_SEL0_5 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
466#define MOD_SEL0_4_3 FM(SEL_ADG_A_0) FM(SEL_ADG_A_1) FM(SEL_ADG_A_2) FM(SEL_ADG_A_3)
467
468/* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
469#define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
470#define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
471#define MOD_SEL1_26 FM(SEL_TIMER_TMU1_0) FM(SEL_TIMER_TMU1_1)
472#define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
473#define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]474#define MOD_SEL1_20 FM(SEL_SSI1_0) FM(SEL_SSI1_1)
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]475#define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
476#define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
477#define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
478#define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
479#define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
480#define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
481#define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
482#define MOD_SEL1_10 FM(SEL_SCIF_0) FM(SEL_SCIF_1)
483#define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
484#define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
485#define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
486#define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
487#define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
488#define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
489#define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
490#define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
491
492/* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
493#define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
494#define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
495#define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
496#define MOD_SEL2_28_27 FM(SEL_FM_0) FM(SEL_FM_1) FM(SEL_FM_2) FM(SEL_FM_3)
497#define MOD_SEL2_26 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1)
498#define MOD_SEL2_25_24_23 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
499#define MOD_SEL2_21 FM(SEL_SSI2_0) FM(SEL_SSI2_1)
500#define MOD_SEL2_20 FM(SEL_SSI9_0) FM(SEL_SSI9_1)
501#define MOD_SEL2_19 FM(SEL_TIMER_TMU2_0) FM(SEL_TIMER_TMU2_1)
502#define MOD_SEL2_18 FM(SEL_ADG_B_0) FM(SEL_ADG_B_1)
503#define MOD_SEL2_17 FM(SEL_ADG_C_0) FM(SEL_ADG_C_1)
504#define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
505
506#define PINMUX_MOD_SELS \
507\
508MOD_SEL0_31_30_29 MOD_SEL1_31_30 MOD_SEL2_31 \
509 MOD_SEL2_30 \
510 MOD_SEL1_29_28_27 MOD_SEL2_29 \
511MOD_SEL0_28_27 MOD_SEL2_28_27 \
512MOD_SEL0_26_25_24 MOD_SEL1_26 MOD_SEL2_26 \
513 MOD_SEL1_25_24 MOD_SEL2_25_24_23 \
514MOD_SEL0_23 MOD_SEL1_23_22_21 \
515MOD_SEL0_22 \
516MOD_SEL0_21 MOD_SEL2_21 \
517MOD_SEL0_20 MOD_SEL1_20 MOD_SEL2_20 \
518MOD_SEL0_19 MOD_SEL1_19 MOD_SEL2_19 \
519MOD_SEL0_18_17 MOD_SEL1_18_17 MOD_SEL2_18 \
520 MOD_SEL2_17 \
521MOD_SEL0_16 MOD_SEL1_16 \
522 MOD_SEL1_15_14 \
523MOD_SEL0_14_13 \
524 MOD_SEL1_13 \
525MOD_SEL0_12 MOD_SEL1_12 \
526MOD_SEL0_11 MOD_SEL1_11 \
527MOD_SEL0_10 MOD_SEL1_10 \
528MOD_SEL0_9_8 MOD_SEL1_9 \
529MOD_SEL0_7_6 \
530 MOD_SEL1_6 \
531MOD_SEL0_5 MOD_SEL1_5 \
532MOD_SEL0_4_3 MOD_SEL1_4 \
533 MOD_SEL1_3 \
534 MOD_SEL1_2 \
535 MOD_SEL1_1 \
536 MOD_SEL1_0 MOD_SEL2_0
537
538/*
539 * These pins are not able to be muxed but have other properties
540 * that can be set, such as drive-strength or pull-up/pull-down enable.
541 */
542#define PINMUX_STATIC \
543 FM(QSPI0_SPCLK) FM(QSPI0_SSL) FM(QSPI0_MOSI_IO0) FM(QSPI0_MISO_IO1) \
544 FM(QSPI0_IO2) FM(QSPI0_IO3) \
545 FM(QSPI1_SPCLK) FM(QSPI1_SSL) FM(QSPI1_MOSI_IO0) FM(QSPI1_MISO_IO1) \
546 FM(QSPI1_IO2) FM(QSPI1_IO3) \
547 FM(RPC_INT) FM(RPC_WP) FM(RPC_RESET) \
548 FM(AVB_TX_CTL) FM(AVB_TXC) FM(AVB_TD0) FM(AVB_TD1) FM(AVB_TD2) FM(AVB_TD3) \
549 FM(AVB_RX_CTL) FM(AVB_RXC) FM(AVB_RD0) FM(AVB_RD1) FM(AVB_RD2) FM(AVB_RD3) \
550 FM(AVB_TXCREFCLK) FM(AVB_MDIO) \
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]551 FM(PRESETOUT) \
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]552 FM(DU_DOTCLKIN0) FM(DU_DOTCLKIN1) FM(DU_DOTCLKIN2) FM(DU_DOTCLKIN3) \
553 FM(TMS) FM(TDO) FM(ASEBRK) FM(MLB_REF) FM(TDI) FM(TCK) FM(TRST) FM(EXTALR)
554
555enum {
556 PINMUX_RESERVED = 0,
557
558 PINMUX_DATA_BEGIN,
559 GP_ALL(DATA),
560 PINMUX_DATA_END,
561
562#define F_(x, y)
563#define FM(x) FN_##x,
564 PINMUX_FUNCTION_BEGIN,
565 GP_ALL(FN),
566 PINMUX_GPSR
567 PINMUX_IPSR
568 PINMUX_MOD_SELS
569 PINMUX_FUNCTION_END,
570#undef F_
571#undef FM
572
573#define F_(x, y)
574#define FM(x) x##_MARK,
575 PINMUX_MARK_BEGIN,
576 PINMUX_GPSR
577 PINMUX_IPSR
578 PINMUX_MOD_SELS
579 PINMUX_STATIC
580 PINMUX_MARK_END,
581#undef F_
582#undef FM
583};
584
585static const u16 pinmux_data[] = {
586 PINMUX_DATA_GP_ALL(),
587
588 PINMUX_SINGLE(AVS1),
589 PINMUX_SINGLE(AVS2),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]590 PINMUX_SINGLE(CLKOUT),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]591 PINMUX_SINGLE(HDMI0_CEC),
592 PINMUX_SINGLE(HDMI1_CEC),
593 PINMUX_SINGLE(I2C_SEL_0_1),
594 PINMUX_SINGLE(I2C_SEL_3_1),
595 PINMUX_SINGLE(I2C_SEL_5_1),
596 PINMUX_SINGLE(MSIOF0_RXD),
597 PINMUX_SINGLE(MSIOF0_SCK),
598 PINMUX_SINGLE(MSIOF0_TXD),
599 PINMUX_SINGLE(SSI_SCK5),
600 PINMUX_SINGLE(SSI_SDATA5),
601 PINMUX_SINGLE(SSI_WS5),
602
603 /* IPSR0 */
604 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
605 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
606
607 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
608 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
609 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
610
611 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
612 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
613 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
614
615 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
616 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
617 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
618
619 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
620 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
621 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
622 PINMUX_IPSR_GPSR(IP0_19_16, FSCLKST2_N_A),
623
624 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
625 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]626 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_A, SEL_SCIF4_0),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]627
628 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
629 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
630 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
631 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
632 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
633 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
634 PINMUX_IPSR_MSEL(IP0_27_24, MSIOF3_SS2_E, SEL_MSIOF3_4),
635
636 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
637 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
638 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
639 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
640 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
641 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
642 PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_SS1_E, SEL_MSIOF3_4),
643
644 /* IPSR1 */
645 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
646 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
647 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
648 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
649 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
650 PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_SYNC_E, SEL_MSIOF3_4),
651
652 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
653 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]654 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
655 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
656 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
657 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_E, SEL_MSIOF3_4),
658
659 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
660 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]661 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
662 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
663 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
664 PINMUX_IPSR_MSEL(IP1_11_8, MSIOF3_RXD_E, SEL_MSIOF3_4),
665
666 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
667 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]668 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
669 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
670 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
671 PINMUX_IPSR_GPSR(IP1_15_12, FSCLKST2_N_B),
672 PINMUX_IPSR_MSEL(IP1_15_12, MSIOF3_TXD_E, SEL_MSIOF3_4),
673
674 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
675 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]676 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
677 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
678
679 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]680 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
681 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
682 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
683
684 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]685 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
686 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
687
688 PINMUX_IPSR_GPSR(IP1_31_28, A0),
689 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
690 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
691 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
692 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
693 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
694
695 /* IPSR2 */
696 PINMUX_IPSR_GPSR(IP2_3_0, A1),
697 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
698 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
699 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
700 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
701 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
702
703 PINMUX_IPSR_GPSR(IP2_7_4, A2),
704 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
705 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
706 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
707 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
708 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
709
710 PINMUX_IPSR_GPSR(IP2_11_8, A3),
711 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
712 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
713 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
714 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
715 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
716
717 PINMUX_IPSR_GPSR(IP2_15_12, A4),
718 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
719 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
720 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
721 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
722 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
723
724 PINMUX_IPSR_GPSR(IP2_19_16, A5),
725 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
726 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
727 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
728 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
729 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
730 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
731
732 PINMUX_IPSR_GPSR(IP2_23_20, A6),
733 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
734 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
735 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
736 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
737 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
738 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
739
740 PINMUX_IPSR_GPSR(IP2_27_24, A7),
741 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
742 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
743 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
744 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
745 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
746 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
747
748 PINMUX_IPSR_GPSR(IP2_31_28, A8),
749 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
750 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
751 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
752 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
753 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
754 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
755
756 /* IPSR3 */
757 PINMUX_IPSR_GPSR(IP3_3_0, A9),
758 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
759 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
760 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
761
762 PINMUX_IPSR_GPSR(IP3_7_4, A10),
763 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]764 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]765 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
766
767 PINMUX_IPSR_GPSR(IP3_11_8, A11),
768 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
769 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
770 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
771 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
772 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
773 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
774 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
775 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
776
777 PINMUX_IPSR_GPSR(IP3_15_12, A12),
778 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
779 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
780 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
781 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
782 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
783
784 PINMUX_IPSR_GPSR(IP3_19_16, A13),
785 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
786 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
787 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
788 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
789 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
790
791 PINMUX_IPSR_GPSR(IP3_23_20, A14),
792 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
793 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
794 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
795 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
796 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
797
798 PINMUX_IPSR_GPSR(IP3_27_24, A15),
799 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
800 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
801 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
802 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
803 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
804
805 PINMUX_IPSR_GPSR(IP3_31_28, A16),
806 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
807 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
808 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
809
810 /* IPSR4 */
811 PINMUX_IPSR_GPSR(IP4_3_0, A17),
812 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
813 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
814 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
815
816 PINMUX_IPSR_GPSR(IP4_7_4, A18),
817 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
818 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
819 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
820
821 PINMUX_IPSR_GPSR(IP4_11_8, A19),
822 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
823 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
824 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
825
826 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
827 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
828
829 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N),
830 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
831 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
832
833 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
834 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
835 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
836 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
837 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
838 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
839 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
840 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
841
842 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
843 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
844 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
845 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
846 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
847 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
848
849 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
850 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
851 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
852 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
853 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
854 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
855
856 /* IPSR5 */
857 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
858 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
859 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
860 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
861 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
862 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
863 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
864
865 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
866 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]867 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]868 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
869 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
870 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
871 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
872 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
873
874 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
875 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
876 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
877 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
878
879 PINMUX_IPSR_GPSR(IP5_15_12, D0),
880 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
881 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
882 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
883 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
884
885 PINMUX_IPSR_GPSR(IP5_19_16, D1),
886 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
887 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
888 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
889 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
890
891 PINMUX_IPSR_GPSR(IP5_23_20, D2),
892 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
893 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
894 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
895
896 PINMUX_IPSR_GPSR(IP5_27_24, D3),
897 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
898 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
899 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
900
901 PINMUX_IPSR_GPSR(IP5_31_28, D4),
902 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
903 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
904 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
905
906 /* IPSR6 */
907 PINMUX_IPSR_GPSR(IP6_3_0, D5),
908 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
909 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
910 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
911
912 PINMUX_IPSR_GPSR(IP6_7_4, D6),
913 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
914 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
915 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
916
917 PINMUX_IPSR_GPSR(IP6_11_8, D7),
918 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
919 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
920 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
921
922 PINMUX_IPSR_GPSR(IP6_15_12, D8),
923 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
924 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
925 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
926 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
927 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
928
929 PINMUX_IPSR_GPSR(IP6_19_16, D9),
930 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
931 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
932 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
933 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
934
935 PINMUX_IPSR_GPSR(IP6_23_20, D10),
936 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
937 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
938 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
939 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
940 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
941 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
942
943 PINMUX_IPSR_GPSR(IP6_27_24, D11),
944 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
945 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
946 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
947 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]948 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_C, SEL_SCIF4_2),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]949 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
950
951 PINMUX_IPSR_GPSR(IP6_31_28, D12),
952 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
953 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
954 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
955 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
956 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
957
958 /* IPSR7 */
959 PINMUX_IPSR_GPSR(IP7_3_0, D13),
960 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
961 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
962 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
963 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
964 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
965
966 PINMUX_IPSR_GPSR(IP7_7_4, D14),
967 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
968 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
969 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
970 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
971 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
972 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
973
974 PINMUX_IPSR_GPSR(IP7_11_8, D15),
975 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
976 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
977 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
978 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
979 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
980 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
981
982 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
983 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
984 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
985
986 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
987 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
988 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
989
990 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
991 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
992 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
993 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
994
995 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
996 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
997 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
998 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
999
1000 /* IPSR8 */
1001 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
1002 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
1003 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
1004 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
1005
1006 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
1007 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
1008 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
1009 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
1010
1011 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
1012 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
1013 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
1014
1015 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
1016 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
1017 PINMUX_IPSR_GPSR(IP8_15_12, NFCE_N_B),
1018 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
1019 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
1020
1021 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
1022 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
1023 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
1024 PINMUX_IPSR_GPSR(IP8_19_16, NFWP_N_B),
1025 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
1026 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
1027
1028 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
1029 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
1030 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
1031 PINMUX_IPSR_GPSR(IP8_23_20, NFDATA14_B),
1032 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
1033 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
1034
1035 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1036 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1037 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1038 PINMUX_IPSR_GPSR(IP8_27_24, NFDATA15_B),
1039 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1040 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1041
1042 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1043 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1044 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1045 PINMUX_IPSR_GPSR(IP8_31_28, NFRB_N_B),
1046 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1047 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1048
1049 /* IPSR9 */
1050 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1051 PINMUX_IPSR_GPSR(IP9_3_0, NFDATA8),
1052
1053 PINMUX_IPSR_GPSR(IP9_7_4, SD2_CMD),
1054 PINMUX_IPSR_GPSR(IP9_7_4, NFDATA9),
1055
1056 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT0),
1057 PINMUX_IPSR_GPSR(IP9_11_8, NFDATA10),
1058
1059 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT1),
1060 PINMUX_IPSR_GPSR(IP9_15_12, NFDATA11),
1061
1062 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT2),
1063 PINMUX_IPSR_GPSR(IP9_19_16, NFDATA12),
1064
1065 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DAT3),
1066 PINMUX_IPSR_GPSR(IP9_23_20, NFDATA13),
1067
1068 PINMUX_IPSR_GPSR(IP9_27_24, SD2_DS),
1069 PINMUX_IPSR_GPSR(IP9_27_24, NFALE),
1070 PINMUX_IPSR_GPSR(IP9_27_24, SATA_DEVSLP_B),
1071
1072 PINMUX_IPSR_GPSR(IP9_31_28, SD3_CLK),
1073 PINMUX_IPSR_GPSR(IP9_31_28, NFWE_N),
1074
1075 /* IPSR10 */
1076 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CMD),
1077 PINMUX_IPSR_GPSR(IP10_3_0, NFRE_N),
1078
1079 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT0),
1080 PINMUX_IPSR_GPSR(IP10_7_4, NFDATA0),
1081
1082 PINMUX_IPSR_GPSR(IP10_11_8, SD3_DAT1),
1083 PINMUX_IPSR_GPSR(IP10_11_8, NFDATA1),
1084
1085 PINMUX_IPSR_GPSR(IP10_15_12, SD3_DAT2),
1086 PINMUX_IPSR_GPSR(IP10_15_12, NFDATA2),
1087
1088 PINMUX_IPSR_GPSR(IP10_19_16, SD3_DAT3),
1089 PINMUX_IPSR_GPSR(IP10_19_16, NFDATA3),
1090
1091 PINMUX_IPSR_GPSR(IP10_23_20, SD3_DAT4),
1092 PINMUX_IPSR_MSEL(IP10_23_20, SD2_CD_A, SEL_SDHI2_0),
1093 PINMUX_IPSR_GPSR(IP10_23_20, NFDATA4),
1094
1095 PINMUX_IPSR_GPSR(IP10_27_24, SD3_DAT5),
1096 PINMUX_IPSR_MSEL(IP10_27_24, SD2_WP_A, SEL_SDHI2_0),
1097 PINMUX_IPSR_GPSR(IP10_27_24, NFDATA5),
1098
1099 PINMUX_IPSR_GPSR(IP10_31_28, SD3_DAT6),
1100 PINMUX_IPSR_GPSR(IP10_31_28, SD3_CD),
1101 PINMUX_IPSR_GPSR(IP10_31_28, NFDATA6),
1102
1103 /* IPSR11 */
1104 PINMUX_IPSR_GPSR(IP11_3_0, SD3_DAT7),
1105 PINMUX_IPSR_GPSR(IP11_3_0, SD3_WP),
1106 PINMUX_IPSR_GPSR(IP11_3_0, NFDATA7),
1107
1108 PINMUX_IPSR_GPSR(IP11_7_4, SD3_DS),
1109 PINMUX_IPSR_GPSR(IP11_7_4, NFCLE),
1110
1111 PINMUX_IPSR_GPSR(IP11_11_8, SD0_CD),
1112 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_B, SEL_I2C2_1),
1113 PINMUX_IPSR_MSEL(IP11_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1114
1115 PINMUX_IPSR_GPSR(IP11_15_12, SD0_WP),
1116 PINMUX_IPSR_MSEL(IP11_15_12, SDA2_B, SEL_I2C2_1),
1117
1118 PINMUX_IPSR_GPSR(IP11_19_16, SD1_CD),
1119 PINMUX_IPSR_MSEL(IP11_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1120
1121 PINMUX_IPSR_GPSR(IP11_23_20, SD1_WP),
1122 PINMUX_IPSR_MSEL(IP11_23_20, SIM0_D_B, SEL_SIMCARD_1),
1123
1124 PINMUX_IPSR_GPSR(IP11_27_24, SCK0),
1125 PINMUX_IPSR_MSEL(IP11_27_24, HSCK1_B, SEL_HSCIF1_1),
1126 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1127 PINMUX_IPSR_MSEL(IP11_27_24, AUDIO_CLKC_B, SEL_ADG_C_1),
1128 PINMUX_IPSR_MSEL(IP11_27_24, SDA2_A, SEL_I2C2_0),
1129 PINMUX_IPSR_MSEL(IP11_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1130 PINMUX_IPSR_MSEL(IP11_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1131 PINMUX_IPSR_MSEL(IP11_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1132 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS2),
1133 PINMUX_IPSR_MSEL(IP11_27_24, SCK5_B, SEL_SCIF5_1),
1134
1135 PINMUX_IPSR_GPSR(IP11_31_28, RX0),
1136 PINMUX_IPSR_MSEL(IP11_31_28, HRX1_B, SEL_HSCIF1_1),
1137 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK0_C, SEL_TSIF0_2),
1138 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1139 PINMUX_IPSR_MSEL(IP11_31_28, RIF0_D0_B, SEL_DRIF0_1),
1140
1141 /* IPSR12 */
1142 PINMUX_IPSR_GPSR(IP12_3_0, TX0),
1143 PINMUX_IPSR_MSEL(IP12_3_0, HTX1_B, SEL_HSCIF1_1),
1144 PINMUX_IPSR_MSEL(IP12_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1145 PINMUX_IPSR_MSEL(IP12_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1146 PINMUX_IPSR_MSEL(IP12_3_0, RIF0_D1_B, SEL_DRIF0_1),
1147
1148 PINMUX_IPSR_GPSR(IP12_7_4, CTS0_N),
1149 PINMUX_IPSR_MSEL(IP12_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1150 PINMUX_IPSR_MSEL(IP12_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1151 PINMUX_IPSR_MSEL(IP12_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1152 PINMUX_IPSR_MSEL(IP12_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1153 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1154 PINMUX_IPSR_GPSR(IP12_7_4, AUDIO_CLKOUT_C),
1155 PINMUX_IPSR_GPSR(IP12_7_4, ADICS_SAMP),
1156
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1157 PINMUX_IPSR_GPSR(IP12_11_8, RTS0_N),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1158 PINMUX_IPSR_MSEL(IP12_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1159 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1160 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKA_B, SEL_ADG_A_1),
1161 PINMUX_IPSR_MSEL(IP12_11_8, SCL2_A, SEL_I2C2_0),
1162 PINMUX_IPSR_MSEL(IP12_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1163 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1164 PINMUX_IPSR_GPSR(IP12_11_8, ADICHS1),
1165
1166 PINMUX_IPSR_MSEL(IP12_15_12, RX1_A, SEL_SCIF1_0),
1167 PINMUX_IPSR_MSEL(IP12_15_12, HRX1_A, SEL_HSCIF1_0),
1168 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1169 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1170 PINMUX_IPSR_MSEL(IP12_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1171
1172 PINMUX_IPSR_MSEL(IP12_19_16, TX1_A, SEL_SCIF1_0),
1173 PINMUX_IPSR_MSEL(IP12_19_16, HTX1_A, SEL_HSCIF1_0),
1174 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1175 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1176 PINMUX_IPSR_MSEL(IP12_19_16, RIF1_D0_C, SEL_DRIF1_2),
1177
1178 PINMUX_IPSR_GPSR(IP12_23_20, CTS1_N),
1179 PINMUX_IPSR_MSEL(IP12_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1180 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1181 PINMUX_IPSR_MSEL(IP12_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1182 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1183 PINMUX_IPSR_MSEL(IP12_23_20, RIF1_D0_B, SEL_DRIF1_1),
1184 PINMUX_IPSR_GPSR(IP12_23_20, ADIDATA),
1185
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1186 PINMUX_IPSR_GPSR(IP12_27_24, RTS1_N),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1187 PINMUX_IPSR_MSEL(IP12_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1188 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1189 PINMUX_IPSR_MSEL(IP12_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1190 PINMUX_IPSR_MSEL(IP12_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1191 PINMUX_IPSR_MSEL(IP12_27_24, RIF1_D1_B, SEL_DRIF1_1),
1192 PINMUX_IPSR_GPSR(IP12_27_24, ADICHS0),
1193
1194 PINMUX_IPSR_GPSR(IP12_31_28, SCK2),
1195 PINMUX_IPSR_MSEL(IP12_31_28, SCIF_CLK_B, SEL_SCIF_1),
1196 PINMUX_IPSR_MSEL(IP12_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1197 PINMUX_IPSR_MSEL(IP12_31_28, TS_SCK1_C, SEL_TSIF1_2),
1198 PINMUX_IPSR_MSEL(IP12_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1199 PINMUX_IPSR_MSEL(IP12_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1200 PINMUX_IPSR_GPSR(IP12_31_28, ADICLK),
1201
1202 /* IPSR13 */
1203 PINMUX_IPSR_MSEL(IP13_3_0, TX2_A, SEL_SCIF2_0),
1204 PINMUX_IPSR_MSEL(IP13_3_0, SD2_CD_B, SEL_SDHI2_1),
1205 PINMUX_IPSR_MSEL(IP13_3_0, SCL1_A, SEL_I2C1_0),
1206 PINMUX_IPSR_MSEL(IP13_3_0, FMCLK_A, SEL_FM_0),
1207 PINMUX_IPSR_MSEL(IP13_3_0, RIF1_D1_C, SEL_DRIF1_2),
1208 PINMUX_IPSR_GPSR(IP13_3_0, FSO_CFE_0_N),
1209
1210 PINMUX_IPSR_MSEL(IP13_7_4, RX2_A, SEL_SCIF2_0),
1211 PINMUX_IPSR_MSEL(IP13_7_4, SD2_WP_B, SEL_SDHI2_1),
1212 PINMUX_IPSR_MSEL(IP13_7_4, SDA1_A, SEL_I2C1_0),
1213 PINMUX_IPSR_MSEL(IP13_7_4, FMIN_A, SEL_FM_0),
1214 PINMUX_IPSR_MSEL(IP13_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1215 PINMUX_IPSR_GPSR(IP13_7_4, FSO_CFE_1_N),
1216
1217 PINMUX_IPSR_GPSR(IP13_11_8, HSCK0),
1218 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1219 PINMUX_IPSR_MSEL(IP13_11_8, AUDIO_CLKB_A, SEL_ADG_B_0),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1220 PINMUX_IPSR_MSEL(IP13_11_8, SSI_SDATA1_B, SEL_SSI1_1),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1221 PINMUX_IPSR_MSEL(IP13_11_8, TS_SCK0_D, SEL_TSIF0_3),
1222 PINMUX_IPSR_MSEL(IP13_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1223 PINMUX_IPSR_MSEL(IP13_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1224 PINMUX_IPSR_MSEL(IP13_11_8, RX5_B, SEL_SCIF5_1),
1225
1226 PINMUX_IPSR_GPSR(IP13_15_12, HRX0),
1227 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1228 PINMUX_IPSR_MSEL(IP13_15_12, SSI_SDATA2_B, SEL_SSI2_1),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1229 PINMUX_IPSR_MSEL(IP13_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1230 PINMUX_IPSR_MSEL(IP13_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1231 PINMUX_IPSR_MSEL(IP13_15_12, RIF0_D0_C, SEL_DRIF0_2),
1232
1233 PINMUX_IPSR_GPSR(IP13_19_16, HTX0),
1234 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1235 PINMUX_IPSR_MSEL(IP13_19_16, SSI_SDATA9_B, SEL_SSI9_1),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1236 PINMUX_IPSR_MSEL(IP13_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1237 PINMUX_IPSR_MSEL(IP13_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1238 PINMUX_IPSR_MSEL(IP13_19_16, RIF0_D1_C, SEL_DRIF0_2),
1239
1240 PINMUX_IPSR_GPSR(IP13_23_20, HCTS0_N),
1241 PINMUX_IPSR_MSEL(IP13_23_20, RX2_B, SEL_SCIF2_1),
1242 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1243 PINMUX_IPSR_MSEL(IP13_23_20, SSI_SCK9_A, SEL_SSI9_0),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1244 PINMUX_IPSR_MSEL(IP13_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1245 PINMUX_IPSR_MSEL(IP13_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1246 PINMUX_IPSR_MSEL(IP13_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1247 PINMUX_IPSR_GPSR(IP13_23_20, AUDIO_CLKOUT1_A),
1248
1249 PINMUX_IPSR_GPSR(IP13_27_24, HRTS0_N),
1250 PINMUX_IPSR_MSEL(IP13_27_24, TX2_B, SEL_SCIF2_1),
1251 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1252 PINMUX_IPSR_MSEL(IP13_27_24, SSI_WS9_A, SEL_SSI9_0),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1253 PINMUX_IPSR_MSEL(IP13_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1254 PINMUX_IPSR_MSEL(IP13_27_24, BPFCLK_A, SEL_FM_0),
1255 PINMUX_IPSR_GPSR(IP13_27_24, AUDIO_CLKOUT2_A),
1256
1257 PINMUX_IPSR_GPSR(IP13_31_28, MSIOF0_SYNC),
1258 PINMUX_IPSR_GPSR(IP13_31_28, AUDIO_CLKOUT_A),
1259 PINMUX_IPSR_MSEL(IP13_31_28, TX5_B, SEL_SCIF5_1),
1260 PINMUX_IPSR_MSEL(IP13_31_28, BPFCLK_D, SEL_FM_3),
1261
1262 /* IPSR14 */
1263 PINMUX_IPSR_GPSR(IP14_3_0, MSIOF0_SS1),
1264 PINMUX_IPSR_MSEL(IP14_3_0, RX5_A, SEL_SCIF5_0),
1265 PINMUX_IPSR_GPSR(IP14_3_0, NFWP_N_A),
1266 PINMUX_IPSR_MSEL(IP14_3_0, AUDIO_CLKA_C, SEL_ADG_A_2),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1267 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SCK2_A, SEL_SSI2_0),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1268 PINMUX_IPSR_MSEL(IP14_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1269 PINMUX_IPSR_GPSR(IP14_3_0, AUDIO_CLKOUT3_A),
1270 PINMUX_IPSR_MSEL(IP14_3_0, TCLK1_B, SEL_TIMER_TMU1_1),
1271
1272 PINMUX_IPSR_GPSR(IP14_7_4, MSIOF0_SS2),
1273 PINMUX_IPSR_MSEL(IP14_7_4, TX5_A, SEL_SCIF5_0),
1274 PINMUX_IPSR_MSEL(IP14_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1275 PINMUX_IPSR_MSEL(IP14_7_4, AUDIO_CLKC_A, SEL_ADG_C_0),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1276 PINMUX_IPSR_MSEL(IP14_7_4, SSI_WS2_A, SEL_SSI2_0),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1277 PINMUX_IPSR_MSEL(IP14_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1278 PINMUX_IPSR_GPSR(IP14_7_4, AUDIO_CLKOUT_D),
1279 PINMUX_IPSR_MSEL(IP14_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1280
1281 PINMUX_IPSR_GPSR(IP14_11_8, MLB_CLK),
1282 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1283 PINMUX_IPSR_MSEL(IP14_11_8, SCL1_B, SEL_I2C1_1),
1284
1285 PINMUX_IPSR_GPSR(IP14_15_12, MLB_SIG),
1286 PINMUX_IPSR_MSEL(IP14_15_12, RX1_B, SEL_SCIF1_1),
1287 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1288 PINMUX_IPSR_MSEL(IP14_15_12, SDA1_B, SEL_I2C1_1),
1289
1290 PINMUX_IPSR_GPSR(IP14_19_16, MLB_DAT),
1291 PINMUX_IPSR_MSEL(IP14_19_16, TX1_B, SEL_SCIF1_1),
1292 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1293
1294 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK01239),
1295 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1296
1297 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS01239),
1298 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1299
1300 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA0),
1301 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1302
1303 /* IPSR15 */
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1304 PINMUX_IPSR_MSEL(IP15_3_0, SSI_SDATA1_A, SEL_SSI1_0),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1305
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1306 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SDATA2_A, SEL_SSI2_0),
1307 PINMUX_IPSR_MSEL(IP15_7_4, SSI_SCK1_B, SEL_SSI1_1),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1308
1309 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SCK349),
1310 PINMUX_IPSR_MSEL(IP15_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1311 PINMUX_IPSR_MSEL(IP15_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1312
1313 PINMUX_IPSR_GPSR(IP15_15_12, SSI_WS349),
1314 PINMUX_IPSR_MSEL(IP15_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1315 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1316 PINMUX_IPSR_MSEL(IP15_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1317
1318 PINMUX_IPSR_GPSR(IP15_19_16, SSI_SDATA3),
1319 PINMUX_IPSR_MSEL(IP15_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1320 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1321 PINMUX_IPSR_MSEL(IP15_19_16, TS_SCK0_A, SEL_TSIF0_0),
1322 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1323 PINMUX_IPSR_MSEL(IP15_19_16, RIF0_D1_A, SEL_DRIF0_0),
1324 PINMUX_IPSR_MSEL(IP15_19_16, RIF2_D0_A, SEL_DRIF2_0),
1325
1326 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SCK4),
1327 PINMUX_IPSR_MSEL(IP15_23_20, HRX2_A, SEL_HSCIF2_0),
1328 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1329 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1330 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1331 PINMUX_IPSR_MSEL(IP15_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1332 PINMUX_IPSR_MSEL(IP15_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1333
1334 PINMUX_IPSR_GPSR(IP15_27_24, SSI_WS4),
1335 PINMUX_IPSR_MSEL(IP15_27_24, HTX2_A, SEL_HSCIF2_0),
1336 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1337 PINMUX_IPSR_MSEL(IP15_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1338 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1339 PINMUX_IPSR_MSEL(IP15_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1340 PINMUX_IPSR_MSEL(IP15_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1341
1342 PINMUX_IPSR_GPSR(IP15_31_28, SSI_SDATA4),
1343 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_A, SEL_HSCIF2_0),
1344 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1345 PINMUX_IPSR_MSEL(IP15_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1346 PINMUX_IPSR_MSEL(IP15_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1347 PINMUX_IPSR_MSEL(IP15_31_28, RIF0_D0_A, SEL_DRIF0_0),
1348 PINMUX_IPSR_MSEL(IP15_31_28, RIF2_D1_A, SEL_DRIF2_0),
1349
1350 /* IPSR16 */
1351 PINMUX_IPSR_GPSR(IP16_3_0, SSI_SCK6),
1352 PINMUX_IPSR_GPSR(IP16_3_0, USB2_PWEN),
1353 PINMUX_IPSR_MSEL(IP16_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1354
1355 PINMUX_IPSR_GPSR(IP16_7_4, SSI_WS6),
1356 PINMUX_IPSR_GPSR(IP16_7_4, USB2_OVC),
1357 PINMUX_IPSR_MSEL(IP16_7_4, SIM0_D_D, SEL_SIMCARD_3),
1358
1359 PINMUX_IPSR_GPSR(IP16_11_8, SSI_SDATA6),
1360 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1361 PINMUX_IPSR_GPSR(IP16_11_8, SATA_DEVSLP_A),
1362
1363 PINMUX_IPSR_GPSR(IP16_15_12, SSI_SCK78),
1364 PINMUX_IPSR_MSEL(IP16_15_12, HRX2_B, SEL_HSCIF2_1),
1365 PINMUX_IPSR_MSEL(IP16_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1366 PINMUX_IPSR_MSEL(IP16_15_12, TS_SCK1_A, SEL_TSIF1_0),
1367 PINMUX_IPSR_MSEL(IP16_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1368 PINMUX_IPSR_MSEL(IP16_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1369 PINMUX_IPSR_MSEL(IP16_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1370
1371 PINMUX_IPSR_GPSR(IP16_19_16, SSI_WS78),
1372 PINMUX_IPSR_MSEL(IP16_19_16, HTX2_B, SEL_HSCIF2_1),
1373 PINMUX_IPSR_MSEL(IP16_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1374 PINMUX_IPSR_MSEL(IP16_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1375 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1376 PINMUX_IPSR_MSEL(IP16_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1377 PINMUX_IPSR_MSEL(IP16_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1378
1379 PINMUX_IPSR_GPSR(IP16_23_20, SSI_SDATA7),
1380 PINMUX_IPSR_MSEL(IP16_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1381 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1382 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1383 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1384 PINMUX_IPSR_MSEL(IP16_23_20, RIF1_D0_A, SEL_DRIF1_0),
1385 PINMUX_IPSR_MSEL(IP16_23_20, RIF3_D0_A, SEL_DRIF3_0),
1386 PINMUX_IPSR_MSEL(IP16_23_20, TCLK2_A, SEL_TIMER_TMU2_0),
1387
1388 PINMUX_IPSR_GPSR(IP16_27_24, SSI_SDATA8),
1389 PINMUX_IPSR_MSEL(IP16_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1390 PINMUX_IPSR_MSEL(IP16_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1391 PINMUX_IPSR_MSEL(IP16_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1392 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1393 PINMUX_IPSR_MSEL(IP16_27_24, RIF1_D1_A, SEL_DRIF1_0),
1394 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D1_A, SEL_DRIF3_0),
1395
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1396 PINMUX_IPSR_MSEL(IP16_31_28, SSI_SDATA9_A, SEL_SSI9_0),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1397 PINMUX_IPSR_MSEL(IP16_31_28, HSCK2_B, SEL_HSCIF2_1),
1398 PINMUX_IPSR_MSEL(IP16_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1399 PINMUX_IPSR_MSEL(IP16_31_28, HSCK1_A, SEL_HSCIF1_0),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1400 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS1_B, SEL_SSI1_1),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1401 PINMUX_IPSR_GPSR(IP16_31_28, SCK1),
1402 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1403 PINMUX_IPSR_MSEL(IP16_31_28, SCK5_A, SEL_SCIF5_0),
1404
1405 /* IPSR17 */
1406 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKA_A, SEL_ADG_A_0),
1407 PINMUX_IPSR_GPSR(IP17_3_0, CC5_OSCOUT),
1408
1409 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKB_B, SEL_ADG_B_1),
1410 PINMUX_IPSR_MSEL(IP17_7_4, SCIF_CLK_A, SEL_SCIF_0),
1411 PINMUX_IPSR_MSEL(IP17_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1412 PINMUX_IPSR_MSEL(IP17_7_4, REMOCON_A, SEL_REMOCON_0),
1413 PINMUX_IPSR_MSEL(IP17_7_4, TCLK1_A, SEL_TIMER_TMU1_0),
1414
1415 PINMUX_IPSR_GPSR(IP17_11_8, USB0_PWEN),
1416 PINMUX_IPSR_MSEL(IP17_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1417 PINMUX_IPSR_MSEL(IP17_11_8, TS_SCK1_D, SEL_TSIF1_3),
1418 PINMUX_IPSR_MSEL(IP17_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1419 PINMUX_IPSR_MSEL(IP17_11_8, BPFCLK_B, SEL_FM_1),
1420 PINMUX_IPSR_MSEL(IP17_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1421 PINMUX_IPSR_MSEL(IP17_11_8, HSCK2_C, SEL_HSCIF2_2),
1422
1423 PINMUX_IPSR_GPSR(IP17_15_12, USB0_OVC),
1424 PINMUX_IPSR_MSEL(IP17_15_12, SIM0_D_C, SEL_SIMCARD_2),
1425 PINMUX_IPSR_MSEL(IP17_15_12, TS_SDAT1_D, SEL_TSIF1_3),
1426 PINMUX_IPSR_MSEL(IP17_15_12, STP_ISD_1_D, SEL_SSP1_1_3),
1427 PINMUX_IPSR_MSEL(IP17_15_12, RIF3_SYNC_B, SEL_DRIF3_1),
1428 PINMUX_IPSR_MSEL(IP17_15_12, HRX2_C, SEL_HSCIF2_2),
1429
1430 PINMUX_IPSR_GPSR(IP17_19_16, USB1_PWEN),
1431 PINMUX_IPSR_MSEL(IP17_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1432 PINMUX_IPSR_MSEL(IP17_19_16, SSI_SCK1_A, SEL_SSI1_0),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1433 PINMUX_IPSR_MSEL(IP17_19_16, TS_SCK0_E, SEL_TSIF0_4),
1434 PINMUX_IPSR_MSEL(IP17_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1435 PINMUX_IPSR_MSEL(IP17_19_16, FMCLK_B, SEL_FM_1),
1436 PINMUX_IPSR_MSEL(IP17_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1437 PINMUX_IPSR_MSEL(IP17_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1438 PINMUX_IPSR_MSEL(IP17_19_16, HTX2_C, SEL_HSCIF2_2),
1439
1440 PINMUX_IPSR_GPSR(IP17_23_20, USB1_OVC),
1441 PINMUX_IPSR_MSEL(IP17_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1442 PINMUX_IPSR_MSEL(IP17_23_20, SSI_WS1_A, SEL_SSI1_0),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1443 PINMUX_IPSR_MSEL(IP17_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1444 PINMUX_IPSR_MSEL(IP17_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1445 PINMUX_IPSR_MSEL(IP17_23_20, FMIN_B, SEL_FM_1),
1446 PINMUX_IPSR_MSEL(IP17_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1447 PINMUX_IPSR_MSEL(IP17_23_20, REMOCON_B, SEL_REMOCON_1),
1448 PINMUX_IPSR_MSEL(IP17_23_20, HCTS2_N_C, SEL_HSCIF2_2),
1449
1450 PINMUX_IPSR_GPSR(IP17_27_24, USB30_PWEN),
1451 PINMUX_IPSR_GPSR(IP17_27_24, AUDIO_CLKOUT_B),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1452 PINMUX_IPSR_MSEL(IP17_27_24, SSI_SCK2_B, SEL_SSI2_1),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1453 PINMUX_IPSR_MSEL(IP17_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1454 PINMUX_IPSR_MSEL(IP17_27_24, STP_ISEN_1_D, SEL_SSP1_1_3),
1455 PINMUX_IPSR_MSEL(IP17_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1456 PINMUX_IPSR_MSEL(IP17_27_24, RIF3_D0_B, SEL_DRIF3_1),
1457 PINMUX_IPSR_MSEL(IP17_27_24, TCLK2_B, SEL_TIMER_TMU2_1),
1458 PINMUX_IPSR_GPSR(IP17_27_24, TPU0TO0),
1459 PINMUX_IPSR_MSEL(IP17_27_24, BPFCLK_C, SEL_FM_2),
1460 PINMUX_IPSR_MSEL(IP17_27_24, HRTS2_N_C, SEL_HSCIF2_2),
1461
1462 PINMUX_IPSR_GPSR(IP17_31_28, USB30_OVC),
1463 PINMUX_IPSR_GPSR(IP17_31_28, AUDIO_CLKOUT1_B),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1464 PINMUX_IPSR_MSEL(IP17_31_28, SSI_WS2_B, SEL_SSI2_1),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1465 PINMUX_IPSR_MSEL(IP17_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1466 PINMUX_IPSR_MSEL(IP17_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1467 PINMUX_IPSR_MSEL(IP17_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1468 PINMUX_IPSR_MSEL(IP17_31_28, RIF3_D1_B, SEL_DRIF3_1),
1469 PINMUX_IPSR_GPSR(IP17_31_28, FSO_TOE_N),
1470 PINMUX_IPSR_GPSR(IP17_31_28, TPU0TO1),
1471
1472 /* IPSR18 */
1473 PINMUX_IPSR_GPSR(IP18_3_0, USB2_CH3_PWEN),
1474 PINMUX_IPSR_GPSR(IP18_3_0, AUDIO_CLKOUT2_B),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1475 PINMUX_IPSR_MSEL(IP18_3_0, SSI_SCK9_B, SEL_SSI9_1),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1476 PINMUX_IPSR_MSEL(IP18_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1477 PINMUX_IPSR_MSEL(IP18_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1478 PINMUX_IPSR_MSEL(IP18_3_0, RIF2_D0_B, SEL_DRIF2_1),
1479 PINMUX_IPSR_GPSR(IP18_3_0, TPU0TO2),
1480 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_C, SEL_FM_2),
1481 PINMUX_IPSR_MSEL(IP18_3_0, FMCLK_D, SEL_FM_3),
1482
1483 PINMUX_IPSR_GPSR(IP18_7_4, USB2_CH3_OVC),
1484 PINMUX_IPSR_GPSR(IP18_7_4, AUDIO_CLKOUT3_B),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1485 PINMUX_IPSR_MSEL(IP18_7_4, SSI_WS9_B, SEL_SSI9_1),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1486 PINMUX_IPSR_MSEL(IP18_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1487 PINMUX_IPSR_MSEL(IP18_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1488 PINMUX_IPSR_MSEL(IP18_7_4, RIF2_D1_B, SEL_DRIF2_1),
1489 PINMUX_IPSR_GPSR(IP18_7_4, TPU0TO3),
1490 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_C, SEL_FM_2),
1491 PINMUX_IPSR_MSEL(IP18_7_4, FMIN_D, SEL_FM_3),
1492
1493/*
1494 * Static pins can not be muxed between different functions but
1495 * still needs a mark entry in the pinmux list. Add each static
1496 * pin to the list without an associated function. The sh-pfc
1497 * core will do the right thing and skip trying to mux then pin
1498 * while still applying configuration to it
1499 */
1500#define FM(x) PINMUX_DATA(x##_MARK, 0),
1501 PINMUX_STATIC
1502#undef FM
1503};
1504
1505/*
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1506 * R8A7795 has 8 banks with 32 GPIOs in each => 256 GPIOs.
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1507 * Physical layout rows: A - AW, cols: 1 - 39.
1508 */
1509#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1510#define PIN_NUMBER(r, c) (((r) - 'A') * 39 + (c) + 300)
1511#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1512#define PIN_NONE U16_MAX
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1513
1514static const struct sh_pfc_pin pinmux_pins[] = {
1515 PINMUX_GPIO_GP_ALL(),
1516
1517 /*
1518 * Pins not associated with a GPIO port.
1519 *
1520 * The pin positions are different between different r8a7795
1521 * packages, all that is needed for the pfc driver is a unique
1522 * number for each pin. To this end use the pin layout from
1523 * R-Car H3SiP to calculate a unique number for each pin.
1524 */
1525 SH_PFC_PIN_NAMED_CFG('A', 8, AVB_TX_CTL, CFG_FLAGS),
1526 SH_PFC_PIN_NAMED_CFG('A', 9, AVB_MDIO, CFG_FLAGS),
1527 SH_PFC_PIN_NAMED_CFG('A', 12, AVB_TXCREFCLK, CFG_FLAGS),
1528 SH_PFC_PIN_NAMED_CFG('A', 13, AVB_RD0, CFG_FLAGS),
1529 SH_PFC_PIN_NAMED_CFG('A', 14, AVB_RD2, CFG_FLAGS),
1530 SH_PFC_PIN_NAMED_CFG('A', 16, AVB_RX_CTL, CFG_FLAGS),
1531 SH_PFC_PIN_NAMED_CFG('A', 17, AVB_TD2, CFG_FLAGS),
1532 SH_PFC_PIN_NAMED_CFG('A', 18, AVB_TD0, CFG_FLAGS),
1533 SH_PFC_PIN_NAMED_CFG('A', 19, AVB_TXC, CFG_FLAGS),
1534 SH_PFC_PIN_NAMED_CFG('B', 13, AVB_RD1, CFG_FLAGS),
1535 SH_PFC_PIN_NAMED_CFG('B', 14, AVB_RD3, CFG_FLAGS),
1536 SH_PFC_PIN_NAMED_CFG('B', 17, AVB_TD3, CFG_FLAGS),
1537 SH_PFC_PIN_NAMED_CFG('B', 18, AVB_TD1, CFG_FLAGS),
1538 SH_PFC_PIN_NAMED_CFG('B', 19, AVB_RXC, CFG_FLAGS),
1539 SH_PFC_PIN_NAMED_CFG('C', 1, PRESETOUT#, CFG_FLAGS),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1540 SH_PFC_PIN_NAMED_CFG('H', 37, MLB_REF, CFG_FLAGS),
1541 SH_PFC_PIN_NAMED_CFG('V', 3, QSPI1_SPCLK, CFG_FLAGS),
1542 SH_PFC_PIN_NAMED_CFG('V', 5, QSPI1_SSL, CFG_FLAGS),
1543 SH_PFC_PIN_NAMED_CFG('V', 6, RPC_WP#, CFG_FLAGS),
1544 SH_PFC_PIN_NAMED_CFG('V', 7, RPC_RESET#, CFG_FLAGS),
1545 SH_PFC_PIN_NAMED_CFG('W', 3, QSPI0_SPCLK, CFG_FLAGS),
1546 SH_PFC_PIN_NAMED_CFG('Y', 3, QSPI0_SSL, CFG_FLAGS),
1547 SH_PFC_PIN_NAMED_CFG('Y', 6, QSPI0_IO2, CFG_FLAGS),
1548 SH_PFC_PIN_NAMED_CFG('Y', 7, RPC_INT#, CFG_FLAGS),
1549 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 4, QSPI0_MISO_IO1, CFG_FLAGS),
1550 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('B'), 6, QSPI0_IO3, CFG_FLAGS),
1551 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 3, QSPI1_IO3, CFG_FLAGS),
1552 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 5, QSPI0_MOSI_IO0, CFG_FLAGS),
1553 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('C'), 7, QSPI1_MOSI_IO0, CFG_FLAGS),
1554 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 38, FSCLKST#, CFG_FLAGS),
1555 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('D'), 39, EXTALR, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1556 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 4, QSPI1_IO2, CFG_FLAGS),
1557 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('E'), 5, QSPI1_MISO_IO1, CFG_FLAGS),
1558 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 7, DU_DOTCLKIN0, CFG_FLAGS),
1559 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('P'), 8, DU_DOTCLKIN1, CFG_FLAGS),
1560 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 7, DU_DOTCLKIN2, CFG_FLAGS),
1561 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 8, DU_DOTCLKIN3, CFG_FLAGS),
1562 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 26, TRST#, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1563 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 29, TDI, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1564 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('R'), 30, TMS, CFG_FLAGS),
1565 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 27, TCK, SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN),
1566 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 28, TDO, SH_PFC_PIN_CFG_DRIVE_STRENGTH),
1567 SH_PFC_PIN_NAMED_CFG(ROW_GROUP_A('T'), 30, ASEBRK, CFG_FLAGS),
1568};
1569
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1570/* - AUDIO CLOCK ------------------------------------------------------------ */
1571static const unsigned int audio_clk_a_a_pins[] = {
1572 /* CLK A */
1573 RCAR_GP_PIN(6, 22),
1574};
1575static const unsigned int audio_clk_a_a_mux[] = {
1576 AUDIO_CLKA_A_MARK,
1577};
1578static const unsigned int audio_clk_a_b_pins[] = {
1579 /* CLK A */
1580 RCAR_GP_PIN(5, 4),
1581};
1582static const unsigned int audio_clk_a_b_mux[] = {
1583 AUDIO_CLKA_B_MARK,
1584};
1585static const unsigned int audio_clk_a_c_pins[] = {
1586 /* CLK A */
1587 RCAR_GP_PIN(5, 19),
1588};
1589static const unsigned int audio_clk_a_c_mux[] = {
1590 AUDIO_CLKA_C_MARK,
1591};
1592static const unsigned int audio_clk_b_a_pins[] = {
1593 /* CLK B */
1594 RCAR_GP_PIN(5, 12),
1595};
1596static const unsigned int audio_clk_b_a_mux[] = {
1597 AUDIO_CLKB_A_MARK,
1598};
1599static const unsigned int audio_clk_b_b_pins[] = {
1600 /* CLK B */
1601 RCAR_GP_PIN(6, 23),
1602};
1603static const unsigned int audio_clk_b_b_mux[] = {
1604 AUDIO_CLKB_B_MARK,
1605};
1606static const unsigned int audio_clk_c_a_pins[] = {
1607 /* CLK C */
1608 RCAR_GP_PIN(5, 21),
1609};
1610static const unsigned int audio_clk_c_a_mux[] = {
1611 AUDIO_CLKC_A_MARK,
1612};
1613static const unsigned int audio_clk_c_b_pins[] = {
1614 /* CLK C */
1615 RCAR_GP_PIN(5, 0),
1616};
1617static const unsigned int audio_clk_c_b_mux[] = {
1618 AUDIO_CLKC_B_MARK,
1619};
1620static const unsigned int audio_clkout_a_pins[] = {
1621 /* CLKOUT */
1622 RCAR_GP_PIN(5, 18),
1623};
1624static const unsigned int audio_clkout_a_mux[] = {
1625 AUDIO_CLKOUT_A_MARK,
1626};
1627static const unsigned int audio_clkout_b_pins[] = {
1628 /* CLKOUT */
1629 RCAR_GP_PIN(6, 28),
1630};
1631static const unsigned int audio_clkout_b_mux[] = {
1632 AUDIO_CLKOUT_B_MARK,
1633};
1634static const unsigned int audio_clkout_c_pins[] = {
1635 /* CLKOUT */
1636 RCAR_GP_PIN(5, 3),
1637};
1638static const unsigned int audio_clkout_c_mux[] = {
1639 AUDIO_CLKOUT_C_MARK,
1640};
1641static const unsigned int audio_clkout_d_pins[] = {
1642 /* CLKOUT */
1643 RCAR_GP_PIN(5, 21),
1644};
1645static const unsigned int audio_clkout_d_mux[] = {
1646 AUDIO_CLKOUT_D_MARK,
1647};
1648static const unsigned int audio_clkout1_a_pins[] = {
1649 /* CLKOUT1 */
1650 RCAR_GP_PIN(5, 15),
1651};
1652static const unsigned int audio_clkout1_a_mux[] = {
1653 AUDIO_CLKOUT1_A_MARK,
1654};
1655static const unsigned int audio_clkout1_b_pins[] = {
1656 /* CLKOUT1 */
1657 RCAR_GP_PIN(6, 29),
1658};
1659static const unsigned int audio_clkout1_b_mux[] = {
1660 AUDIO_CLKOUT1_B_MARK,
1661};
1662static const unsigned int audio_clkout2_a_pins[] = {
1663 /* CLKOUT2 */
1664 RCAR_GP_PIN(5, 16),
1665};
1666static const unsigned int audio_clkout2_a_mux[] = {
1667 AUDIO_CLKOUT2_A_MARK,
1668};
1669static const unsigned int audio_clkout2_b_pins[] = {
1670 /* CLKOUT2 */
1671 RCAR_GP_PIN(6, 30),
1672};
1673static const unsigned int audio_clkout2_b_mux[] = {
1674 AUDIO_CLKOUT2_B_MARK,
1675};
1676static const unsigned int audio_clkout3_a_pins[] = {
1677 /* CLKOUT3 */
1678 RCAR_GP_PIN(5, 19),
1679};
1680static const unsigned int audio_clkout3_a_mux[] = {
1681 AUDIO_CLKOUT3_A_MARK,
1682};
1683static const unsigned int audio_clkout3_b_pins[] = {
1684 /* CLKOUT3 */
1685 RCAR_GP_PIN(6, 31),
1686};
1687static const unsigned int audio_clkout3_b_mux[] = {
1688 AUDIO_CLKOUT3_B_MARK,
1689};
1690
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1691/* - EtherAVB --------------------------------------------------------------- */
1692static const unsigned int avb_link_pins[] = {
1693 /* AVB_LINK */
1694 RCAR_GP_PIN(2, 12),
1695};
1696static const unsigned int avb_link_mux[] = {
1697 AVB_LINK_MARK,
1698};
1699static const unsigned int avb_magic_pins[] = {
1700 /* AVB_MAGIC_ */
1701 RCAR_GP_PIN(2, 10),
1702};
1703static const unsigned int avb_magic_mux[] = {
1704 AVB_MAGIC_MARK,
1705};
1706static const unsigned int avb_phy_int_pins[] = {
1707 /* AVB_PHY_INT */
1708 RCAR_GP_PIN(2, 11),
1709};
1710static const unsigned int avb_phy_int_mux[] = {
1711 AVB_PHY_INT_MARK,
1712};
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1713static const unsigned int avb_mdio_pins[] = {
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1714 /* AVB_MDC, AVB_MDIO */
1715 RCAR_GP_PIN(2, 9), PIN_NUMBER('A', 9),
1716};
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1717static const unsigned int avb_mdio_mux[] = {
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1718 AVB_MDC_MARK, AVB_MDIO_MARK,
1719};
1720static const unsigned int avb_mii_pins[] = {
1721 /*
1722 * AVB_TX_CTL, AVB_TXC, AVB_TD0,
1723 * AVB_TD1, AVB_TD2, AVB_TD3,
1724 * AVB_RX_CTL, AVB_RXC, AVB_RD0,
1725 * AVB_RD1, AVB_RD2, AVB_RD3,
1726 * AVB_TXCREFCLK
1727 */
1728 PIN_NUMBER('A', 8), PIN_NUMBER('A', 19), PIN_NUMBER('A', 18),
1729 PIN_NUMBER('B', 18), PIN_NUMBER('A', 17), PIN_NUMBER('B', 17),
1730 PIN_NUMBER('A', 16), PIN_NUMBER('B', 19), PIN_NUMBER('A', 13),
1731 PIN_NUMBER('B', 13), PIN_NUMBER('A', 14), PIN_NUMBER('B', 14),
1732 PIN_NUMBER('A', 12),
1733
1734};
1735static const unsigned int avb_mii_mux[] = {
1736 AVB_TX_CTL_MARK, AVB_TXC_MARK, AVB_TD0_MARK,
1737 AVB_TD1_MARK, AVB_TD2_MARK, AVB_TD3_MARK,
1738 AVB_RX_CTL_MARK, AVB_RXC_MARK, AVB_RD0_MARK,
1739 AVB_RD1_MARK, AVB_RD2_MARK, AVB_RD3_MARK,
1740 AVB_TXCREFCLK_MARK,
1741};
1742static const unsigned int avb_avtp_pps_pins[] = {
1743 /* AVB_AVTP_PPS */
1744 RCAR_GP_PIN(2, 6),
1745};
1746static const unsigned int avb_avtp_pps_mux[] = {
1747 AVB_AVTP_PPS_MARK,
1748};
1749static const unsigned int avb_avtp_match_a_pins[] = {
1750 /* AVB_AVTP_MATCH_A */
1751 RCAR_GP_PIN(2, 13),
1752};
1753static const unsigned int avb_avtp_match_a_mux[] = {
1754 AVB_AVTP_MATCH_A_MARK,
1755};
1756static const unsigned int avb_avtp_capture_a_pins[] = {
1757 /* AVB_AVTP_CAPTURE_A */
1758 RCAR_GP_PIN(2, 14),
1759};
1760static const unsigned int avb_avtp_capture_a_mux[] = {
1761 AVB_AVTP_CAPTURE_A_MARK,
1762};
1763static const unsigned int avb_avtp_match_b_pins[] = {
1764 /* AVB_AVTP_MATCH_B */
1765 RCAR_GP_PIN(1, 8),
1766};
1767static const unsigned int avb_avtp_match_b_mux[] = {
1768 AVB_AVTP_MATCH_B_MARK,
1769};
1770static const unsigned int avb_avtp_capture_b_pins[] = {
1771 /* AVB_AVTP_CAPTURE_B */
1772 RCAR_GP_PIN(1, 11),
1773};
1774static const unsigned int avb_avtp_capture_b_mux[] = {
1775 AVB_AVTP_CAPTURE_B_MARK,
1776};
1777
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]1778/* - CAN ------------------------------------------------------------------ */
1779static const unsigned int can0_data_a_pins[] = {
1780 /* TX, RX */
1781 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1782};
1783static const unsigned int can0_data_a_mux[] = {
1784 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1785};
1786static const unsigned int can0_data_b_pins[] = {
1787 /* TX, RX */
1788 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1789};
1790static const unsigned int can0_data_b_mux[] = {
1791 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1792};
1793static const unsigned int can1_data_pins[] = {
1794 /* TX, RX */
1795 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1796};
1797static const unsigned int can1_data_mux[] = {
1798 CAN1_TX_MARK, CAN1_RX_MARK,
1799};
1800
1801/* - CAN Clock -------------------------------------------------------------- */
1802static const unsigned int can_clk_pins[] = {
1803 /* CLK */
1804 RCAR_GP_PIN(1, 25),
1805};
1806static const unsigned int can_clk_mux[] = {
1807 CAN_CLK_MARK,
1808};
1809
1810/* - CAN FD --------------------------------------------------------------- */
1811static const unsigned int canfd0_data_a_pins[] = {
1812 /* TX, RX */
1813 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1814};
1815static const unsigned int canfd0_data_a_mux[] = {
1816 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1817};
1818static const unsigned int canfd0_data_b_pins[] = {
1819 /* TX, RX */
1820 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1821};
1822static const unsigned int canfd0_data_b_mux[] = {
1823 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1824};
1825static const unsigned int canfd1_data_pins[] = {
1826 /* TX, RX */
1827 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1828};
1829static const unsigned int canfd1_data_mux[] = {
1830 CANFD1_TX_MARK, CANFD1_RX_MARK,
1831};
1832
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]1833/* - DRIF0 --------------------------------------------------------------- */
1834static const unsigned int drif0_ctrl_a_pins[] = {
1835 /* CLK, SYNC */
1836 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1837};
1838static const unsigned int drif0_ctrl_a_mux[] = {
1839 RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK,
1840};
1841static const unsigned int drif0_data0_a_pins[] = {
1842 /* D0 */
1843 RCAR_GP_PIN(6, 10),
1844};
1845static const unsigned int drif0_data0_a_mux[] = {
1846 RIF0_D0_A_MARK,
1847};
1848static const unsigned int drif0_data1_a_pins[] = {
1849 /* D1 */
1850 RCAR_GP_PIN(6, 7),
1851};
1852static const unsigned int drif0_data1_a_mux[] = {
1853 RIF0_D1_A_MARK,
1854};
1855static const unsigned int drif0_ctrl_b_pins[] = {
1856 /* CLK, SYNC */
1857 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1858};
1859static const unsigned int drif0_ctrl_b_mux[] = {
1860 RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK,
1861};
1862static const unsigned int drif0_data0_b_pins[] = {
1863 /* D0 */
1864 RCAR_GP_PIN(5, 1),
1865};
1866static const unsigned int drif0_data0_b_mux[] = {
1867 RIF0_D0_B_MARK,
1868};
1869static const unsigned int drif0_data1_b_pins[] = {
1870 /* D1 */
1871 RCAR_GP_PIN(5, 2),
1872};
1873static const unsigned int drif0_data1_b_mux[] = {
1874 RIF0_D1_B_MARK,
1875};
1876static const unsigned int drif0_ctrl_c_pins[] = {
1877 /* CLK, SYNC */
1878 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15),
1879};
1880static const unsigned int drif0_ctrl_c_mux[] = {
1881 RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK,
1882};
1883static const unsigned int drif0_data0_c_pins[] = {
1884 /* D0 */
1885 RCAR_GP_PIN(5, 13),
1886};
1887static const unsigned int drif0_data0_c_mux[] = {
1888 RIF0_D0_C_MARK,
1889};
1890static const unsigned int drif0_data1_c_pins[] = {
1891 /* D1 */
1892 RCAR_GP_PIN(5, 14),
1893};
1894static const unsigned int drif0_data1_c_mux[] = {
1895 RIF0_D1_C_MARK,
1896};
1897/* - DRIF1 --------------------------------------------------------------- */
1898static const unsigned int drif1_ctrl_a_pins[] = {
1899 /* CLK, SYNC */
1900 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1901};
1902static const unsigned int drif1_ctrl_a_mux[] = {
1903 RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK,
1904};
1905static const unsigned int drif1_data0_a_pins[] = {
1906 /* D0 */
1907 RCAR_GP_PIN(6, 19),
1908};
1909static const unsigned int drif1_data0_a_mux[] = {
1910 RIF1_D0_A_MARK,
1911};
1912static const unsigned int drif1_data1_a_pins[] = {
1913 /* D1 */
1914 RCAR_GP_PIN(6, 20),
1915};
1916static const unsigned int drif1_data1_a_mux[] = {
1917 RIF1_D1_A_MARK,
1918};
1919static const unsigned int drif1_ctrl_b_pins[] = {
1920 /* CLK, SYNC */
1921 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3),
1922};
1923static const unsigned int drif1_ctrl_b_mux[] = {
1924 RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK,
1925};
1926static const unsigned int drif1_data0_b_pins[] = {
1927 /* D0 */
1928 RCAR_GP_PIN(5, 7),
1929};
1930static const unsigned int drif1_data0_b_mux[] = {
1931 RIF1_D0_B_MARK,
1932};
1933static const unsigned int drif1_data1_b_pins[] = {
1934 /* D1 */
1935 RCAR_GP_PIN(5, 8),
1936};
1937static const unsigned int drif1_data1_b_mux[] = {
1938 RIF1_D1_B_MARK,
1939};
1940static const unsigned int drif1_ctrl_c_pins[] = {
1941 /* CLK, SYNC */
1942 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11),
1943};
1944static const unsigned int drif1_ctrl_c_mux[] = {
1945 RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK,
1946};
1947static const unsigned int drif1_data0_c_pins[] = {
1948 /* D0 */
1949 RCAR_GP_PIN(5, 6),
1950};
1951static const unsigned int drif1_data0_c_mux[] = {
1952 RIF1_D0_C_MARK,
1953};
1954static const unsigned int drif1_data1_c_pins[] = {
1955 /* D1 */
1956 RCAR_GP_PIN(5, 10),
1957};
1958static const unsigned int drif1_data1_c_mux[] = {
1959 RIF1_D1_C_MARK,
1960};
1961/* - DRIF2 --------------------------------------------------------------- */
1962static const unsigned int drif2_ctrl_a_pins[] = {
1963 /* CLK, SYNC */
1964 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1965};
1966static const unsigned int drif2_ctrl_a_mux[] = {
1967 RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK,
1968};
1969static const unsigned int drif2_data0_a_pins[] = {
1970 /* D0 */
1971 RCAR_GP_PIN(6, 7),
1972};
1973static const unsigned int drif2_data0_a_mux[] = {
1974 RIF2_D0_A_MARK,
1975};
1976static const unsigned int drif2_data1_a_pins[] = {
1977 /* D1 */
1978 RCAR_GP_PIN(6, 10),
1979};
1980static const unsigned int drif2_data1_a_mux[] = {
1981 RIF2_D1_A_MARK,
1982};
1983static const unsigned int drif2_ctrl_b_pins[] = {
1984 /* CLK, SYNC */
1985 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
1986};
1987static const unsigned int drif2_ctrl_b_mux[] = {
1988 RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK,
1989};
1990static const unsigned int drif2_data0_b_pins[] = {
1991 /* D0 */
1992 RCAR_GP_PIN(6, 30),
1993};
1994static const unsigned int drif2_data0_b_mux[] = {
1995 RIF2_D0_B_MARK,
1996};
1997static const unsigned int drif2_data1_b_pins[] = {
1998 /* D1 */
1999 RCAR_GP_PIN(6, 31),
2000};
2001static const unsigned int drif2_data1_b_mux[] = {
2002 RIF2_D1_B_MARK,
2003};
2004/* - DRIF3 --------------------------------------------------------------- */
2005static const unsigned int drif3_ctrl_a_pins[] = {
2006 /* CLK, SYNC */
2007 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2008};
2009static const unsigned int drif3_ctrl_a_mux[] = {
2010 RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK,
2011};
2012static const unsigned int drif3_data0_a_pins[] = {
2013 /* D0 */
2014 RCAR_GP_PIN(6, 19),
2015};
2016static const unsigned int drif3_data0_a_mux[] = {
2017 RIF3_D0_A_MARK,
2018};
2019static const unsigned int drif3_data1_a_pins[] = {
2020 /* D1 */
2021 RCAR_GP_PIN(6, 20),
2022};
2023static const unsigned int drif3_data1_a_mux[] = {
2024 RIF3_D1_A_MARK,
2025};
2026static const unsigned int drif3_ctrl_b_pins[] = {
2027 /* CLK, SYNC */
2028 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2029};
2030static const unsigned int drif3_ctrl_b_mux[] = {
2031 RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK,
2032};
2033static const unsigned int drif3_data0_b_pins[] = {
2034 /* D0 */
2035 RCAR_GP_PIN(6, 28),
2036};
2037static const unsigned int drif3_data0_b_mux[] = {
2038 RIF3_D0_B_MARK,
2039};
2040static const unsigned int drif3_data1_b_pins[] = {
2041 /* D1 */
2042 RCAR_GP_PIN(6, 29),
2043};
2044static const unsigned int drif3_data1_b_mux[] = {
2045 RIF3_D1_B_MARK,
2046};
2047
2048/* - DU --------------------------------------------------------------------- */
2049static const unsigned int du_rgb666_pins[] = {
2050 /* R[7:2], G[7:2], B[7:2] */
2051 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2052 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2053 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2054 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2055 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2056 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2057};
2058static const unsigned int du_rgb666_mux[] = {
2059 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2060 DU_DR3_MARK, DU_DR2_MARK,
2061 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2062 DU_DG3_MARK, DU_DG2_MARK,
2063 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2064 DU_DB3_MARK, DU_DB2_MARK,
2065};
2066static const unsigned int du_rgb888_pins[] = {
2067 /* R[7:0], G[7:0], B[7:0] */
2068 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13),
2069 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2070 RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8),
2071 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2072 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
2073 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2074 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5),
2075 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
2076 RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0),
2077};
2078static const unsigned int du_rgb888_mux[] = {
2079 DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK,
2080 DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK,
2081 DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK,
2082 DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK,
2083 DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK,
2084 DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK,
2085};
2086static const unsigned int du_clk_out_0_pins[] = {
2087 /* CLKOUT */
2088 RCAR_GP_PIN(1, 27),
2089};
2090static const unsigned int du_clk_out_0_mux[] = {
2091 DU_DOTCLKOUT0_MARK
2092};
2093static const unsigned int du_clk_out_1_pins[] = {
2094 /* CLKOUT */
2095 RCAR_GP_PIN(2, 3),
2096};
2097static const unsigned int du_clk_out_1_mux[] = {
2098 DU_DOTCLKOUT1_MARK
2099};
2100static const unsigned int du_sync_pins[] = {
2101 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */
2102 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
2103};
2104static const unsigned int du_sync_mux[] = {
2105 DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK
2106};
2107static const unsigned int du_oddf_pins[] = {
2108 /* EXDISP/EXODDF/EXCDE */
2109 RCAR_GP_PIN(2, 2),
2110};
2111static const unsigned int du_oddf_mux[] = {
2112 DU_EXODDF_DU_ODDF_DISP_CDE_MARK,
2113};
2114static const unsigned int du_cde_pins[] = {
2115 /* CDE */
2116 RCAR_GP_PIN(2, 0),
2117};
2118static const unsigned int du_cde_mux[] = {
2119 DU_CDE_MARK,
2120};
2121static const unsigned int du_disp_pins[] = {
2122 /* DISP */
2123 RCAR_GP_PIN(2, 1),
2124};
2125static const unsigned int du_disp_mux[] = {
2126 DU_DISP_MARK,
2127};
2128
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]2129/* - HDMI ------------------------------------------------------------------- */
2130static const unsigned int hdmi0_cec_pins[] = {
2131 /* HDMI0_CEC */
2132 RCAR_GP_PIN(7, 2),
2133};
2134static const unsigned int hdmi0_cec_mux[] = {
2135 HDMI0_CEC_MARK,
2136};
2137static const unsigned int hdmi1_cec_pins[] = {
2138 /* HDMI1_CEC */
2139 RCAR_GP_PIN(7, 3),
2140};
2141static const unsigned int hdmi1_cec_mux[] = {
2142 HDMI1_CEC_MARK,
2143};
2144
2145/* - HSCIF0 ----------------------------------------------------------------- */
2146static const unsigned int hscif0_data_pins[] = {
2147 /* RX, TX */
2148 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
2149};
2150static const unsigned int hscif0_data_mux[] = {
2151 HRX0_MARK, HTX0_MARK,
2152};
2153static const unsigned int hscif0_clk_pins[] = {
2154 /* SCK */
2155 RCAR_GP_PIN(5, 12),
2156};
2157static const unsigned int hscif0_clk_mux[] = {
2158 HSCK0_MARK,
2159};
2160static const unsigned int hscif0_ctrl_pins[] = {
2161 /* RTS, CTS */
2162 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
2163};
2164static const unsigned int hscif0_ctrl_mux[] = {
2165 HRTS0_N_MARK, HCTS0_N_MARK,
2166};
2167/* - HSCIF1 ----------------------------------------------------------------- */
2168static const unsigned int hscif1_data_a_pins[] = {
2169 /* RX, TX */
2170 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2171};
2172static const unsigned int hscif1_data_a_mux[] = {
2173 HRX1_A_MARK, HTX1_A_MARK,
2174};
2175static const unsigned int hscif1_clk_a_pins[] = {
2176 /* SCK */
2177 RCAR_GP_PIN(6, 21),
2178};
2179static const unsigned int hscif1_clk_a_mux[] = {
2180 HSCK1_A_MARK,
2181};
2182static const unsigned int hscif1_ctrl_a_pins[] = {
2183 /* RTS, CTS */
2184 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2185};
2186static const unsigned int hscif1_ctrl_a_mux[] = {
2187 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
2188};
2189
2190static const unsigned int hscif1_data_b_pins[] = {
2191 /* RX, TX */
2192 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2193};
2194static const unsigned int hscif1_data_b_mux[] = {
2195 HRX1_B_MARK, HTX1_B_MARK,
2196};
2197static const unsigned int hscif1_clk_b_pins[] = {
2198 /* SCK */
2199 RCAR_GP_PIN(5, 0),
2200};
2201static const unsigned int hscif1_clk_b_mux[] = {
2202 HSCK1_B_MARK,
2203};
2204static const unsigned int hscif1_ctrl_b_pins[] = {
2205 /* RTS, CTS */
2206 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2207};
2208static const unsigned int hscif1_ctrl_b_mux[] = {
2209 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2210};
2211/* - HSCIF2 ----------------------------------------------------------------- */
2212static const unsigned int hscif2_data_a_pins[] = {
2213 /* RX, TX */
2214 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2215};
2216static const unsigned int hscif2_data_a_mux[] = {
2217 HRX2_A_MARK, HTX2_A_MARK,
2218};
2219static const unsigned int hscif2_clk_a_pins[] = {
2220 /* SCK */
2221 RCAR_GP_PIN(6, 10),
2222};
2223static const unsigned int hscif2_clk_a_mux[] = {
2224 HSCK2_A_MARK,
2225};
2226static const unsigned int hscif2_ctrl_a_pins[] = {
2227 /* RTS, CTS */
2228 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2229};
2230static const unsigned int hscif2_ctrl_a_mux[] = {
2231 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
2232};
2233
2234static const unsigned int hscif2_data_b_pins[] = {
2235 /* RX, TX */
2236 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
2237};
2238static const unsigned int hscif2_data_b_mux[] = {
2239 HRX2_B_MARK, HTX2_B_MARK,
2240};
2241static const unsigned int hscif2_clk_b_pins[] = {
2242 /* SCK */
2243 RCAR_GP_PIN(6, 21),
2244};
2245static const unsigned int hscif2_clk_b_mux[] = {
2246 HSCK2_B_MARK,
2247};
2248static const unsigned int hscif2_ctrl_b_pins[] = {
2249 /* RTS, CTS */
2250 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
2251};
2252static const unsigned int hscif2_ctrl_b_mux[] = {
2253 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
2254};
2255
2256static const unsigned int hscif2_data_c_pins[] = {
2257 /* RX, TX */
2258 RCAR_GP_PIN(6, 25), RCAR_GP_PIN(6, 26),
2259};
2260static const unsigned int hscif2_data_c_mux[] = {
2261 HRX2_C_MARK, HTX2_C_MARK,
2262};
2263static const unsigned int hscif2_clk_c_pins[] = {
2264 /* SCK */
2265 RCAR_GP_PIN(6, 24),
2266};
2267static const unsigned int hscif2_clk_c_mux[] = {
2268 HSCK2_C_MARK,
2269};
2270static const unsigned int hscif2_ctrl_c_pins[] = {
2271 /* RTS, CTS */
2272 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 27),
2273};
2274static const unsigned int hscif2_ctrl_c_mux[] = {
2275 HRTS2_N_C_MARK, HCTS2_N_C_MARK,
2276};
2277/* - HSCIF3 ----------------------------------------------------------------- */
2278static const unsigned int hscif3_data_a_pins[] = {
2279 /* RX, TX */
2280 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2281};
2282static const unsigned int hscif3_data_a_mux[] = {
2283 HRX3_A_MARK, HTX3_A_MARK,
2284};
2285static const unsigned int hscif3_clk_pins[] = {
2286 /* SCK */
2287 RCAR_GP_PIN(1, 22),
2288};
2289static const unsigned int hscif3_clk_mux[] = {
2290 HSCK3_MARK,
2291};
2292static const unsigned int hscif3_ctrl_pins[] = {
2293 /* RTS, CTS */
2294 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2295};
2296static const unsigned int hscif3_ctrl_mux[] = {
2297 HRTS3_N_MARK, HCTS3_N_MARK,
2298};
2299
2300static const unsigned int hscif3_data_b_pins[] = {
2301 /* RX, TX */
2302 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
2303};
2304static const unsigned int hscif3_data_b_mux[] = {
2305 HRX3_B_MARK, HTX3_B_MARK,
2306};
2307static const unsigned int hscif3_data_c_pins[] = {
2308 /* RX, TX */
2309 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2310};
2311static const unsigned int hscif3_data_c_mux[] = {
2312 HRX3_C_MARK, HTX3_C_MARK,
2313};
2314static const unsigned int hscif3_data_d_pins[] = {
2315 /* RX, TX */
2316 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2317};
2318static const unsigned int hscif3_data_d_mux[] = {
2319 HRX3_D_MARK, HTX3_D_MARK,
2320};
2321/* - HSCIF4 ----------------------------------------------------------------- */
2322static const unsigned int hscif4_data_a_pins[] = {
2323 /* RX, TX */
2324 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
2325};
2326static const unsigned int hscif4_data_a_mux[] = {
2327 HRX4_A_MARK, HTX4_A_MARK,
2328};
2329static const unsigned int hscif4_clk_pins[] = {
2330 /* SCK */
2331 RCAR_GP_PIN(1, 11),
2332};
2333static const unsigned int hscif4_clk_mux[] = {
2334 HSCK4_MARK,
2335};
2336static const unsigned int hscif4_ctrl_pins[] = {
2337 /* RTS, CTS */
2338 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
2339};
2340static const unsigned int hscif4_ctrl_mux[] = {
2341 HRTS4_N_MARK, HCTS4_N_MARK,
2342};
2343
2344static const unsigned int hscif4_data_b_pins[] = {
2345 /* RX, TX */
2346 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2347};
2348static const unsigned int hscif4_data_b_mux[] = {
2349 HRX4_B_MARK, HTX4_B_MARK,
2350};
2351
2352/* - I2C -------------------------------------------------------------------- */
2353static const unsigned int i2c1_a_pins[] = {
2354 /* SDA, SCL */
2355 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2356};
2357static const unsigned int i2c1_a_mux[] = {
2358 SDA1_A_MARK, SCL1_A_MARK,
2359};
2360static const unsigned int i2c1_b_pins[] = {
2361 /* SDA, SCL */
2362 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
2363};
2364static const unsigned int i2c1_b_mux[] = {
2365 SDA1_B_MARK, SCL1_B_MARK,
2366};
2367static const unsigned int i2c2_a_pins[] = {
2368 /* SDA, SCL */
2369 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
2370};
2371static const unsigned int i2c2_a_mux[] = {
2372 SDA2_A_MARK, SCL2_A_MARK,
2373};
2374static const unsigned int i2c2_b_pins[] = {
2375 /* SDA, SCL */
2376 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
2377};
2378static const unsigned int i2c2_b_mux[] = {
2379 SDA2_B_MARK, SCL2_B_MARK,
2380};
2381static const unsigned int i2c6_a_pins[] = {
2382 /* SDA, SCL */
2383 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2384};
2385static const unsigned int i2c6_a_mux[] = {
2386 SDA6_A_MARK, SCL6_A_MARK,
2387};
2388static const unsigned int i2c6_b_pins[] = {
2389 /* SDA, SCL */
2390 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2391};
2392static const unsigned int i2c6_b_mux[] = {
2393 SDA6_B_MARK, SCL6_B_MARK,
2394};
2395static const unsigned int i2c6_c_pins[] = {
2396 /* SDA, SCL */
2397 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
2398};
2399static const unsigned int i2c6_c_mux[] = {
2400 SDA6_C_MARK, SCL6_C_MARK,
2401};
2402
2403/* - INTC-EX ---------------------------------------------------------------- */
2404static const unsigned int intc_ex_irq0_pins[] = {
2405 /* IRQ0 */
2406 RCAR_GP_PIN(2, 0),
2407};
2408static const unsigned int intc_ex_irq0_mux[] = {
2409 IRQ0_MARK,
2410};
2411static const unsigned int intc_ex_irq1_pins[] = {
2412 /* IRQ1 */
2413 RCAR_GP_PIN(2, 1),
2414};
2415static const unsigned int intc_ex_irq1_mux[] = {
2416 IRQ1_MARK,
2417};
2418static const unsigned int intc_ex_irq2_pins[] = {
2419 /* IRQ2 */
2420 RCAR_GP_PIN(2, 2),
2421};
2422static const unsigned int intc_ex_irq2_mux[] = {
2423 IRQ2_MARK,
2424};
2425static const unsigned int intc_ex_irq3_pins[] = {
2426 /* IRQ3 */
2427 RCAR_GP_PIN(2, 3),
2428};
2429static const unsigned int intc_ex_irq3_mux[] = {
2430 IRQ3_MARK,
2431};
2432static const unsigned int intc_ex_irq4_pins[] = {
2433 /* IRQ4 */
2434 RCAR_GP_PIN(2, 4),
2435};
2436static const unsigned int intc_ex_irq4_mux[] = {
2437 IRQ4_MARK,
2438};
2439static const unsigned int intc_ex_irq5_pins[] = {
2440 /* IRQ5 */
2441 RCAR_GP_PIN(2, 5),
2442};
2443static const unsigned int intc_ex_irq5_mux[] = {
2444 IRQ5_MARK,
2445};
2446
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]2447/* - MSIOF0 ----------------------------------------------------------------- */
2448static const unsigned int msiof0_clk_pins[] = {
2449 /* SCK */
2450 RCAR_GP_PIN(5, 17),
2451};
2452static const unsigned int msiof0_clk_mux[] = {
2453 MSIOF0_SCK_MARK,
2454};
2455static const unsigned int msiof0_sync_pins[] = {
2456 /* SYNC */
2457 RCAR_GP_PIN(5, 18),
2458};
2459static const unsigned int msiof0_sync_mux[] = {
2460 MSIOF0_SYNC_MARK,
2461};
2462static const unsigned int msiof0_ss1_pins[] = {
2463 /* SS1 */
2464 RCAR_GP_PIN(5, 19),
2465};
2466static const unsigned int msiof0_ss1_mux[] = {
2467 MSIOF0_SS1_MARK,
2468};
2469static const unsigned int msiof0_ss2_pins[] = {
2470 /* SS2 */
2471 RCAR_GP_PIN(5, 21),
2472};
2473static const unsigned int msiof0_ss2_mux[] = {
2474 MSIOF0_SS2_MARK,
2475};
2476static const unsigned int msiof0_txd_pins[] = {
2477 /* TXD */
2478 RCAR_GP_PIN(5, 20),
2479};
2480static const unsigned int msiof0_txd_mux[] = {
2481 MSIOF0_TXD_MARK,
2482};
2483static const unsigned int msiof0_rxd_pins[] = {
2484 /* RXD */
2485 RCAR_GP_PIN(5, 22),
2486};
2487static const unsigned int msiof0_rxd_mux[] = {
2488 MSIOF0_RXD_MARK,
2489};
2490/* - MSIOF1 ----------------------------------------------------------------- */
2491static const unsigned int msiof1_clk_a_pins[] = {
2492 /* SCK */
2493 RCAR_GP_PIN(6, 8),
2494};
2495static const unsigned int msiof1_clk_a_mux[] = {
2496 MSIOF1_SCK_A_MARK,
2497};
2498static const unsigned int msiof1_sync_a_pins[] = {
2499 /* SYNC */
2500 RCAR_GP_PIN(6, 9),
2501};
2502static const unsigned int msiof1_sync_a_mux[] = {
2503 MSIOF1_SYNC_A_MARK,
2504};
2505static const unsigned int msiof1_ss1_a_pins[] = {
2506 /* SS1 */
2507 RCAR_GP_PIN(6, 5),
2508};
2509static const unsigned int msiof1_ss1_a_mux[] = {
2510 MSIOF1_SS1_A_MARK,
2511};
2512static const unsigned int msiof1_ss2_a_pins[] = {
2513 /* SS2 */
2514 RCAR_GP_PIN(6, 6),
2515};
2516static const unsigned int msiof1_ss2_a_mux[] = {
2517 MSIOF1_SS2_A_MARK,
2518};
2519static const unsigned int msiof1_txd_a_pins[] = {
2520 /* TXD */
2521 RCAR_GP_PIN(6, 7),
2522};
2523static const unsigned int msiof1_txd_a_mux[] = {
2524 MSIOF1_TXD_A_MARK,
2525};
2526static const unsigned int msiof1_rxd_a_pins[] = {
2527 /* RXD */
2528 RCAR_GP_PIN(6, 10),
2529};
2530static const unsigned int msiof1_rxd_a_mux[] = {
2531 MSIOF1_RXD_A_MARK,
2532};
2533static const unsigned int msiof1_clk_b_pins[] = {
2534 /* SCK */
2535 RCAR_GP_PIN(5, 9),
2536};
2537static const unsigned int msiof1_clk_b_mux[] = {
2538 MSIOF1_SCK_B_MARK,
2539};
2540static const unsigned int msiof1_sync_b_pins[] = {
2541 /* SYNC */
2542 RCAR_GP_PIN(5, 3),
2543};
2544static const unsigned int msiof1_sync_b_mux[] = {
2545 MSIOF1_SYNC_B_MARK,
2546};
2547static const unsigned int msiof1_ss1_b_pins[] = {
2548 /* SS1 */
2549 RCAR_GP_PIN(5, 4),
2550};
2551static const unsigned int msiof1_ss1_b_mux[] = {
2552 MSIOF1_SS1_B_MARK,
2553};
2554static const unsigned int msiof1_ss2_b_pins[] = {
2555 /* SS2 */
2556 RCAR_GP_PIN(5, 0),
2557};
2558static const unsigned int msiof1_ss2_b_mux[] = {
2559 MSIOF1_SS2_B_MARK,
2560};
2561static const unsigned int msiof1_txd_b_pins[] = {
2562 /* TXD */
2563 RCAR_GP_PIN(5, 8),
2564};
2565static const unsigned int msiof1_txd_b_mux[] = {
2566 MSIOF1_TXD_B_MARK,
2567};
2568static const unsigned int msiof1_rxd_b_pins[] = {
2569 /* RXD */
2570 RCAR_GP_PIN(5, 7),
2571};
2572static const unsigned int msiof1_rxd_b_mux[] = {
2573 MSIOF1_RXD_B_MARK,
2574};
2575static const unsigned int msiof1_clk_c_pins[] = {
2576 /* SCK */
2577 RCAR_GP_PIN(6, 17),
2578};
2579static const unsigned int msiof1_clk_c_mux[] = {
2580 MSIOF1_SCK_C_MARK,
2581};
2582static const unsigned int msiof1_sync_c_pins[] = {
2583 /* SYNC */
2584 RCAR_GP_PIN(6, 18),
2585};
2586static const unsigned int msiof1_sync_c_mux[] = {
2587 MSIOF1_SYNC_C_MARK,
2588};
2589static const unsigned int msiof1_ss1_c_pins[] = {
2590 /* SS1 */
2591 RCAR_GP_PIN(6, 21),
2592};
2593static const unsigned int msiof1_ss1_c_mux[] = {
2594 MSIOF1_SS1_C_MARK,
2595};
2596static const unsigned int msiof1_ss2_c_pins[] = {
2597 /* SS2 */
2598 RCAR_GP_PIN(6, 27),
2599};
2600static const unsigned int msiof1_ss2_c_mux[] = {
2601 MSIOF1_SS2_C_MARK,
2602};
2603static const unsigned int msiof1_txd_c_pins[] = {
2604 /* TXD */
2605 RCAR_GP_PIN(6, 20),
2606};
2607static const unsigned int msiof1_txd_c_mux[] = {
2608 MSIOF1_TXD_C_MARK,
2609};
2610static const unsigned int msiof1_rxd_c_pins[] = {
2611 /* RXD */
2612 RCAR_GP_PIN(6, 19),
2613};
2614static const unsigned int msiof1_rxd_c_mux[] = {
2615 MSIOF1_RXD_C_MARK,
2616};
2617static const unsigned int msiof1_clk_d_pins[] = {
2618 /* SCK */
2619 RCAR_GP_PIN(5, 12),
2620};
2621static const unsigned int msiof1_clk_d_mux[] = {
2622 MSIOF1_SCK_D_MARK,
2623};
2624static const unsigned int msiof1_sync_d_pins[] = {
2625 /* SYNC */
2626 RCAR_GP_PIN(5, 15),
2627};
2628static const unsigned int msiof1_sync_d_mux[] = {
2629 MSIOF1_SYNC_D_MARK,
2630};
2631static const unsigned int msiof1_ss1_d_pins[] = {
2632 /* SS1 */
2633 RCAR_GP_PIN(5, 16),
2634};
2635static const unsigned int msiof1_ss1_d_mux[] = {
2636 MSIOF1_SS1_D_MARK,
2637};
2638static const unsigned int msiof1_ss2_d_pins[] = {
2639 /* SS2 */
2640 RCAR_GP_PIN(5, 21),
2641};
2642static const unsigned int msiof1_ss2_d_mux[] = {
2643 MSIOF1_SS2_D_MARK,
2644};
2645static const unsigned int msiof1_txd_d_pins[] = {
2646 /* TXD */
2647 RCAR_GP_PIN(5, 14),
2648};
2649static const unsigned int msiof1_txd_d_mux[] = {
2650 MSIOF1_TXD_D_MARK,
2651};
2652static const unsigned int msiof1_rxd_d_pins[] = {
2653 /* RXD */
2654 RCAR_GP_PIN(5, 13),
2655};
2656static const unsigned int msiof1_rxd_d_mux[] = {
2657 MSIOF1_RXD_D_MARK,
2658};
2659static const unsigned int msiof1_clk_e_pins[] = {
2660 /* SCK */
2661 RCAR_GP_PIN(3, 0),
2662};
2663static const unsigned int msiof1_clk_e_mux[] = {
2664 MSIOF1_SCK_E_MARK,
2665};
2666static const unsigned int msiof1_sync_e_pins[] = {
2667 /* SYNC */
2668 RCAR_GP_PIN(3, 1),
2669};
2670static const unsigned int msiof1_sync_e_mux[] = {
2671 MSIOF1_SYNC_E_MARK,
2672};
2673static const unsigned int msiof1_ss1_e_pins[] = {
2674 /* SS1 */
2675 RCAR_GP_PIN(3, 4),
2676};
2677static const unsigned int msiof1_ss1_e_mux[] = {
2678 MSIOF1_SS1_E_MARK,
2679};
2680static const unsigned int msiof1_ss2_e_pins[] = {
2681 /* SS2 */
2682 RCAR_GP_PIN(3, 5),
2683};
2684static const unsigned int msiof1_ss2_e_mux[] = {
2685 MSIOF1_SS2_E_MARK,
2686};
2687static const unsigned int msiof1_txd_e_pins[] = {
2688 /* TXD */
2689 RCAR_GP_PIN(3, 3),
2690};
2691static const unsigned int msiof1_txd_e_mux[] = {
2692 MSIOF1_TXD_E_MARK,
2693};
2694static const unsigned int msiof1_rxd_e_pins[] = {
2695 /* RXD */
2696 RCAR_GP_PIN(3, 2),
2697};
2698static const unsigned int msiof1_rxd_e_mux[] = {
2699 MSIOF1_RXD_E_MARK,
2700};
2701static const unsigned int msiof1_clk_f_pins[] = {
2702 /* SCK */
2703 RCAR_GP_PIN(5, 23),
2704};
2705static const unsigned int msiof1_clk_f_mux[] = {
2706 MSIOF1_SCK_F_MARK,
2707};
2708static const unsigned int msiof1_sync_f_pins[] = {
2709 /* SYNC */
2710 RCAR_GP_PIN(5, 24),
2711};
2712static const unsigned int msiof1_sync_f_mux[] = {
2713 MSIOF1_SYNC_F_MARK,
2714};
2715static const unsigned int msiof1_ss1_f_pins[] = {
2716 /* SS1 */
2717 RCAR_GP_PIN(6, 1),
2718};
2719static const unsigned int msiof1_ss1_f_mux[] = {
2720 MSIOF1_SS1_F_MARK,
2721};
2722static const unsigned int msiof1_ss2_f_pins[] = {
2723 /* SS2 */
2724 RCAR_GP_PIN(6, 2),
2725};
2726static const unsigned int msiof1_ss2_f_mux[] = {
2727 MSIOF1_SS2_F_MARK,
2728};
2729static const unsigned int msiof1_txd_f_pins[] = {
2730 /* TXD */
2731 RCAR_GP_PIN(6, 0),
2732};
2733static const unsigned int msiof1_txd_f_mux[] = {
2734 MSIOF1_TXD_F_MARK,
2735};
2736static const unsigned int msiof1_rxd_f_pins[] = {
2737 /* RXD */
2738 RCAR_GP_PIN(5, 25),
2739};
2740static const unsigned int msiof1_rxd_f_mux[] = {
2741 MSIOF1_RXD_F_MARK,
2742};
2743static const unsigned int msiof1_clk_g_pins[] = {
2744 /* SCK */
2745 RCAR_GP_PIN(3, 6),
2746};
2747static const unsigned int msiof1_clk_g_mux[] = {
2748 MSIOF1_SCK_G_MARK,
2749};
2750static const unsigned int msiof1_sync_g_pins[] = {
2751 /* SYNC */
2752 RCAR_GP_PIN(3, 7),
2753};
2754static const unsigned int msiof1_sync_g_mux[] = {
2755 MSIOF1_SYNC_G_MARK,
2756};
2757static const unsigned int msiof1_ss1_g_pins[] = {
2758 /* SS1 */
2759 RCAR_GP_PIN(3, 10),
2760};
2761static const unsigned int msiof1_ss1_g_mux[] = {
2762 MSIOF1_SS1_G_MARK,
2763};
2764static const unsigned int msiof1_ss2_g_pins[] = {
2765 /* SS2 */
2766 RCAR_GP_PIN(3, 11),
2767};
2768static const unsigned int msiof1_ss2_g_mux[] = {
2769 MSIOF1_SS2_G_MARK,
2770};
2771static const unsigned int msiof1_txd_g_pins[] = {
2772 /* TXD */
2773 RCAR_GP_PIN(3, 9),
2774};
2775static const unsigned int msiof1_txd_g_mux[] = {
2776 MSIOF1_TXD_G_MARK,
2777};
2778static const unsigned int msiof1_rxd_g_pins[] = {
2779 /* RXD */
2780 RCAR_GP_PIN(3, 8),
2781};
2782static const unsigned int msiof1_rxd_g_mux[] = {
2783 MSIOF1_RXD_G_MARK,
2784};
2785/* - MSIOF2 ----------------------------------------------------------------- */
2786static const unsigned int msiof2_clk_a_pins[] = {
2787 /* SCK */
2788 RCAR_GP_PIN(1, 9),
2789};
2790static const unsigned int msiof2_clk_a_mux[] = {
2791 MSIOF2_SCK_A_MARK,
2792};
2793static const unsigned int msiof2_sync_a_pins[] = {
2794 /* SYNC */
2795 RCAR_GP_PIN(1, 8),
2796};
2797static const unsigned int msiof2_sync_a_mux[] = {
2798 MSIOF2_SYNC_A_MARK,
2799};
2800static const unsigned int msiof2_ss1_a_pins[] = {
2801 /* SS1 */
2802 RCAR_GP_PIN(1, 6),
2803};
2804static const unsigned int msiof2_ss1_a_mux[] = {
2805 MSIOF2_SS1_A_MARK,
2806};
2807static const unsigned int msiof2_ss2_a_pins[] = {
2808 /* SS2 */
2809 RCAR_GP_PIN(1, 7),
2810};
2811static const unsigned int msiof2_ss2_a_mux[] = {
2812 MSIOF2_SS2_A_MARK,
2813};
2814static const unsigned int msiof2_txd_a_pins[] = {
2815 /* TXD */
2816 RCAR_GP_PIN(1, 11),
2817};
2818static const unsigned int msiof2_txd_a_mux[] = {
2819 MSIOF2_TXD_A_MARK,
2820};
2821static const unsigned int msiof2_rxd_a_pins[] = {
2822 /* RXD */
2823 RCAR_GP_PIN(1, 10),
2824};
2825static const unsigned int msiof2_rxd_a_mux[] = {
2826 MSIOF2_RXD_A_MARK,
2827};
2828static const unsigned int msiof2_clk_b_pins[] = {
2829 /* SCK */
2830 RCAR_GP_PIN(0, 4),
2831};
2832static const unsigned int msiof2_clk_b_mux[] = {
2833 MSIOF2_SCK_B_MARK,
2834};
2835static const unsigned int msiof2_sync_b_pins[] = {
2836 /* SYNC */
2837 RCAR_GP_PIN(0, 5),
2838};
2839static const unsigned int msiof2_sync_b_mux[] = {
2840 MSIOF2_SYNC_B_MARK,
2841};
2842static const unsigned int msiof2_ss1_b_pins[] = {
2843 /* SS1 */
2844 RCAR_GP_PIN(0, 0),
2845};
2846static const unsigned int msiof2_ss1_b_mux[] = {
2847 MSIOF2_SS1_B_MARK,
2848};
2849static const unsigned int msiof2_ss2_b_pins[] = {
2850 /* SS2 */
2851 RCAR_GP_PIN(0, 1),
2852};
2853static const unsigned int msiof2_ss2_b_mux[] = {
2854 MSIOF2_SS2_B_MARK,
2855};
2856static const unsigned int msiof2_txd_b_pins[] = {
2857 /* TXD */
2858 RCAR_GP_PIN(0, 7),
2859};
2860static const unsigned int msiof2_txd_b_mux[] = {
2861 MSIOF2_TXD_B_MARK,
2862};
2863static const unsigned int msiof2_rxd_b_pins[] = {
2864 /* RXD */
2865 RCAR_GP_PIN(0, 6),
2866};
2867static const unsigned int msiof2_rxd_b_mux[] = {
2868 MSIOF2_RXD_B_MARK,
2869};
2870static const unsigned int msiof2_clk_c_pins[] = {
2871 /* SCK */
2872 RCAR_GP_PIN(2, 12),
2873};
2874static const unsigned int msiof2_clk_c_mux[] = {
2875 MSIOF2_SCK_C_MARK,
2876};
2877static const unsigned int msiof2_sync_c_pins[] = {
2878 /* SYNC */
2879 RCAR_GP_PIN(2, 11),
2880};
2881static const unsigned int msiof2_sync_c_mux[] = {
2882 MSIOF2_SYNC_C_MARK,
2883};
2884static const unsigned int msiof2_ss1_c_pins[] = {
2885 /* SS1 */
2886 RCAR_GP_PIN(2, 10),
2887};
2888static const unsigned int msiof2_ss1_c_mux[] = {
2889 MSIOF2_SS1_C_MARK,
2890};
2891static const unsigned int msiof2_ss2_c_pins[] = {
2892 /* SS2 */
2893 RCAR_GP_PIN(2, 9),
2894};
2895static const unsigned int msiof2_ss2_c_mux[] = {
2896 MSIOF2_SS2_C_MARK,
2897};
2898static const unsigned int msiof2_txd_c_pins[] = {
2899 /* TXD */
2900 RCAR_GP_PIN(2, 14),
2901};
2902static const unsigned int msiof2_txd_c_mux[] = {
2903 MSIOF2_TXD_C_MARK,
2904};
2905static const unsigned int msiof2_rxd_c_pins[] = {
2906 /* RXD */
2907 RCAR_GP_PIN(2, 13),
2908};
2909static const unsigned int msiof2_rxd_c_mux[] = {
2910 MSIOF2_RXD_C_MARK,
2911};
2912static const unsigned int msiof2_clk_d_pins[] = {
2913 /* SCK */
2914 RCAR_GP_PIN(0, 8),
2915};
2916static const unsigned int msiof2_clk_d_mux[] = {
2917 MSIOF2_SCK_D_MARK,
2918};
2919static const unsigned int msiof2_sync_d_pins[] = {
2920 /* SYNC */
2921 RCAR_GP_PIN(0, 9),
2922};
2923static const unsigned int msiof2_sync_d_mux[] = {
2924 MSIOF2_SYNC_D_MARK,
2925};
2926static const unsigned int msiof2_ss1_d_pins[] = {
2927 /* SS1 */
2928 RCAR_GP_PIN(0, 12),
2929};
2930static const unsigned int msiof2_ss1_d_mux[] = {
2931 MSIOF2_SS1_D_MARK,
2932};
2933static const unsigned int msiof2_ss2_d_pins[] = {
2934 /* SS2 */
2935 RCAR_GP_PIN(0, 13),
2936};
2937static const unsigned int msiof2_ss2_d_mux[] = {
2938 MSIOF2_SS2_D_MARK,
2939};
2940static const unsigned int msiof2_txd_d_pins[] = {
2941 /* TXD */
2942 RCAR_GP_PIN(0, 11),
2943};
2944static const unsigned int msiof2_txd_d_mux[] = {
2945 MSIOF2_TXD_D_MARK,
2946};
2947static const unsigned int msiof2_rxd_d_pins[] = {
2948 /* RXD */
2949 RCAR_GP_PIN(0, 10),
2950};
2951static const unsigned int msiof2_rxd_d_mux[] = {
2952 MSIOF2_RXD_D_MARK,
2953};
2954/* - MSIOF3 ----------------------------------------------------------------- */
2955static const unsigned int msiof3_clk_a_pins[] = {
2956 /* SCK */
2957 RCAR_GP_PIN(0, 0),
2958};
2959static const unsigned int msiof3_clk_a_mux[] = {
2960 MSIOF3_SCK_A_MARK,
2961};
2962static const unsigned int msiof3_sync_a_pins[] = {
2963 /* SYNC */
2964 RCAR_GP_PIN(0, 1),
2965};
2966static const unsigned int msiof3_sync_a_mux[] = {
2967 MSIOF3_SYNC_A_MARK,
2968};
2969static const unsigned int msiof3_ss1_a_pins[] = {
2970 /* SS1 */
2971 RCAR_GP_PIN(0, 14),
2972};
2973static const unsigned int msiof3_ss1_a_mux[] = {
2974 MSIOF3_SS1_A_MARK,
2975};
2976static const unsigned int msiof3_ss2_a_pins[] = {
2977 /* SS2 */
2978 RCAR_GP_PIN(0, 15),
2979};
2980static const unsigned int msiof3_ss2_a_mux[] = {
2981 MSIOF3_SS2_A_MARK,
2982};
2983static const unsigned int msiof3_txd_a_pins[] = {
2984 /* TXD */
2985 RCAR_GP_PIN(0, 3),
2986};
2987static const unsigned int msiof3_txd_a_mux[] = {
2988 MSIOF3_TXD_A_MARK,
2989};
2990static const unsigned int msiof3_rxd_a_pins[] = {
2991 /* RXD */
2992 RCAR_GP_PIN(0, 2),
2993};
2994static const unsigned int msiof3_rxd_a_mux[] = {
2995 MSIOF3_RXD_A_MARK,
2996};
2997static const unsigned int msiof3_clk_b_pins[] = {
2998 /* SCK */
2999 RCAR_GP_PIN(1, 2),
3000};
3001static const unsigned int msiof3_clk_b_mux[] = {
3002 MSIOF3_SCK_B_MARK,
3003};
3004static const unsigned int msiof3_sync_b_pins[] = {
3005 /* SYNC */
3006 RCAR_GP_PIN(1, 0),
3007};
3008static const unsigned int msiof3_sync_b_mux[] = {
3009 MSIOF3_SYNC_B_MARK,
3010};
3011static const unsigned int msiof3_ss1_b_pins[] = {
3012 /* SS1 */
3013 RCAR_GP_PIN(1, 4),
3014};
3015static const unsigned int msiof3_ss1_b_mux[] = {
3016 MSIOF3_SS1_B_MARK,
3017};
3018static const unsigned int msiof3_ss2_b_pins[] = {
3019 /* SS2 */
3020 RCAR_GP_PIN(1, 5),
3021};
3022static const unsigned int msiof3_ss2_b_mux[] = {
3023 MSIOF3_SS2_B_MARK,
3024};
3025static const unsigned int msiof3_txd_b_pins[] = {
3026 /* TXD */
3027 RCAR_GP_PIN(1, 1),
3028};
3029static const unsigned int msiof3_txd_b_mux[] = {
3030 MSIOF3_TXD_B_MARK,
3031};
3032static const unsigned int msiof3_rxd_b_pins[] = {
3033 /* RXD */
3034 RCAR_GP_PIN(1, 3),
3035};
3036static const unsigned int msiof3_rxd_b_mux[] = {
3037 MSIOF3_RXD_B_MARK,
3038};
3039static const unsigned int msiof3_clk_c_pins[] = {
3040 /* SCK */
3041 RCAR_GP_PIN(1, 12),
3042};
3043static const unsigned int msiof3_clk_c_mux[] = {
3044 MSIOF3_SCK_C_MARK,
3045};
3046static const unsigned int msiof3_sync_c_pins[] = {
3047 /* SYNC */
3048 RCAR_GP_PIN(1, 13),
3049};
3050static const unsigned int msiof3_sync_c_mux[] = {
3051 MSIOF3_SYNC_C_MARK,
3052};
3053static const unsigned int msiof3_txd_c_pins[] = {
3054 /* TXD */
3055 RCAR_GP_PIN(1, 15),
3056};
3057static const unsigned int msiof3_txd_c_mux[] = {
3058 MSIOF3_TXD_C_MARK,
3059};
3060static const unsigned int msiof3_rxd_c_pins[] = {
3061 /* RXD */
3062 RCAR_GP_PIN(1, 14),
3063};
3064static const unsigned int msiof3_rxd_c_mux[] = {
3065 MSIOF3_RXD_C_MARK,
3066};
3067static const unsigned int msiof3_clk_d_pins[] = {
3068 /* SCK */
3069 RCAR_GP_PIN(1, 22),
3070};
3071static const unsigned int msiof3_clk_d_mux[] = {
3072 MSIOF3_SCK_D_MARK,
3073};
3074static const unsigned int msiof3_sync_d_pins[] = {
3075 /* SYNC */
3076 RCAR_GP_PIN(1, 23),
3077};
3078static const unsigned int msiof3_sync_d_mux[] = {
3079 MSIOF3_SYNC_D_MARK,
3080};
3081static const unsigned int msiof3_ss1_d_pins[] = {
3082 /* SS1 */
3083 RCAR_GP_PIN(1, 26),
3084};
3085static const unsigned int msiof3_ss1_d_mux[] = {
3086 MSIOF3_SS1_D_MARK,
3087};
3088static const unsigned int msiof3_txd_d_pins[] = {
3089 /* TXD */
3090 RCAR_GP_PIN(1, 25),
3091};
3092static const unsigned int msiof3_txd_d_mux[] = {
3093 MSIOF3_TXD_D_MARK,
3094};
3095static const unsigned int msiof3_rxd_d_pins[] = {
3096 /* RXD */
3097 RCAR_GP_PIN(1, 24),
3098};
3099static const unsigned int msiof3_rxd_d_mux[] = {
3100 MSIOF3_RXD_D_MARK,
3101};
3102static const unsigned int msiof3_clk_e_pins[] = {
3103 /* SCK */
3104 RCAR_GP_PIN(2, 3),
3105};
3106static const unsigned int msiof3_clk_e_mux[] = {
3107 MSIOF3_SCK_E_MARK,
3108};
3109static const unsigned int msiof3_sync_e_pins[] = {
3110 /* SYNC */
3111 RCAR_GP_PIN(2, 2),
3112};
3113static const unsigned int msiof3_sync_e_mux[] = {
3114 MSIOF3_SYNC_E_MARK,
3115};
3116static const unsigned int msiof3_ss1_e_pins[] = {
3117 /* SS1 */
3118 RCAR_GP_PIN(2, 1),
3119};
3120static const unsigned int msiof3_ss1_e_mux[] = {
3121 MSIOF3_SS1_E_MARK,
3122};
3123static const unsigned int msiof3_ss2_e_pins[] = {
3124 /* SS1 */
3125 RCAR_GP_PIN(2, 0),
3126};
3127static const unsigned int msiof3_ss2_e_mux[] = {
3128 MSIOF3_SS2_E_MARK,
3129};
3130static const unsigned int msiof3_txd_e_pins[] = {
3131 /* TXD */
3132 RCAR_GP_PIN(2, 5),
3133};
3134static const unsigned int msiof3_txd_e_mux[] = {
3135 MSIOF3_TXD_E_MARK,
3136};
3137static const unsigned int msiof3_rxd_e_pins[] = {
3138 /* RXD */
3139 RCAR_GP_PIN(2, 4),
3140};
3141static const unsigned int msiof3_rxd_e_mux[] = {
3142 MSIOF3_RXD_E_MARK,
3143};
3144
3145/* - PWM0 --------------------------------------------------------------------*/
3146static const unsigned int pwm0_pins[] = {
3147 /* PWM */
3148 RCAR_GP_PIN(2, 6),
3149};
3150static const unsigned int pwm0_mux[] = {
3151 PWM0_MARK,
3152};
3153/* - PWM1 --------------------------------------------------------------------*/
3154static const unsigned int pwm1_a_pins[] = {
3155 /* PWM */
3156 RCAR_GP_PIN(2, 7),
3157};
3158static const unsigned int pwm1_a_mux[] = {
3159 PWM1_A_MARK,
3160};
3161static const unsigned int pwm1_b_pins[] = {
3162 /* PWM */
3163 RCAR_GP_PIN(1, 8),
3164};
3165static const unsigned int pwm1_b_mux[] = {
3166 PWM1_B_MARK,
3167};
3168/* - PWM2 --------------------------------------------------------------------*/
3169static const unsigned int pwm2_a_pins[] = {
3170 /* PWM */
3171 RCAR_GP_PIN(2, 8),
3172};
3173static const unsigned int pwm2_a_mux[] = {
3174 PWM2_A_MARK,
3175};
3176static const unsigned int pwm2_b_pins[] = {
3177 /* PWM */
3178 RCAR_GP_PIN(1, 11),
3179};
3180static const unsigned int pwm2_b_mux[] = {
3181 PWM2_B_MARK,
3182};
3183/* - PWM3 --------------------------------------------------------------------*/
3184static const unsigned int pwm3_a_pins[] = {
3185 /* PWM */
3186 RCAR_GP_PIN(1, 0),
3187};
3188static const unsigned int pwm3_a_mux[] = {
3189 PWM3_A_MARK,
3190};
3191static const unsigned int pwm3_b_pins[] = {
3192 /* PWM */
3193 RCAR_GP_PIN(2, 2),
3194};
3195static const unsigned int pwm3_b_mux[] = {
3196 PWM3_B_MARK,
3197};
3198/* - PWM4 --------------------------------------------------------------------*/
3199static const unsigned int pwm4_a_pins[] = {
3200 /* PWM */
3201 RCAR_GP_PIN(1, 1),
3202};
3203static const unsigned int pwm4_a_mux[] = {
3204 PWM4_A_MARK,
3205};
3206static const unsigned int pwm4_b_pins[] = {
3207 /* PWM */
3208 RCAR_GP_PIN(2, 3),
3209};
3210static const unsigned int pwm4_b_mux[] = {
3211 PWM4_B_MARK,
3212};
3213/* - PWM5 --------------------------------------------------------------------*/
3214static const unsigned int pwm5_a_pins[] = {
3215 /* PWM */
3216 RCAR_GP_PIN(1, 2),
3217};
3218static const unsigned int pwm5_a_mux[] = {
3219 PWM5_A_MARK,
3220};
3221static const unsigned int pwm5_b_pins[] = {
3222 /* PWM */
3223 RCAR_GP_PIN(2, 4),
3224};
3225static const unsigned int pwm5_b_mux[] = {
3226 PWM5_B_MARK,
3227};
3228/* - PWM6 --------------------------------------------------------------------*/
3229static const unsigned int pwm6_a_pins[] = {
3230 /* PWM */
3231 RCAR_GP_PIN(1, 3),
3232};
3233static const unsigned int pwm6_a_mux[] = {
3234 PWM6_A_MARK,
3235};
3236static const unsigned int pwm6_b_pins[] = {
3237 /* PWM */
3238 RCAR_GP_PIN(2, 5),
3239};
3240static const unsigned int pwm6_b_mux[] = {
3241 PWM6_B_MARK,
3242};
3243
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]3244/* - SATA --------------------------------------------------------------------*/
3245static const unsigned int sata0_devslp_a_pins[] = {
3246 /* DEVSLP */
3247 RCAR_GP_PIN(6, 16),
3248};
3249static const unsigned int sata0_devslp_a_mux[] = {
3250 SATA_DEVSLP_A_MARK,
3251};
3252static const unsigned int sata0_devslp_b_pins[] = {
3253 /* DEVSLP */
3254 RCAR_GP_PIN(4, 6),
3255};
3256static const unsigned int sata0_devslp_b_mux[] = {
3257 SATA_DEVSLP_B_MARK,
3258};
3259
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]3260/* - SCIF0 ------------------------------------------------------------------ */
3261static const unsigned int scif0_data_pins[] = {
3262 /* RX, TX */
3263 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
3264};
3265static const unsigned int scif0_data_mux[] = {
3266 RX0_MARK, TX0_MARK,
3267};
3268static const unsigned int scif0_clk_pins[] = {
3269 /* SCK */
3270 RCAR_GP_PIN(5, 0),
3271};
3272static const unsigned int scif0_clk_mux[] = {
3273 SCK0_MARK,
3274};
3275static const unsigned int scif0_ctrl_pins[] = {
3276 /* RTS, CTS */
3277 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
3278};
3279static const unsigned int scif0_ctrl_mux[] = {
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]3280 RTS0_N_MARK, CTS0_N_MARK,
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]3281};
3282/* - SCIF1 ------------------------------------------------------------------ */
3283static const unsigned int scif1_data_a_pins[] = {
3284 /* RX, TX */
3285 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
3286};
3287static const unsigned int scif1_data_a_mux[] = {
3288 RX1_A_MARK, TX1_A_MARK,
3289};
3290static const unsigned int scif1_clk_pins[] = {
3291 /* SCK */
3292 RCAR_GP_PIN(6, 21),
3293};
3294static const unsigned int scif1_clk_mux[] = {
3295 SCK1_MARK,
3296};
3297static const unsigned int scif1_ctrl_pins[] = {
3298 /* RTS, CTS */
3299 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
3300};
3301static const unsigned int scif1_ctrl_mux[] = {
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]3302 RTS1_N_MARK, CTS1_N_MARK,
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]3303};
3304
3305static const unsigned int scif1_data_b_pins[] = {
3306 /* RX, TX */
3307 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
3308};
3309static const unsigned int scif1_data_b_mux[] = {
3310 RX1_B_MARK, TX1_B_MARK,
3311};
3312/* - SCIF2 ------------------------------------------------------------------ */
3313static const unsigned int scif2_data_a_pins[] = {
3314 /* RX, TX */
3315 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
3316};
3317static const unsigned int scif2_data_a_mux[] = {
3318 RX2_A_MARK, TX2_A_MARK,
3319};
3320static const unsigned int scif2_clk_pins[] = {
3321 /* SCK */
3322 RCAR_GP_PIN(5, 9),
3323};
3324static const unsigned int scif2_clk_mux[] = {
3325 SCK2_MARK,
3326};
3327static const unsigned int scif2_data_b_pins[] = {
3328 /* RX, TX */
3329 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3330};
3331static const unsigned int scif2_data_b_mux[] = {
3332 RX2_B_MARK, TX2_B_MARK,
3333};
3334/* - SCIF3 ------------------------------------------------------------------ */
3335static const unsigned int scif3_data_a_pins[] = {
3336 /* RX, TX */
3337 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
3338};
3339static const unsigned int scif3_data_a_mux[] = {
3340 RX3_A_MARK, TX3_A_MARK,
3341};
3342static const unsigned int scif3_clk_pins[] = {
3343 /* SCK */
3344 RCAR_GP_PIN(1, 22),
3345};
3346static const unsigned int scif3_clk_mux[] = {
3347 SCK3_MARK,
3348};
3349static const unsigned int scif3_ctrl_pins[] = {
3350 /* RTS, CTS */
3351 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
3352};
3353static const unsigned int scif3_ctrl_mux[] = {
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]3354 RTS3_N_MARK, CTS3_N_MARK,
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]3355};
3356static const unsigned int scif3_data_b_pins[] = {
3357 /* RX, TX */
3358 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
3359};
3360static const unsigned int scif3_data_b_mux[] = {
3361 RX3_B_MARK, TX3_B_MARK,
3362};
3363/* - SCIF4 ------------------------------------------------------------------ */
3364static const unsigned int scif4_data_a_pins[] = {
3365 /* RX, TX */
3366 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
3367};
3368static const unsigned int scif4_data_a_mux[] = {
3369 RX4_A_MARK, TX4_A_MARK,
3370};
3371static const unsigned int scif4_clk_a_pins[] = {
3372 /* SCK */
3373 RCAR_GP_PIN(2, 10),
3374};
3375static const unsigned int scif4_clk_a_mux[] = {
3376 SCK4_A_MARK,
3377};
3378static const unsigned int scif4_ctrl_a_pins[] = {
3379 /* RTS, CTS */
3380 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
3381};
3382static const unsigned int scif4_ctrl_a_mux[] = {
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]3383 RTS4_N_A_MARK, CTS4_N_A_MARK,
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]3384};
3385static const unsigned int scif4_data_b_pins[] = {
3386 /* RX, TX */
3387 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3388};
3389static const unsigned int scif4_data_b_mux[] = {
3390 RX4_B_MARK, TX4_B_MARK,
3391};
3392static const unsigned int scif4_clk_b_pins[] = {
3393 /* SCK */
3394 RCAR_GP_PIN(1, 5),
3395};
3396static const unsigned int scif4_clk_b_mux[] = {
3397 SCK4_B_MARK,
3398};
3399static const unsigned int scif4_ctrl_b_pins[] = {
3400 /* RTS, CTS */
3401 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
3402};
3403static const unsigned int scif4_ctrl_b_mux[] = {
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]3404 RTS4_N_B_MARK, CTS4_N_B_MARK,
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]3405};
3406static const unsigned int scif4_data_c_pins[] = {
3407 /* RX, TX */
3408 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3409};
3410static const unsigned int scif4_data_c_mux[] = {
3411 RX4_C_MARK, TX4_C_MARK,
3412};
3413static const unsigned int scif4_clk_c_pins[] = {
3414 /* SCK */
3415 RCAR_GP_PIN(0, 8),
3416};
3417static const unsigned int scif4_clk_c_mux[] = {
3418 SCK4_C_MARK,
3419};
3420static const unsigned int scif4_ctrl_c_pins[] = {
3421 /* RTS, CTS */
3422 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
3423};
3424static const unsigned int scif4_ctrl_c_mux[] = {
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]3425 RTS4_N_C_MARK, CTS4_N_C_MARK,
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]3426};
3427/* - SCIF5 ------------------------------------------------------------------ */
3428static const unsigned int scif5_data_a_pins[] = {
3429 /* RX, TX */
3430 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3431};
3432static const unsigned int scif5_data_a_mux[] = {
3433 RX5_A_MARK, TX5_A_MARK,
3434};
3435static const unsigned int scif5_clk_a_pins[] = {
3436 /* SCK */
3437 RCAR_GP_PIN(6, 21),
3438};
3439static const unsigned int scif5_clk_a_mux[] = {
3440 SCK5_A_MARK,
3441};
3442static const unsigned int scif5_data_b_pins[] = {
3443 /* RX, TX */
3444 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 18),
3445};
3446static const unsigned int scif5_data_b_mux[] = {
3447 RX5_B_MARK, TX5_B_MARK,
3448};
3449static const unsigned int scif5_clk_b_pins[] = {
3450 /* SCK */
3451 RCAR_GP_PIN(5, 0),
3452};
3453static const unsigned int scif5_clk_b_mux[] = {
3454 SCK5_B_MARK,
3455};
3456
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]3457/* - SCIF Clock ------------------------------------------------------------- */
3458static const unsigned int scif_clk_a_pins[] = {
3459 /* SCIF_CLK */
3460 RCAR_GP_PIN(6, 23),
3461};
3462static const unsigned int scif_clk_a_mux[] = {
3463 SCIF_CLK_A_MARK,
3464};
3465static const unsigned int scif_clk_b_pins[] = {
3466 /* SCIF_CLK */
3467 RCAR_GP_PIN(5, 9),
3468};
3469static const unsigned int scif_clk_b_mux[] = {
3470 SCIF_CLK_B_MARK,
3471};
3472
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]3473/* - SDHI0 ------------------------------------------------------------------ */
3474static const unsigned int sdhi0_data1_pins[] = {
3475 /* D0 */
3476 RCAR_GP_PIN(3, 2),
3477};
3478static const unsigned int sdhi0_data1_mux[] = {
3479 SD0_DAT0_MARK,
3480};
3481static const unsigned int sdhi0_data4_pins[] = {
3482 /* D[0:3] */
3483 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3484 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3485};
3486static const unsigned int sdhi0_data4_mux[] = {
3487 SD0_DAT0_MARK, SD0_DAT1_MARK,
3488 SD0_DAT2_MARK, SD0_DAT3_MARK,
3489};
3490static const unsigned int sdhi0_ctrl_pins[] = {
3491 /* CLK, CMD */
3492 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3493};
3494static const unsigned int sdhi0_ctrl_mux[] = {
3495 SD0_CLK_MARK, SD0_CMD_MARK,
3496};
3497static const unsigned int sdhi0_cd_pins[] = {
3498 /* CD */
3499 RCAR_GP_PIN(3, 12),
3500};
3501static const unsigned int sdhi0_cd_mux[] = {
3502 SD0_CD_MARK,
3503};
3504static const unsigned int sdhi0_wp_pins[] = {
3505 /* WP */
3506 RCAR_GP_PIN(3, 13),
3507};
3508static const unsigned int sdhi0_wp_mux[] = {
3509 SD0_WP_MARK,
3510};
3511/* - SDHI1 ------------------------------------------------------------------ */
3512static const unsigned int sdhi1_data1_pins[] = {
3513 /* D0 */
3514 RCAR_GP_PIN(3, 8),
3515};
3516static const unsigned int sdhi1_data1_mux[] = {
3517 SD1_DAT0_MARK,
3518};
3519static const unsigned int sdhi1_data4_pins[] = {
3520 /* D[0:3] */
3521 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3522 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3523};
3524static const unsigned int sdhi1_data4_mux[] = {
3525 SD1_DAT0_MARK, SD1_DAT1_MARK,
3526 SD1_DAT2_MARK, SD1_DAT3_MARK,
3527};
3528static const unsigned int sdhi1_ctrl_pins[] = {
3529 /* CLK, CMD */
3530 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
3531};
3532static const unsigned int sdhi1_ctrl_mux[] = {
3533 SD1_CLK_MARK, SD1_CMD_MARK,
3534};
3535static const unsigned int sdhi1_cd_pins[] = {
3536 /* CD */
3537 RCAR_GP_PIN(3, 14),
3538};
3539static const unsigned int sdhi1_cd_mux[] = {
3540 SD1_CD_MARK,
3541};
3542static const unsigned int sdhi1_wp_pins[] = {
3543 /* WP */
3544 RCAR_GP_PIN(3, 15),
3545};
3546static const unsigned int sdhi1_wp_mux[] = {
3547 SD1_WP_MARK,
3548};
3549/* - SDHI2 ------------------------------------------------------------------ */
3550static const unsigned int sdhi2_data1_pins[] = {
3551 /* D0 */
3552 RCAR_GP_PIN(4, 2),
3553};
3554static const unsigned int sdhi2_data1_mux[] = {
3555 SD2_DAT0_MARK,
3556};
3557static const unsigned int sdhi2_data4_pins[] = {
3558 /* D[0:3] */
3559 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3560 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3561};
3562static const unsigned int sdhi2_data4_mux[] = {
3563 SD2_DAT0_MARK, SD2_DAT1_MARK,
3564 SD2_DAT2_MARK, SD2_DAT3_MARK,
3565};
3566static const unsigned int sdhi2_data8_pins[] = {
3567 /* D[0:7] */
3568 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
3569 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
3570 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3571 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3572};
3573static const unsigned int sdhi2_data8_mux[] = {
3574 SD2_DAT0_MARK, SD2_DAT1_MARK,
3575 SD2_DAT2_MARK, SD2_DAT3_MARK,
3576 SD2_DAT4_MARK, SD2_DAT5_MARK,
3577 SD2_DAT6_MARK, SD2_DAT7_MARK,
3578};
3579static const unsigned int sdhi2_ctrl_pins[] = {
3580 /* CLK, CMD */
3581 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
3582};
3583static const unsigned int sdhi2_ctrl_mux[] = {
3584 SD2_CLK_MARK, SD2_CMD_MARK,
3585};
3586static const unsigned int sdhi2_cd_a_pins[] = {
3587 /* CD */
3588 RCAR_GP_PIN(4, 13),
3589};
3590static const unsigned int sdhi2_cd_a_mux[] = {
3591 SD2_CD_A_MARK,
3592};
3593static const unsigned int sdhi2_cd_b_pins[] = {
3594 /* CD */
3595 RCAR_GP_PIN(5, 10),
3596};
3597static const unsigned int sdhi2_cd_b_mux[] = {
3598 SD2_CD_B_MARK,
3599};
3600static const unsigned int sdhi2_wp_a_pins[] = {
3601 /* WP */
3602 RCAR_GP_PIN(4, 14),
3603};
3604static const unsigned int sdhi2_wp_a_mux[] = {
3605 SD2_WP_A_MARK,
3606};
3607static const unsigned int sdhi2_wp_b_pins[] = {
3608 /* WP */
3609 RCAR_GP_PIN(5, 11),
3610};
3611static const unsigned int sdhi2_wp_b_mux[] = {
3612 SD2_WP_B_MARK,
3613};
3614static const unsigned int sdhi2_ds_pins[] = {
3615 /* DS */
3616 RCAR_GP_PIN(4, 6),
3617};
3618static const unsigned int sdhi2_ds_mux[] = {
3619 SD2_DS_MARK,
3620};
3621/* - SDHI3 ------------------------------------------------------------------ */
3622static const unsigned int sdhi3_data1_pins[] = {
3623 /* D0 */
3624 RCAR_GP_PIN(4, 9),
3625};
3626static const unsigned int sdhi3_data1_mux[] = {
3627 SD3_DAT0_MARK,
3628};
3629static const unsigned int sdhi3_data4_pins[] = {
3630 /* D[0:3] */
3631 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3632 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3633};
3634static const unsigned int sdhi3_data4_mux[] = {
3635 SD3_DAT0_MARK, SD3_DAT1_MARK,
3636 SD3_DAT2_MARK, SD3_DAT3_MARK,
3637};
3638static const unsigned int sdhi3_data8_pins[] = {
3639 /* D[0:7] */
3640 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3641 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3642 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3643 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3644};
3645static const unsigned int sdhi3_data8_mux[] = {
3646 SD3_DAT0_MARK, SD3_DAT1_MARK,
3647 SD3_DAT2_MARK, SD3_DAT3_MARK,
3648 SD3_DAT4_MARK, SD3_DAT5_MARK,
3649 SD3_DAT6_MARK, SD3_DAT7_MARK,
3650};
3651static const unsigned int sdhi3_ctrl_pins[] = {
3652 /* CLK, CMD */
3653 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3654};
3655static const unsigned int sdhi3_ctrl_mux[] = {
3656 SD3_CLK_MARK, SD3_CMD_MARK,
3657};
3658static const unsigned int sdhi3_cd_pins[] = {
3659 /* CD */
3660 RCAR_GP_PIN(4, 15),
3661};
3662static const unsigned int sdhi3_cd_mux[] = {
3663 SD3_CD_MARK,
3664};
3665static const unsigned int sdhi3_wp_pins[] = {
3666 /* WP */
3667 RCAR_GP_PIN(4, 16),
3668};
3669static const unsigned int sdhi3_wp_mux[] = {
3670 SD3_WP_MARK,
3671};
3672static const unsigned int sdhi3_ds_pins[] = {
3673 /* DS */
3674 RCAR_GP_PIN(4, 17),
3675};
3676static const unsigned int sdhi3_ds_mux[] = {
3677 SD3_DS_MARK,
3678};
3679
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]3680/* - SSI -------------------------------------------------------------------- */
3681static const unsigned int ssi0_data_pins[] = {
3682 /* SDATA */
3683 RCAR_GP_PIN(6, 2),
3684};
3685static const unsigned int ssi0_data_mux[] = {
3686 SSI_SDATA0_MARK,
3687};
3688static const unsigned int ssi01239_ctrl_pins[] = {
3689 /* SCK, WS */
3690 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3691};
3692static const unsigned int ssi01239_ctrl_mux[] = {
3693 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3694};
3695static const unsigned int ssi1_data_a_pins[] = {
3696 /* SDATA */
3697 RCAR_GP_PIN(6, 3),
3698};
3699static const unsigned int ssi1_data_a_mux[] = {
3700 SSI_SDATA1_A_MARK,
3701};
3702static const unsigned int ssi1_data_b_pins[] = {
3703 /* SDATA */
3704 RCAR_GP_PIN(5, 12),
3705};
3706static const unsigned int ssi1_data_b_mux[] = {
3707 SSI_SDATA1_B_MARK,
3708};
3709static const unsigned int ssi1_ctrl_a_pins[] = {
3710 /* SCK, WS */
3711 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3712};
3713static const unsigned int ssi1_ctrl_a_mux[] = {
3714 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3715};
3716static const unsigned int ssi1_ctrl_b_pins[] = {
3717 /* SCK, WS */
3718 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3719};
3720static const unsigned int ssi1_ctrl_b_mux[] = {
3721 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3722};
3723static const unsigned int ssi2_data_a_pins[] = {
3724 /* SDATA */
3725 RCAR_GP_PIN(6, 4),
3726};
3727static const unsigned int ssi2_data_a_mux[] = {
3728 SSI_SDATA2_A_MARK,
3729};
3730static const unsigned int ssi2_data_b_pins[] = {
3731 /* SDATA */
3732 RCAR_GP_PIN(5, 13),
3733};
3734static const unsigned int ssi2_data_b_mux[] = {
3735 SSI_SDATA2_B_MARK,
3736};
3737static const unsigned int ssi2_ctrl_a_pins[] = {
3738 /* SCK, WS */
3739 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3740};
3741static const unsigned int ssi2_ctrl_a_mux[] = {
3742 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3743};
3744static const unsigned int ssi2_ctrl_b_pins[] = {
3745 /* SCK, WS */
3746 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3747};
3748static const unsigned int ssi2_ctrl_b_mux[] = {
3749 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3750};
3751static const unsigned int ssi3_data_pins[] = {
3752 /* SDATA */
3753 RCAR_GP_PIN(6, 7),
3754};
3755static const unsigned int ssi3_data_mux[] = {
3756 SSI_SDATA3_MARK,
3757};
3758static const unsigned int ssi349_ctrl_pins[] = {
3759 /* SCK, WS */
3760 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3761};
3762static const unsigned int ssi349_ctrl_mux[] = {
3763 SSI_SCK349_MARK, SSI_WS349_MARK,
3764};
3765static const unsigned int ssi4_data_pins[] = {
3766 /* SDATA */
3767 RCAR_GP_PIN(6, 10),
3768};
3769static const unsigned int ssi4_data_mux[] = {
3770 SSI_SDATA4_MARK,
3771};
3772static const unsigned int ssi4_ctrl_pins[] = {
3773 /* SCK, WS */
3774 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3775};
3776static const unsigned int ssi4_ctrl_mux[] = {
3777 SSI_SCK4_MARK, SSI_WS4_MARK,
3778};
3779static const unsigned int ssi5_data_pins[] = {
3780 /* SDATA */
3781 RCAR_GP_PIN(6, 13),
3782};
3783static const unsigned int ssi5_data_mux[] = {
3784 SSI_SDATA5_MARK,
3785};
3786static const unsigned int ssi5_ctrl_pins[] = {
3787 /* SCK, WS */
3788 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3789};
3790static const unsigned int ssi5_ctrl_mux[] = {
3791 SSI_SCK5_MARK, SSI_WS5_MARK,
3792};
3793static const unsigned int ssi6_data_pins[] = {
3794 /* SDATA */
3795 RCAR_GP_PIN(6, 16),
3796};
3797static const unsigned int ssi6_data_mux[] = {
3798 SSI_SDATA6_MARK,
3799};
3800static const unsigned int ssi6_ctrl_pins[] = {
3801 /* SCK, WS */
3802 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3803};
3804static const unsigned int ssi6_ctrl_mux[] = {
3805 SSI_SCK6_MARK, SSI_WS6_MARK,
3806};
3807static const unsigned int ssi7_data_pins[] = {
3808 /* SDATA */
3809 RCAR_GP_PIN(6, 19),
3810};
3811static const unsigned int ssi7_data_mux[] = {
3812 SSI_SDATA7_MARK,
3813};
3814static const unsigned int ssi78_ctrl_pins[] = {
3815 /* SCK, WS */
3816 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3817};
3818static const unsigned int ssi78_ctrl_mux[] = {
3819 SSI_SCK78_MARK, SSI_WS78_MARK,
3820};
3821static const unsigned int ssi8_data_pins[] = {
3822 /* SDATA */
3823 RCAR_GP_PIN(6, 20),
3824};
3825static const unsigned int ssi8_data_mux[] = {
3826 SSI_SDATA8_MARK,
3827};
3828static const unsigned int ssi9_data_a_pins[] = {
3829 /* SDATA */
3830 RCAR_GP_PIN(6, 21),
3831};
3832static const unsigned int ssi9_data_a_mux[] = {
3833 SSI_SDATA9_A_MARK,
3834};
3835static const unsigned int ssi9_data_b_pins[] = {
3836 /* SDATA */
3837 RCAR_GP_PIN(5, 14),
3838};
3839static const unsigned int ssi9_data_b_mux[] = {
3840 SSI_SDATA9_B_MARK,
3841};
3842static const unsigned int ssi9_ctrl_a_pins[] = {
3843 /* SCK, WS */
3844 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3845};
3846static const unsigned int ssi9_ctrl_a_mux[] = {
3847 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3848};
3849static const unsigned int ssi9_ctrl_b_pins[] = {
3850 /* SCK, WS */
3851 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3852};
3853static const unsigned int ssi9_ctrl_b_mux[] = {
3854 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3855};
3856
3857/* - TMU -------------------------------------------------------------------- */
3858static const unsigned int tmu_tclk1_a_pins[] = {
3859 /* TCLK */
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]3860 RCAR_GP_PIN(6, 23),
3861};
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]3862static const unsigned int tmu_tclk1_a_mux[] = {
3863 TCLK1_A_MARK,
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]3864};
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]3865static const unsigned int tmu_tclk1_b_pins[] = {
3866 /* TCLK */
3867 RCAR_GP_PIN(5, 19),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]3868};
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]3869static const unsigned int tmu_tclk1_b_mux[] = {
3870 TCLK1_B_MARK,
3871};
3872static const unsigned int tmu_tclk2_a_pins[] = {
3873 /* TCLK */
3874 RCAR_GP_PIN(6, 19),
3875};
3876static const unsigned int tmu_tclk2_a_mux[] = {
3877 TCLK2_A_MARK,
3878};
3879static const unsigned int tmu_tclk2_b_pins[] = {
3880 /* TCLK */
3881 RCAR_GP_PIN(6, 28),
3882};
3883static const unsigned int tmu_tclk2_b_mux[] = {
3884 TCLK2_B_MARK,
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]3885};
3886
3887/* - USB0 ------------------------------------------------------------------- */
3888static const unsigned int usb0_pins[] = {
3889 /* PWEN, OVC */
3890 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3891};
3892static const unsigned int usb0_mux[] = {
3893 USB0_PWEN_MARK, USB0_OVC_MARK,
3894};
3895/* - USB1 ------------------------------------------------------------------- */
3896static const unsigned int usb1_pins[] = {
3897 /* PWEN, OVC */
3898 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3899};
3900static const unsigned int usb1_mux[] = {
3901 USB1_PWEN_MARK, USB1_OVC_MARK,
3902};
3903/* - USB2 ------------------------------------------------------------------- */
3904static const unsigned int usb2_pins[] = {
3905 /* PWEN, OVC */
3906 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3907};
3908static const unsigned int usb2_mux[] = {
3909 USB2_PWEN_MARK, USB2_OVC_MARK,
3910};
3911/* - USB2_CH3 --------------------------------------------------------------- */
3912static const unsigned int usb2_ch3_pins[] = {
3913 /* PWEN, OVC */
3914 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3915};
3916static const unsigned int usb2_ch3_mux[] = {
3917 USB2_CH3_PWEN_MARK, USB2_CH3_OVC_MARK,
3918};
3919
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]3920/* - USB30 ------------------------------------------------------------------ */
3921static const unsigned int usb30_pins[] = {
3922 /* PWEN, OVC */
3923 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3924};
3925static const unsigned int usb30_mux[] = {
3926 USB30_PWEN_MARK, USB30_OVC_MARK,
3927};
3928
3929/* - VIN4 ------------------------------------------------------------------- */
3930static const unsigned int vin4_data18_a_pins[] = {
3931 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3932 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3933 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3934 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3935 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3936 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3937 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3938 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3939 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3940};
3941static const unsigned int vin4_data18_a_mux[] = {
3942 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3943 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3944 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3945 VI4_DATA10_MARK, VI4_DATA11_MARK,
3946 VI4_DATA12_MARK, VI4_DATA13_MARK,
3947 VI4_DATA14_MARK, VI4_DATA15_MARK,
3948 VI4_DATA18_MARK, VI4_DATA19_MARK,
3949 VI4_DATA20_MARK, VI4_DATA21_MARK,
3950 VI4_DATA22_MARK, VI4_DATA23_MARK,
3951};
3952static const unsigned int vin4_data18_b_pins[] = {
3953 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
3954 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
3955 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
3956 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3957 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3958 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3959 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3960 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3961 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3962};
3963static const unsigned int vin4_data18_b_mux[] = {
3964 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
3965 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
3966 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
3967 VI4_DATA10_MARK, VI4_DATA11_MARK,
3968 VI4_DATA12_MARK, VI4_DATA13_MARK,
3969 VI4_DATA14_MARK, VI4_DATA15_MARK,
3970 VI4_DATA18_MARK, VI4_DATA19_MARK,
3971 VI4_DATA20_MARK, VI4_DATA21_MARK,
3972 VI4_DATA22_MARK, VI4_DATA23_MARK,
3973};
3974static const union vin_data vin4_data_a_pins = {
3975 .data24 = {
3976 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3977 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3978 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3979 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3980 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
3981 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
3982 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3983 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3984 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3985 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3986 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3987 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3988 },
3989};
3990static const union vin_data vin4_data_a_mux = {
3991 .data24 = {
3992 VI4_DATA0_A_MARK, VI4_DATA1_A_MARK,
3993 VI4_DATA2_A_MARK, VI4_DATA3_A_MARK,
3994 VI4_DATA4_A_MARK, VI4_DATA5_A_MARK,
3995 VI4_DATA6_A_MARK, VI4_DATA7_A_MARK,
3996 VI4_DATA8_MARK, VI4_DATA9_MARK,
3997 VI4_DATA10_MARK, VI4_DATA11_MARK,
3998 VI4_DATA12_MARK, VI4_DATA13_MARK,
3999 VI4_DATA14_MARK, VI4_DATA15_MARK,
4000 VI4_DATA16_MARK, VI4_DATA17_MARK,
4001 VI4_DATA18_MARK, VI4_DATA19_MARK,
4002 VI4_DATA20_MARK, VI4_DATA21_MARK,
4003 VI4_DATA22_MARK, VI4_DATA23_MARK,
4004 },
4005};
4006static const union vin_data vin4_data_b_pins = {
4007 .data24 = {
4008 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
4009 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
4010 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
4011 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
4012 RCAR_GP_PIN(1, 0), RCAR_GP_PIN(1, 1),
4013 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
4014 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4015 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4016 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4017 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4018 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4019 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4020 },
4021};
4022static const union vin_data vin4_data_b_mux = {
4023 .data24 = {
4024 VI4_DATA0_B_MARK, VI4_DATA1_B_MARK,
4025 VI4_DATA2_B_MARK, VI4_DATA3_B_MARK,
4026 VI4_DATA4_B_MARK, VI4_DATA5_B_MARK,
4027 VI4_DATA6_B_MARK, VI4_DATA7_B_MARK,
4028 VI4_DATA8_MARK, VI4_DATA9_MARK,
4029 VI4_DATA10_MARK, VI4_DATA11_MARK,
4030 VI4_DATA12_MARK, VI4_DATA13_MARK,
4031 VI4_DATA14_MARK, VI4_DATA15_MARK,
4032 VI4_DATA16_MARK, VI4_DATA17_MARK,
4033 VI4_DATA18_MARK, VI4_DATA19_MARK,
4034 VI4_DATA20_MARK, VI4_DATA21_MARK,
4035 VI4_DATA22_MARK, VI4_DATA23_MARK,
4036 },
4037};
4038static const unsigned int vin4_sync_pins[] = {
4039 /* HSYNC#, VSYNC# */
4040 RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 17),
4041};
4042static const unsigned int vin4_sync_mux[] = {
4043 VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK,
4044};
4045static const unsigned int vin4_field_pins[] = {
4046 /* FIELD */
4047 RCAR_GP_PIN(1, 16),
4048};
4049static const unsigned int vin4_field_mux[] = {
4050 VI4_FIELD_MARK,
4051};
4052static const unsigned int vin4_clkenb_pins[] = {
4053 /* CLKENB */
4054 RCAR_GP_PIN(1, 19),
4055};
4056static const unsigned int vin4_clkenb_mux[] = {
4057 VI4_CLKENB_MARK,
4058};
4059static const unsigned int vin4_clk_pins[] = {
4060 /* CLK */
4061 RCAR_GP_PIN(1, 27),
4062};
4063static const unsigned int vin4_clk_mux[] = {
4064 VI4_CLK_MARK,
4065};
4066
4067/* - VIN5 ------------------------------------------------------------------- */
4068static const unsigned int vin5_data8_pins[] = {
4069 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4070 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4071 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4072 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4073};
4074static const unsigned int vin5_data8_mux[] = {
4075 VI5_DATA0_MARK, VI5_DATA1_MARK,
4076 VI5_DATA2_MARK, VI5_DATA3_MARK,
4077 VI5_DATA4_MARK, VI5_DATA5_MARK,
4078 VI5_DATA6_MARK, VI5_DATA7_MARK,
4079};
4080static const unsigned int vin5_data10_pins[] = {
4081 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4082 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4083 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4084 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4085 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4086};
4087static const unsigned int vin5_data10_mux[] = {
4088 VI5_DATA0_MARK, VI5_DATA1_MARK,
4089 VI5_DATA2_MARK, VI5_DATA3_MARK,
4090 VI5_DATA4_MARK, VI5_DATA5_MARK,
4091 VI5_DATA6_MARK, VI5_DATA7_MARK,
4092 VI5_DATA8_MARK, VI5_DATA9_MARK,
4093};
4094static const unsigned int vin5_data12_pins[] = {
4095 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4096 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4097 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4098 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4099 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4100 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4101};
4102static const unsigned int vin5_data12_mux[] = {
4103 VI5_DATA0_MARK, VI5_DATA1_MARK,
4104 VI5_DATA2_MARK, VI5_DATA3_MARK,
4105 VI5_DATA4_MARK, VI5_DATA5_MARK,
4106 VI5_DATA6_MARK, VI5_DATA7_MARK,
4107 VI5_DATA8_MARK, VI5_DATA9_MARK,
4108 VI5_DATA10_MARK, VI5_DATA11_MARK,
4109};
4110static const unsigned int vin5_data16_pins[] = {
4111 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
4112 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
4113 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
4114 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
4115 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
4116 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
4117 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
4118 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
4119};
4120static const unsigned int vin5_data16_mux[] = {
4121 VI5_DATA0_MARK, VI5_DATA1_MARK,
4122 VI5_DATA2_MARK, VI5_DATA3_MARK,
4123 VI5_DATA4_MARK, VI5_DATA5_MARK,
4124 VI5_DATA6_MARK, VI5_DATA7_MARK,
4125 VI5_DATA8_MARK, VI5_DATA9_MARK,
4126 VI5_DATA10_MARK, VI5_DATA11_MARK,
4127 VI5_DATA12_MARK, VI5_DATA13_MARK,
4128 VI5_DATA14_MARK, VI5_DATA15_MARK,
4129};
4130static const unsigned int vin5_sync_pins[] = {
4131 /* HSYNC#, VSYNC# */
4132 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
4133};
4134static const unsigned int vin5_sync_mux[] = {
4135 VI5_HSYNC_N_MARK, VI5_VSYNC_N_MARK,
4136};
4137static const unsigned int vin5_field_pins[] = {
4138 RCAR_GP_PIN(1, 11),
4139};
4140static const unsigned int vin5_field_mux[] = {
4141 /* FIELD */
4142 VI5_FIELD_MARK,
4143};
4144static const unsigned int vin5_clkenb_pins[] = {
4145 RCAR_GP_PIN(1, 20),
4146};
4147static const unsigned int vin5_clkenb_mux[] = {
4148 /* CLKENB */
4149 VI5_CLKENB_MARK,
4150};
4151static const unsigned int vin5_clk_pins[] = {
4152 RCAR_GP_PIN(1, 21),
4153};
4154static const unsigned int vin5_clk_mux[] = {
4155 /* CLK */
4156 VI5_CLK_MARK,
4157};
4158
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]4159static const struct sh_pfc_pin_group pinmux_groups[] = {
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]4160 SH_PFC_PIN_GROUP(audio_clk_a_a),
4161 SH_PFC_PIN_GROUP(audio_clk_a_b),
4162 SH_PFC_PIN_GROUP(audio_clk_a_c),
4163 SH_PFC_PIN_GROUP(audio_clk_b_a),
4164 SH_PFC_PIN_GROUP(audio_clk_b_b),
4165 SH_PFC_PIN_GROUP(audio_clk_c_a),
4166 SH_PFC_PIN_GROUP(audio_clk_c_b),
4167 SH_PFC_PIN_GROUP(audio_clkout_a),
4168 SH_PFC_PIN_GROUP(audio_clkout_b),
4169 SH_PFC_PIN_GROUP(audio_clkout_c),
4170 SH_PFC_PIN_GROUP(audio_clkout_d),
4171 SH_PFC_PIN_GROUP(audio_clkout1_a),
4172 SH_PFC_PIN_GROUP(audio_clkout1_b),
4173 SH_PFC_PIN_GROUP(audio_clkout2_a),
4174 SH_PFC_PIN_GROUP(audio_clkout2_b),
4175 SH_PFC_PIN_GROUP(audio_clkout3_a),
4176 SH_PFC_PIN_GROUP(audio_clkout3_b),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]4177 SH_PFC_PIN_GROUP(avb_link),
4178 SH_PFC_PIN_GROUP(avb_magic),
4179 SH_PFC_PIN_GROUP(avb_phy_int),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]4180 SH_PFC_PIN_GROUP_ALIAS(avb_mdc, avb_mdio), /* Deprecated */
4181 SH_PFC_PIN_GROUP(avb_mdio),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]4182 SH_PFC_PIN_GROUP(avb_mii),
4183 SH_PFC_PIN_GROUP(avb_avtp_pps),
4184 SH_PFC_PIN_GROUP(avb_avtp_match_a),
4185 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
4186 SH_PFC_PIN_GROUP(avb_avtp_match_b),
4187 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]4188 SH_PFC_PIN_GROUP(can0_data_a),
4189 SH_PFC_PIN_GROUP(can0_data_b),
4190 SH_PFC_PIN_GROUP(can1_data),
4191 SH_PFC_PIN_GROUP(can_clk),
4192 SH_PFC_PIN_GROUP(canfd0_data_a),
4193 SH_PFC_PIN_GROUP(canfd0_data_b),
4194 SH_PFC_PIN_GROUP(canfd1_data),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]4195 SH_PFC_PIN_GROUP(drif0_ctrl_a),
4196 SH_PFC_PIN_GROUP(drif0_data0_a),
4197 SH_PFC_PIN_GROUP(drif0_data1_a),
4198 SH_PFC_PIN_GROUP(drif0_ctrl_b),
4199 SH_PFC_PIN_GROUP(drif0_data0_b),
4200 SH_PFC_PIN_GROUP(drif0_data1_b),
4201 SH_PFC_PIN_GROUP(drif0_ctrl_c),
4202 SH_PFC_PIN_GROUP(drif0_data0_c),
4203 SH_PFC_PIN_GROUP(drif0_data1_c),
4204 SH_PFC_PIN_GROUP(drif1_ctrl_a),
4205 SH_PFC_PIN_GROUP(drif1_data0_a),
4206 SH_PFC_PIN_GROUP(drif1_data1_a),
4207 SH_PFC_PIN_GROUP(drif1_ctrl_b),
4208 SH_PFC_PIN_GROUP(drif1_data0_b),
4209 SH_PFC_PIN_GROUP(drif1_data1_b),
4210 SH_PFC_PIN_GROUP(drif1_ctrl_c),
4211 SH_PFC_PIN_GROUP(drif1_data0_c),
4212 SH_PFC_PIN_GROUP(drif1_data1_c),
4213 SH_PFC_PIN_GROUP(drif2_ctrl_a),
4214 SH_PFC_PIN_GROUP(drif2_data0_a),
4215 SH_PFC_PIN_GROUP(drif2_data1_a),
4216 SH_PFC_PIN_GROUP(drif2_ctrl_b),
4217 SH_PFC_PIN_GROUP(drif2_data0_b),
4218 SH_PFC_PIN_GROUP(drif2_data1_b),
4219 SH_PFC_PIN_GROUP(drif3_ctrl_a),
4220 SH_PFC_PIN_GROUP(drif3_data0_a),
4221 SH_PFC_PIN_GROUP(drif3_data1_a),
4222 SH_PFC_PIN_GROUP(drif3_ctrl_b),
4223 SH_PFC_PIN_GROUP(drif3_data0_b),
4224 SH_PFC_PIN_GROUP(drif3_data1_b),
4225 SH_PFC_PIN_GROUP(du_rgb666),
4226 SH_PFC_PIN_GROUP(du_rgb888),
4227 SH_PFC_PIN_GROUP(du_clk_out_0),
4228 SH_PFC_PIN_GROUP(du_clk_out_1),
4229 SH_PFC_PIN_GROUP(du_sync),
4230 SH_PFC_PIN_GROUP(du_oddf),
4231 SH_PFC_PIN_GROUP(du_cde),
4232 SH_PFC_PIN_GROUP(du_disp),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]4233 SH_PFC_PIN_GROUP(hdmi0_cec),
4234 SH_PFC_PIN_GROUP(hdmi1_cec),
4235 SH_PFC_PIN_GROUP(hscif0_data),
4236 SH_PFC_PIN_GROUP(hscif0_clk),
4237 SH_PFC_PIN_GROUP(hscif0_ctrl),
4238 SH_PFC_PIN_GROUP(hscif1_data_a),
4239 SH_PFC_PIN_GROUP(hscif1_clk_a),
4240 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
4241 SH_PFC_PIN_GROUP(hscif1_data_b),
4242 SH_PFC_PIN_GROUP(hscif1_clk_b),
4243 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
4244 SH_PFC_PIN_GROUP(hscif2_data_a),
4245 SH_PFC_PIN_GROUP(hscif2_clk_a),
4246 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
4247 SH_PFC_PIN_GROUP(hscif2_data_b),
4248 SH_PFC_PIN_GROUP(hscif2_clk_b),
4249 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
4250 SH_PFC_PIN_GROUP(hscif2_data_c),
4251 SH_PFC_PIN_GROUP(hscif2_clk_c),
4252 SH_PFC_PIN_GROUP(hscif2_ctrl_c),
4253 SH_PFC_PIN_GROUP(hscif3_data_a),
4254 SH_PFC_PIN_GROUP(hscif3_clk),
4255 SH_PFC_PIN_GROUP(hscif3_ctrl),
4256 SH_PFC_PIN_GROUP(hscif3_data_b),
4257 SH_PFC_PIN_GROUP(hscif3_data_c),
4258 SH_PFC_PIN_GROUP(hscif3_data_d),
4259 SH_PFC_PIN_GROUP(hscif4_data_a),
4260 SH_PFC_PIN_GROUP(hscif4_clk),
4261 SH_PFC_PIN_GROUP(hscif4_ctrl),
4262 SH_PFC_PIN_GROUP(hscif4_data_b),
4263 SH_PFC_PIN_GROUP(i2c1_a),
4264 SH_PFC_PIN_GROUP(i2c1_b),
4265 SH_PFC_PIN_GROUP(i2c2_a),
4266 SH_PFC_PIN_GROUP(i2c2_b),
4267 SH_PFC_PIN_GROUP(i2c6_a),
4268 SH_PFC_PIN_GROUP(i2c6_b),
4269 SH_PFC_PIN_GROUP(i2c6_c),
4270 SH_PFC_PIN_GROUP(intc_ex_irq0),
4271 SH_PFC_PIN_GROUP(intc_ex_irq1),
4272 SH_PFC_PIN_GROUP(intc_ex_irq2),
4273 SH_PFC_PIN_GROUP(intc_ex_irq3),
4274 SH_PFC_PIN_GROUP(intc_ex_irq4),
4275 SH_PFC_PIN_GROUP(intc_ex_irq5),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]4276 SH_PFC_PIN_GROUP(msiof0_clk),
4277 SH_PFC_PIN_GROUP(msiof0_sync),
4278 SH_PFC_PIN_GROUP(msiof0_ss1),
4279 SH_PFC_PIN_GROUP(msiof0_ss2),
4280 SH_PFC_PIN_GROUP(msiof0_txd),
4281 SH_PFC_PIN_GROUP(msiof0_rxd),
4282 SH_PFC_PIN_GROUP(msiof1_clk_a),
4283 SH_PFC_PIN_GROUP(msiof1_sync_a),
4284 SH_PFC_PIN_GROUP(msiof1_ss1_a),
4285 SH_PFC_PIN_GROUP(msiof1_ss2_a),
4286 SH_PFC_PIN_GROUP(msiof1_txd_a),
4287 SH_PFC_PIN_GROUP(msiof1_rxd_a),
4288 SH_PFC_PIN_GROUP(msiof1_clk_b),
4289 SH_PFC_PIN_GROUP(msiof1_sync_b),
4290 SH_PFC_PIN_GROUP(msiof1_ss1_b),
4291 SH_PFC_PIN_GROUP(msiof1_ss2_b),
4292 SH_PFC_PIN_GROUP(msiof1_txd_b),
4293 SH_PFC_PIN_GROUP(msiof1_rxd_b),
4294 SH_PFC_PIN_GROUP(msiof1_clk_c),
4295 SH_PFC_PIN_GROUP(msiof1_sync_c),
4296 SH_PFC_PIN_GROUP(msiof1_ss1_c),
4297 SH_PFC_PIN_GROUP(msiof1_ss2_c),
4298 SH_PFC_PIN_GROUP(msiof1_txd_c),
4299 SH_PFC_PIN_GROUP(msiof1_rxd_c),
4300 SH_PFC_PIN_GROUP(msiof1_clk_d),
4301 SH_PFC_PIN_GROUP(msiof1_sync_d),
4302 SH_PFC_PIN_GROUP(msiof1_ss1_d),
4303 SH_PFC_PIN_GROUP(msiof1_ss2_d),
4304 SH_PFC_PIN_GROUP(msiof1_txd_d),
4305 SH_PFC_PIN_GROUP(msiof1_rxd_d),
4306 SH_PFC_PIN_GROUP(msiof1_clk_e),
4307 SH_PFC_PIN_GROUP(msiof1_sync_e),
4308 SH_PFC_PIN_GROUP(msiof1_ss1_e),
4309 SH_PFC_PIN_GROUP(msiof1_ss2_e),
4310 SH_PFC_PIN_GROUP(msiof1_txd_e),
4311 SH_PFC_PIN_GROUP(msiof1_rxd_e),
4312 SH_PFC_PIN_GROUP(msiof1_clk_f),
4313 SH_PFC_PIN_GROUP(msiof1_sync_f),
4314 SH_PFC_PIN_GROUP(msiof1_ss1_f),
4315 SH_PFC_PIN_GROUP(msiof1_ss2_f),
4316 SH_PFC_PIN_GROUP(msiof1_txd_f),
4317 SH_PFC_PIN_GROUP(msiof1_rxd_f),
4318 SH_PFC_PIN_GROUP(msiof1_clk_g),
4319 SH_PFC_PIN_GROUP(msiof1_sync_g),
4320 SH_PFC_PIN_GROUP(msiof1_ss1_g),
4321 SH_PFC_PIN_GROUP(msiof1_ss2_g),
4322 SH_PFC_PIN_GROUP(msiof1_txd_g),
4323 SH_PFC_PIN_GROUP(msiof1_rxd_g),
4324 SH_PFC_PIN_GROUP(msiof2_clk_a),
4325 SH_PFC_PIN_GROUP(msiof2_sync_a),
4326 SH_PFC_PIN_GROUP(msiof2_ss1_a),
4327 SH_PFC_PIN_GROUP(msiof2_ss2_a),
4328 SH_PFC_PIN_GROUP(msiof2_txd_a),
4329 SH_PFC_PIN_GROUP(msiof2_rxd_a),
4330 SH_PFC_PIN_GROUP(msiof2_clk_b),
4331 SH_PFC_PIN_GROUP(msiof2_sync_b),
4332 SH_PFC_PIN_GROUP(msiof2_ss1_b),
4333 SH_PFC_PIN_GROUP(msiof2_ss2_b),
4334 SH_PFC_PIN_GROUP(msiof2_txd_b),
4335 SH_PFC_PIN_GROUP(msiof2_rxd_b),
4336 SH_PFC_PIN_GROUP(msiof2_clk_c),
4337 SH_PFC_PIN_GROUP(msiof2_sync_c),
4338 SH_PFC_PIN_GROUP(msiof2_ss1_c),
4339 SH_PFC_PIN_GROUP(msiof2_ss2_c),
4340 SH_PFC_PIN_GROUP(msiof2_txd_c),
4341 SH_PFC_PIN_GROUP(msiof2_rxd_c),
4342 SH_PFC_PIN_GROUP(msiof2_clk_d),
4343 SH_PFC_PIN_GROUP(msiof2_sync_d),
4344 SH_PFC_PIN_GROUP(msiof2_ss1_d),
4345 SH_PFC_PIN_GROUP(msiof2_ss2_d),
4346 SH_PFC_PIN_GROUP(msiof2_txd_d),
4347 SH_PFC_PIN_GROUP(msiof2_rxd_d),
4348 SH_PFC_PIN_GROUP(msiof3_clk_a),
4349 SH_PFC_PIN_GROUP(msiof3_sync_a),
4350 SH_PFC_PIN_GROUP(msiof3_ss1_a),
4351 SH_PFC_PIN_GROUP(msiof3_ss2_a),
4352 SH_PFC_PIN_GROUP(msiof3_txd_a),
4353 SH_PFC_PIN_GROUP(msiof3_rxd_a),
4354 SH_PFC_PIN_GROUP(msiof3_clk_b),
4355 SH_PFC_PIN_GROUP(msiof3_sync_b),
4356 SH_PFC_PIN_GROUP(msiof3_ss1_b),
4357 SH_PFC_PIN_GROUP(msiof3_ss2_b),
4358 SH_PFC_PIN_GROUP(msiof3_txd_b),
4359 SH_PFC_PIN_GROUP(msiof3_rxd_b),
4360 SH_PFC_PIN_GROUP(msiof3_clk_c),
4361 SH_PFC_PIN_GROUP(msiof3_sync_c),
4362 SH_PFC_PIN_GROUP(msiof3_txd_c),
4363 SH_PFC_PIN_GROUP(msiof3_rxd_c),
4364 SH_PFC_PIN_GROUP(msiof3_clk_d),
4365 SH_PFC_PIN_GROUP(msiof3_sync_d),
4366 SH_PFC_PIN_GROUP(msiof3_ss1_d),
4367 SH_PFC_PIN_GROUP(msiof3_txd_d),
4368 SH_PFC_PIN_GROUP(msiof3_rxd_d),
4369 SH_PFC_PIN_GROUP(msiof3_clk_e),
4370 SH_PFC_PIN_GROUP(msiof3_sync_e),
4371 SH_PFC_PIN_GROUP(msiof3_ss1_e),
4372 SH_PFC_PIN_GROUP(msiof3_ss2_e),
4373 SH_PFC_PIN_GROUP(msiof3_txd_e),
4374 SH_PFC_PIN_GROUP(msiof3_rxd_e),
4375 SH_PFC_PIN_GROUP(pwm0),
4376 SH_PFC_PIN_GROUP(pwm1_a),
4377 SH_PFC_PIN_GROUP(pwm1_b),
4378 SH_PFC_PIN_GROUP(pwm2_a),
4379 SH_PFC_PIN_GROUP(pwm2_b),
4380 SH_PFC_PIN_GROUP(pwm3_a),
4381 SH_PFC_PIN_GROUP(pwm3_b),
4382 SH_PFC_PIN_GROUP(pwm4_a),
4383 SH_PFC_PIN_GROUP(pwm4_b),
4384 SH_PFC_PIN_GROUP(pwm5_a),
4385 SH_PFC_PIN_GROUP(pwm5_b),
4386 SH_PFC_PIN_GROUP(pwm6_a),
4387 SH_PFC_PIN_GROUP(pwm6_b),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]4388 SH_PFC_PIN_GROUP(sata0_devslp_a),
4389 SH_PFC_PIN_GROUP(sata0_devslp_b),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]4390 SH_PFC_PIN_GROUP(scif0_data),
4391 SH_PFC_PIN_GROUP(scif0_clk),
4392 SH_PFC_PIN_GROUP(scif0_ctrl),
4393 SH_PFC_PIN_GROUP(scif1_data_a),
4394 SH_PFC_PIN_GROUP(scif1_clk),
4395 SH_PFC_PIN_GROUP(scif1_ctrl),
4396 SH_PFC_PIN_GROUP(scif1_data_b),
4397 SH_PFC_PIN_GROUP(scif2_data_a),
4398 SH_PFC_PIN_GROUP(scif2_clk),
4399 SH_PFC_PIN_GROUP(scif2_data_b),
4400 SH_PFC_PIN_GROUP(scif3_data_a),
4401 SH_PFC_PIN_GROUP(scif3_clk),
4402 SH_PFC_PIN_GROUP(scif3_ctrl),
4403 SH_PFC_PIN_GROUP(scif3_data_b),
4404 SH_PFC_PIN_GROUP(scif4_data_a),
4405 SH_PFC_PIN_GROUP(scif4_clk_a),
4406 SH_PFC_PIN_GROUP(scif4_ctrl_a),
4407 SH_PFC_PIN_GROUP(scif4_data_b),
4408 SH_PFC_PIN_GROUP(scif4_clk_b),
4409 SH_PFC_PIN_GROUP(scif4_ctrl_b),
4410 SH_PFC_PIN_GROUP(scif4_data_c),
4411 SH_PFC_PIN_GROUP(scif4_clk_c),
4412 SH_PFC_PIN_GROUP(scif4_ctrl_c),
4413 SH_PFC_PIN_GROUP(scif5_data_a),
4414 SH_PFC_PIN_GROUP(scif5_clk_a),
4415 SH_PFC_PIN_GROUP(scif5_data_b),
4416 SH_PFC_PIN_GROUP(scif5_clk_b),
4417 SH_PFC_PIN_GROUP(scif_clk_a),
4418 SH_PFC_PIN_GROUP(scif_clk_b),
4419 SH_PFC_PIN_GROUP(sdhi0_data1),
4420 SH_PFC_PIN_GROUP(sdhi0_data4),
4421 SH_PFC_PIN_GROUP(sdhi0_ctrl),
4422 SH_PFC_PIN_GROUP(sdhi0_cd),
4423 SH_PFC_PIN_GROUP(sdhi0_wp),
4424 SH_PFC_PIN_GROUP(sdhi1_data1),
4425 SH_PFC_PIN_GROUP(sdhi1_data4),
4426 SH_PFC_PIN_GROUP(sdhi1_ctrl),
4427 SH_PFC_PIN_GROUP(sdhi1_cd),
4428 SH_PFC_PIN_GROUP(sdhi1_wp),
4429 SH_PFC_PIN_GROUP(sdhi2_data1),
4430 SH_PFC_PIN_GROUP(sdhi2_data4),
4431 SH_PFC_PIN_GROUP(sdhi2_data8),
4432 SH_PFC_PIN_GROUP(sdhi2_ctrl),
4433 SH_PFC_PIN_GROUP(sdhi2_cd_a),
4434 SH_PFC_PIN_GROUP(sdhi2_wp_a),
4435 SH_PFC_PIN_GROUP(sdhi2_cd_b),
4436 SH_PFC_PIN_GROUP(sdhi2_wp_b),
4437 SH_PFC_PIN_GROUP(sdhi2_ds),
4438 SH_PFC_PIN_GROUP(sdhi3_data1),
4439 SH_PFC_PIN_GROUP(sdhi3_data4),
4440 SH_PFC_PIN_GROUP(sdhi3_data8),
4441 SH_PFC_PIN_GROUP(sdhi3_ctrl),
4442 SH_PFC_PIN_GROUP(sdhi3_cd),
4443 SH_PFC_PIN_GROUP(sdhi3_wp),
4444 SH_PFC_PIN_GROUP(sdhi3_ds),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]4445 SH_PFC_PIN_GROUP(ssi0_data),
4446 SH_PFC_PIN_GROUP(ssi01239_ctrl),
4447 SH_PFC_PIN_GROUP(ssi1_data_a),
4448 SH_PFC_PIN_GROUP(ssi1_data_b),
4449 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
4450 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
4451 SH_PFC_PIN_GROUP(ssi2_data_a),
4452 SH_PFC_PIN_GROUP(ssi2_data_b),
4453 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
4454 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
4455 SH_PFC_PIN_GROUP(ssi3_data),
4456 SH_PFC_PIN_GROUP(ssi349_ctrl),
4457 SH_PFC_PIN_GROUP(ssi4_data),
4458 SH_PFC_PIN_GROUP(ssi4_ctrl),
4459 SH_PFC_PIN_GROUP(ssi5_data),
4460 SH_PFC_PIN_GROUP(ssi5_ctrl),
4461 SH_PFC_PIN_GROUP(ssi6_data),
4462 SH_PFC_PIN_GROUP(ssi6_ctrl),
4463 SH_PFC_PIN_GROUP(ssi7_data),
4464 SH_PFC_PIN_GROUP(ssi78_ctrl),
4465 SH_PFC_PIN_GROUP(ssi8_data),
4466 SH_PFC_PIN_GROUP(ssi9_data_a),
4467 SH_PFC_PIN_GROUP(ssi9_data_b),
4468 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
4469 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
4470 SH_PFC_PIN_GROUP(tmu_tclk1_a),
4471 SH_PFC_PIN_GROUP(tmu_tclk1_b),
4472 SH_PFC_PIN_GROUP(tmu_tclk2_a),
4473 SH_PFC_PIN_GROUP(tmu_tclk2_b),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]4474 SH_PFC_PIN_GROUP(usb0),
4475 SH_PFC_PIN_GROUP(usb1),
4476 SH_PFC_PIN_GROUP(usb2),
4477 SH_PFC_PIN_GROUP(usb2_ch3),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]4478 SH_PFC_PIN_GROUP(usb30),
4479 VIN_DATA_PIN_GROUP(vin4_data_a, 8),
4480 VIN_DATA_PIN_GROUP(vin4_data_a, 10),
4481 VIN_DATA_PIN_GROUP(vin4_data_a, 12),
4482 VIN_DATA_PIN_GROUP(vin4_data_a, 16),
4483 SH_PFC_PIN_GROUP(vin4_data18_a),
4484 VIN_DATA_PIN_GROUP(vin4_data_a, 20),
4485 VIN_DATA_PIN_GROUP(vin4_data_a, 24),
4486 VIN_DATA_PIN_GROUP(vin4_data_b, 8),
4487 VIN_DATA_PIN_GROUP(vin4_data_b, 10),
4488 VIN_DATA_PIN_GROUP(vin4_data_b, 12),
4489 VIN_DATA_PIN_GROUP(vin4_data_b, 16),
4490 SH_PFC_PIN_GROUP(vin4_data18_b),
4491 VIN_DATA_PIN_GROUP(vin4_data_b, 20),
4492 VIN_DATA_PIN_GROUP(vin4_data_b, 24),
4493 SH_PFC_PIN_GROUP(vin4_sync),
4494 SH_PFC_PIN_GROUP(vin4_field),
4495 SH_PFC_PIN_GROUP(vin4_clkenb),
4496 SH_PFC_PIN_GROUP(vin4_clk),
4497 SH_PFC_PIN_GROUP(vin5_data8),
4498 SH_PFC_PIN_GROUP(vin5_data10),
4499 SH_PFC_PIN_GROUP(vin5_data12),
4500 SH_PFC_PIN_GROUP(vin5_data16),
4501 SH_PFC_PIN_GROUP(vin5_sync),
4502 SH_PFC_PIN_GROUP(vin5_field),
4503 SH_PFC_PIN_GROUP(vin5_clkenb),
4504 SH_PFC_PIN_GROUP(vin5_clk),
4505};
4506
4507static const char * const audio_clk_groups[] = {
4508 "audio_clk_a_a",
4509 "audio_clk_a_b",
4510 "audio_clk_a_c",
4511 "audio_clk_b_a",
4512 "audio_clk_b_b",
4513 "audio_clk_c_a",
4514 "audio_clk_c_b",
4515 "audio_clkout_a",
4516 "audio_clkout_b",
4517 "audio_clkout_c",
4518 "audio_clkout_d",
4519 "audio_clkout1_a",
4520 "audio_clkout1_b",
4521 "audio_clkout2_a",
4522 "audio_clkout2_b",
4523 "audio_clkout3_a",
4524 "audio_clkout3_b",
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]4525};
4526
4527static const char * const avb_groups[] = {
4528 "avb_link",
4529 "avb_magic",
4530 "avb_phy_int",
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]4531 "avb_mdc", /* Deprecated, please use "avb_mdio" instead */
4532 "avb_mdio",
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]4533 "avb_mii",
4534 "avb_avtp_pps",
4535 "avb_avtp_match_a",
4536 "avb_avtp_capture_a",
4537 "avb_avtp_match_b",
4538 "avb_avtp_capture_b",
4539};
4540
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]4541static const char * const can0_groups[] = {
4542 "can0_data_a",
4543 "can0_data_b",
4544};
4545
4546static const char * const can1_groups[] = {
4547 "can1_data",
4548};
4549
4550static const char * const can_clk_groups[] = {
4551 "can_clk",
4552};
4553
4554static const char * const canfd0_groups[] = {
4555 "canfd0_data_a",
4556 "canfd0_data_b",
4557};
4558
4559static const char * const canfd1_groups[] = {
4560 "canfd1_data",
4561};
4562
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]4563static const char * const drif0_groups[] = {
4564 "drif0_ctrl_a",
4565 "drif0_data0_a",
4566 "drif0_data1_a",
4567 "drif0_ctrl_b",
4568 "drif0_data0_b",
4569 "drif0_data1_b",
4570 "drif0_ctrl_c",
4571 "drif0_data0_c",
4572 "drif0_data1_c",
4573};
4574
4575static const char * const drif1_groups[] = {
4576 "drif1_ctrl_a",
4577 "drif1_data0_a",
4578 "drif1_data1_a",
4579 "drif1_ctrl_b",
4580 "drif1_data0_b",
4581 "drif1_data1_b",
4582 "drif1_ctrl_c",
4583 "drif1_data0_c",
4584 "drif1_data1_c",
4585};
4586
4587static const char * const drif2_groups[] = {
4588 "drif2_ctrl_a",
4589 "drif2_data0_a",
4590 "drif2_data1_a",
4591 "drif2_ctrl_b",
4592 "drif2_data0_b",
4593 "drif2_data1_b",
4594};
4595
4596static const char * const drif3_groups[] = {
4597 "drif3_ctrl_a",
4598 "drif3_data0_a",
4599 "drif3_data1_a",
4600 "drif3_ctrl_b",
4601 "drif3_data0_b",
4602 "drif3_data1_b",
4603};
4604
4605static const char * const du_groups[] = {
4606 "du_rgb666",
4607 "du_rgb888",
4608 "du_clk_out_0",
4609 "du_clk_out_1",
4610 "du_sync",
4611 "du_oddf",
4612 "du_cde",
4613 "du_disp",
4614};
4615
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]4616static const char * const hdmi0_groups[] = {
4617 "hdmi0_cec",
4618};
4619
4620static const char * const hdmi1_groups[] = {
4621 "hdmi1_cec",
4622};
4623
4624static const char * const hscif0_groups[] = {
4625 "hscif0_data",
4626 "hscif0_clk",
4627 "hscif0_ctrl",
4628};
4629
4630static const char * const hscif1_groups[] = {
4631 "hscif1_data_a",
4632 "hscif1_clk_a",
4633 "hscif1_ctrl_a",
4634 "hscif1_data_b",
4635 "hscif1_clk_b",
4636 "hscif1_ctrl_b",
4637};
4638
4639static const char * const hscif2_groups[] = {
4640 "hscif2_data_a",
4641 "hscif2_clk_a",
4642 "hscif2_ctrl_a",
4643 "hscif2_data_b",
4644 "hscif2_clk_b",
4645 "hscif2_ctrl_b",
4646 "hscif2_data_c",
4647 "hscif2_clk_c",
4648 "hscif2_ctrl_c",
4649};
4650
4651static const char * const hscif3_groups[] = {
4652 "hscif3_data_a",
4653 "hscif3_clk",
4654 "hscif3_ctrl",
4655 "hscif3_data_b",
4656 "hscif3_data_c",
4657 "hscif3_data_d",
4658};
4659
4660static const char * const hscif4_groups[] = {
4661 "hscif4_data_a",
4662 "hscif4_clk",
4663 "hscif4_ctrl",
4664 "hscif4_data_b",
4665};
4666
4667static const char * const i2c1_groups[] = {
4668 "i2c1_a",
4669 "i2c1_b",
4670};
4671
4672static const char * const i2c2_groups[] = {
4673 "i2c2_a",
4674 "i2c2_b",
4675};
4676
4677static const char * const i2c6_groups[] = {
4678 "i2c6_a",
4679 "i2c6_b",
4680 "i2c6_c",
4681};
4682
4683static const char * const intc_ex_groups[] = {
4684 "intc_ex_irq0",
4685 "intc_ex_irq1",
4686 "intc_ex_irq2",
4687 "intc_ex_irq3",
4688 "intc_ex_irq4",
4689 "intc_ex_irq5",
4690};
4691
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]4692static const char * const msiof0_groups[] = {
4693 "msiof0_clk",
4694 "msiof0_sync",
4695 "msiof0_ss1",
4696 "msiof0_ss2",
4697 "msiof0_txd",
4698 "msiof0_rxd",
4699};
4700
4701static const char * const msiof1_groups[] = {
4702 "msiof1_clk_a",
4703 "msiof1_sync_a",
4704 "msiof1_ss1_a",
4705 "msiof1_ss2_a",
4706 "msiof1_txd_a",
4707 "msiof1_rxd_a",
4708 "msiof1_clk_b",
4709 "msiof1_sync_b",
4710 "msiof1_ss1_b",
4711 "msiof1_ss2_b",
4712 "msiof1_txd_b",
4713 "msiof1_rxd_b",
4714 "msiof1_clk_c",
4715 "msiof1_sync_c",
4716 "msiof1_ss1_c",
4717 "msiof1_ss2_c",
4718 "msiof1_txd_c",
4719 "msiof1_rxd_c",
4720 "msiof1_clk_d",
4721 "msiof1_sync_d",
4722 "msiof1_ss1_d",
4723 "msiof1_ss2_d",
4724 "msiof1_txd_d",
4725 "msiof1_rxd_d",
4726 "msiof1_clk_e",
4727 "msiof1_sync_e",
4728 "msiof1_ss1_e",
4729 "msiof1_ss2_e",
4730 "msiof1_txd_e",
4731 "msiof1_rxd_e",
4732 "msiof1_clk_f",
4733 "msiof1_sync_f",
4734 "msiof1_ss1_f",
4735 "msiof1_ss2_f",
4736 "msiof1_txd_f",
4737 "msiof1_rxd_f",
4738 "msiof1_clk_g",
4739 "msiof1_sync_g",
4740 "msiof1_ss1_g",
4741 "msiof1_ss2_g",
4742 "msiof1_txd_g",
4743 "msiof1_rxd_g",
4744};
4745
4746static const char * const msiof2_groups[] = {
4747 "msiof2_clk_a",
4748 "msiof2_sync_a",
4749 "msiof2_ss1_a",
4750 "msiof2_ss2_a",
4751 "msiof2_txd_a",
4752 "msiof2_rxd_a",
4753 "msiof2_clk_b",
4754 "msiof2_sync_b",
4755 "msiof2_ss1_b",
4756 "msiof2_ss2_b",
4757 "msiof2_txd_b",
4758 "msiof2_rxd_b",
4759 "msiof2_clk_c",
4760 "msiof2_sync_c",
4761 "msiof2_ss1_c",
4762 "msiof2_ss2_c",
4763 "msiof2_txd_c",
4764 "msiof2_rxd_c",
4765 "msiof2_clk_d",
4766 "msiof2_sync_d",
4767 "msiof2_ss1_d",
4768 "msiof2_ss2_d",
4769 "msiof2_txd_d",
4770 "msiof2_rxd_d",
4771};
4772
4773static const char * const msiof3_groups[] = {
4774 "msiof3_clk_a",
4775 "msiof3_sync_a",
4776 "msiof3_ss1_a",
4777 "msiof3_ss2_a",
4778 "msiof3_txd_a",
4779 "msiof3_rxd_a",
4780 "msiof3_clk_b",
4781 "msiof3_sync_b",
4782 "msiof3_ss1_b",
4783 "msiof3_ss2_b",
4784 "msiof3_txd_b",
4785 "msiof3_rxd_b",
4786 "msiof3_clk_c",
4787 "msiof3_sync_c",
4788 "msiof3_txd_c",
4789 "msiof3_rxd_c",
4790 "msiof3_clk_d",
4791 "msiof3_sync_d",
4792 "msiof3_ss1_d",
4793 "msiof3_txd_d",
4794 "msiof3_rxd_d",
4795 "msiof3_clk_e",
4796 "msiof3_sync_e",
4797 "msiof3_ss1_e",
4798 "msiof3_ss2_e",
4799 "msiof3_txd_e",
4800 "msiof3_rxd_e",
4801};
4802
4803static const char * const pwm0_groups[] = {
4804 "pwm0",
4805};
4806
4807static const char * const pwm1_groups[] = {
4808 "pwm1_a",
4809 "pwm1_b",
4810};
4811
4812static const char * const pwm2_groups[] = {
4813 "pwm2_a",
4814 "pwm2_b",
4815};
4816
4817static const char * const pwm3_groups[] = {
4818 "pwm3_a",
4819 "pwm3_b",
4820};
4821
4822static const char * const pwm4_groups[] = {
4823 "pwm4_a",
4824 "pwm4_b",
4825};
4826
4827static const char * const pwm5_groups[] = {
4828 "pwm5_a",
4829 "pwm5_b",
4830};
4831
4832static const char * const pwm6_groups[] = {
4833 "pwm6_a",
4834 "pwm6_b",
4835};
4836
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]4837static const char * const sata0_groups[] = {
4838 "sata0_devslp_a",
4839 "sata0_devslp_b",
4840};
4841
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]4842static const char * const scif0_groups[] = {
4843 "scif0_data",
4844 "scif0_clk",
4845 "scif0_ctrl",
4846};
4847
4848static const char * const scif1_groups[] = {
4849 "scif1_data_a",
4850 "scif1_clk",
4851 "scif1_ctrl",
4852 "scif1_data_b",
4853};
4854
4855static const char * const scif2_groups[] = {
4856 "scif2_data_a",
4857 "scif2_clk",
4858 "scif2_data_b",
4859};
4860
4861static const char * const scif3_groups[] = {
4862 "scif3_data_a",
4863 "scif3_clk",
4864 "scif3_ctrl",
4865 "scif3_data_b",
4866};
4867
4868static const char * const scif4_groups[] = {
4869 "scif4_data_a",
4870 "scif4_clk_a",
4871 "scif4_ctrl_a",
4872 "scif4_data_b",
4873 "scif4_clk_b",
4874 "scif4_ctrl_b",
4875 "scif4_data_c",
4876 "scif4_clk_c",
4877 "scif4_ctrl_c",
4878};
4879
4880static const char * const scif5_groups[] = {
4881 "scif5_data_a",
4882 "scif5_clk_a",
4883 "scif5_data_b",
4884 "scif5_clk_b",
4885};
4886
4887static const char * const scif_clk_groups[] = {
4888 "scif_clk_a",
4889 "scif_clk_b",
4890};
4891
4892static const char * const sdhi0_groups[] = {
4893 "sdhi0_data1",
4894 "sdhi0_data4",
4895 "sdhi0_ctrl",
4896 "sdhi0_cd",
4897 "sdhi0_wp",
4898};
4899
4900static const char * const sdhi1_groups[] = {
4901 "sdhi1_data1",
4902 "sdhi1_data4",
4903 "sdhi1_ctrl",
4904 "sdhi1_cd",
4905 "sdhi1_wp",
4906};
4907
4908static const char * const sdhi2_groups[] = {
4909 "sdhi2_data1",
4910 "sdhi2_data4",
4911 "sdhi2_data8",
4912 "sdhi2_ctrl",
4913 "sdhi2_cd_a",
4914 "sdhi2_wp_a",
4915 "sdhi2_cd_b",
4916 "sdhi2_wp_b",
4917 "sdhi2_ds",
4918};
4919
4920static const char * const sdhi3_groups[] = {
4921 "sdhi3_data1",
4922 "sdhi3_data4",
4923 "sdhi3_data8",
4924 "sdhi3_ctrl",
4925 "sdhi3_cd",
4926 "sdhi3_wp",
4927 "sdhi3_ds",
4928};
4929
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]4930static const char * const ssi_groups[] = {
4931 "ssi0_data",
4932 "ssi01239_ctrl",
4933 "ssi1_data_a",
4934 "ssi1_data_b",
4935 "ssi1_ctrl_a",
4936 "ssi1_ctrl_b",
4937 "ssi2_data_a",
4938 "ssi2_data_b",
4939 "ssi2_ctrl_a",
4940 "ssi2_ctrl_b",
4941 "ssi3_data",
4942 "ssi349_ctrl",
4943 "ssi4_data",
4944 "ssi4_ctrl",
4945 "ssi5_data",
4946 "ssi5_ctrl",
4947 "ssi6_data",
4948 "ssi6_ctrl",
4949 "ssi7_data",
4950 "ssi78_ctrl",
4951 "ssi8_data",
4952 "ssi9_data_a",
4953 "ssi9_data_b",
4954 "ssi9_ctrl_a",
4955 "ssi9_ctrl_b",
4956};
4957
4958static const char * const tmu_groups[] = {
4959 "tmu_tclk1_a",
4960 "tmu_tclk1_b",
4961 "tmu_tclk2_a",
4962 "tmu_tclk2_b",
4963};
4964
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]4965static const char * const usb0_groups[] = {
4966 "usb0",
4967};
4968
4969static const char * const usb1_groups[] = {
4970 "usb1",
4971};
4972
4973static const char * const usb2_groups[] = {
4974 "usb2",
4975};
4976
4977static const char * const usb2_ch3_groups[] = {
4978 "usb2_ch3",
4979};
4980
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]4981static const char * const usb30_groups[] = {
4982 "usb30",
4983};
4984
4985static const char * const vin4_groups[] = {
4986 "vin4_data8_a",
4987 "vin4_data10_a",
4988 "vin4_data12_a",
4989 "vin4_data16_a",
4990 "vin4_data18_a",
4991 "vin4_data20_a",
4992 "vin4_data24_a",
4993 "vin4_data8_b",
4994 "vin4_data10_b",
4995 "vin4_data12_b",
4996 "vin4_data16_b",
4997 "vin4_data18_b",
4998 "vin4_data20_b",
4999 "vin4_data24_b",
5000 "vin4_sync",
5001 "vin4_field",
5002 "vin4_clkenb",
5003 "vin4_clk",
5004};
5005
5006static const char * const vin5_groups[] = {
5007 "vin5_data8",
5008 "vin5_data10",
5009 "vin5_data12",
5010 "vin5_data16",
5011 "vin5_sync",
5012 "vin5_field",
5013 "vin5_clkenb",
5014 "vin5_clk",
5015};
5016
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]5017static const struct sh_pfc_function pinmux_functions[] = {
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]5018 SH_PFC_FUNCTION(audio_clk),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]5019 SH_PFC_FUNCTION(avb),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]5020 SH_PFC_FUNCTION(can0),
5021 SH_PFC_FUNCTION(can1),
5022 SH_PFC_FUNCTION(can_clk),
5023 SH_PFC_FUNCTION(canfd0),
5024 SH_PFC_FUNCTION(canfd1),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]5025 SH_PFC_FUNCTION(drif0),
5026 SH_PFC_FUNCTION(drif1),
5027 SH_PFC_FUNCTION(drif2),
5028 SH_PFC_FUNCTION(drif3),
5029 SH_PFC_FUNCTION(du),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]5030 SH_PFC_FUNCTION(hdmi0),
5031 SH_PFC_FUNCTION(hdmi1),
5032 SH_PFC_FUNCTION(hscif0),
5033 SH_PFC_FUNCTION(hscif1),
5034 SH_PFC_FUNCTION(hscif2),
5035 SH_PFC_FUNCTION(hscif3),
5036 SH_PFC_FUNCTION(hscif4),
5037 SH_PFC_FUNCTION(i2c1),
5038 SH_PFC_FUNCTION(i2c2),
5039 SH_PFC_FUNCTION(i2c6),
5040 SH_PFC_FUNCTION(intc_ex),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]5041 SH_PFC_FUNCTION(msiof0),
5042 SH_PFC_FUNCTION(msiof1),
5043 SH_PFC_FUNCTION(msiof2),
5044 SH_PFC_FUNCTION(msiof3),
5045 SH_PFC_FUNCTION(pwm0),
5046 SH_PFC_FUNCTION(pwm1),
5047 SH_PFC_FUNCTION(pwm2),
5048 SH_PFC_FUNCTION(pwm3),
5049 SH_PFC_FUNCTION(pwm4),
5050 SH_PFC_FUNCTION(pwm5),
5051 SH_PFC_FUNCTION(pwm6),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]5052 SH_PFC_FUNCTION(sata0),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]5053 SH_PFC_FUNCTION(scif0),
5054 SH_PFC_FUNCTION(scif1),
5055 SH_PFC_FUNCTION(scif2),
5056 SH_PFC_FUNCTION(scif3),
5057 SH_PFC_FUNCTION(scif4),
5058 SH_PFC_FUNCTION(scif5),
5059 SH_PFC_FUNCTION(scif_clk),
5060 SH_PFC_FUNCTION(sdhi0),
5061 SH_PFC_FUNCTION(sdhi1),
5062 SH_PFC_FUNCTION(sdhi2),
5063 SH_PFC_FUNCTION(sdhi3),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]5064 SH_PFC_FUNCTION(ssi),
5065 SH_PFC_FUNCTION(tmu),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]5066 SH_PFC_FUNCTION(usb0),
5067 SH_PFC_FUNCTION(usb1),
5068 SH_PFC_FUNCTION(usb2),
5069 SH_PFC_FUNCTION(usb2_ch3),
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]5070 SH_PFC_FUNCTION(usb30),
5071 SH_PFC_FUNCTION(vin4),
5072 SH_PFC_FUNCTION(vin5),
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]5073};
5074
5075static const struct pinmux_cfg_reg pinmux_config_regs[] = {
5076#define F_(x, y) FN_##y
5077#define FM(x) FN_##x
5078 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
5079 0, 0,
5080 0, 0,
5081 0, 0,
5082 0, 0,
5083 0, 0,
5084 0, 0,
5085 0, 0,
5086 0, 0,
5087 0, 0,
5088 0, 0,
5089 0, 0,
5090 0, 0,
5091 0, 0,
5092 0, 0,
5093 0, 0,
5094 0, 0,
5095 GP_0_15_FN, GPSR0_15,
5096 GP_0_14_FN, GPSR0_14,
5097 GP_0_13_FN, GPSR0_13,
5098 GP_0_12_FN, GPSR0_12,
5099 GP_0_11_FN, GPSR0_11,
5100 GP_0_10_FN, GPSR0_10,
5101 GP_0_9_FN, GPSR0_9,
5102 GP_0_8_FN, GPSR0_8,
5103 GP_0_7_FN, GPSR0_7,
5104 GP_0_6_FN, GPSR0_6,
5105 GP_0_5_FN, GPSR0_5,
5106 GP_0_4_FN, GPSR0_4,
5107 GP_0_3_FN, GPSR0_3,
5108 GP_0_2_FN, GPSR0_2,
5109 GP_0_1_FN, GPSR0_1,
5110 GP_0_0_FN, GPSR0_0, }
5111 },
5112 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
5113 0, 0,
5114 0, 0,
5115 0, 0,
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]5116 GP_1_28_FN, GPSR1_28,
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]5117 GP_1_27_FN, GPSR1_27,
5118 GP_1_26_FN, GPSR1_26,
5119 GP_1_25_FN, GPSR1_25,
5120 GP_1_24_FN, GPSR1_24,
5121 GP_1_23_FN, GPSR1_23,
5122 GP_1_22_FN, GPSR1_22,
5123 GP_1_21_FN, GPSR1_21,
5124 GP_1_20_FN, GPSR1_20,
5125 GP_1_19_FN, GPSR1_19,
5126 GP_1_18_FN, GPSR1_18,
5127 GP_1_17_FN, GPSR1_17,
5128 GP_1_16_FN, GPSR1_16,
5129 GP_1_15_FN, GPSR1_15,
5130 GP_1_14_FN, GPSR1_14,
5131 GP_1_13_FN, GPSR1_13,
5132 GP_1_12_FN, GPSR1_12,
5133 GP_1_11_FN, GPSR1_11,
5134 GP_1_10_FN, GPSR1_10,
5135 GP_1_9_FN, GPSR1_9,
5136 GP_1_8_FN, GPSR1_8,
5137 GP_1_7_FN, GPSR1_7,
5138 GP_1_6_FN, GPSR1_6,
5139 GP_1_5_FN, GPSR1_5,
5140 GP_1_4_FN, GPSR1_4,
5141 GP_1_3_FN, GPSR1_3,
5142 GP_1_2_FN, GPSR1_2,
5143 GP_1_1_FN, GPSR1_1,
5144 GP_1_0_FN, GPSR1_0, }
5145 },
5146 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
5147 0, 0,
5148 0, 0,
5149 0, 0,
5150 0, 0,
5151 0, 0,
5152 0, 0,
5153 0, 0,
5154 0, 0,
5155 0, 0,
5156 0, 0,
5157 0, 0,
5158 0, 0,
5159 0, 0,
5160 0, 0,
5161 0, 0,
5162 0, 0,
5163 0, 0,
5164 GP_2_14_FN, GPSR2_14,
5165 GP_2_13_FN, GPSR2_13,
5166 GP_2_12_FN, GPSR2_12,
5167 GP_2_11_FN, GPSR2_11,
5168 GP_2_10_FN, GPSR2_10,
5169 GP_2_9_FN, GPSR2_9,
5170 GP_2_8_FN, GPSR2_8,
5171 GP_2_7_FN, GPSR2_7,
5172 GP_2_6_FN, GPSR2_6,
5173 GP_2_5_FN, GPSR2_5,
5174 GP_2_4_FN, GPSR2_4,
5175 GP_2_3_FN, GPSR2_3,
5176 GP_2_2_FN, GPSR2_2,
5177 GP_2_1_FN, GPSR2_1,
5178 GP_2_0_FN, GPSR2_0, }
5179 },
5180 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
5181 0, 0,
5182 0, 0,
5183 0, 0,
5184 0, 0,
5185 0, 0,
5186 0, 0,
5187 0, 0,
5188 0, 0,
5189 0, 0,
5190 0, 0,
5191 0, 0,
5192 0, 0,
5193 0, 0,
5194 0, 0,
5195 0, 0,
5196 0, 0,
5197 GP_3_15_FN, GPSR3_15,
5198 GP_3_14_FN, GPSR3_14,
5199 GP_3_13_FN, GPSR3_13,
5200 GP_3_12_FN, GPSR3_12,
5201 GP_3_11_FN, GPSR3_11,
5202 GP_3_10_FN, GPSR3_10,
5203 GP_3_9_FN, GPSR3_9,
5204 GP_3_8_FN, GPSR3_8,
5205 GP_3_7_FN, GPSR3_7,
5206 GP_3_6_FN, GPSR3_6,
5207 GP_3_5_FN, GPSR3_5,
5208 GP_3_4_FN, GPSR3_4,
5209 GP_3_3_FN, GPSR3_3,
5210 GP_3_2_FN, GPSR3_2,
5211 GP_3_1_FN, GPSR3_1,
5212 GP_3_0_FN, GPSR3_0, }
5213 },
5214 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
5215 0, 0,
5216 0, 0,
5217 0, 0,
5218 0, 0,
5219 0, 0,
5220 0, 0,
5221 0, 0,
5222 0, 0,
5223 0, 0,
5224 0, 0,
5225 0, 0,
5226 0, 0,
5227 0, 0,
5228 0, 0,
5229 GP_4_17_FN, GPSR4_17,
5230 GP_4_16_FN, GPSR4_16,
5231 GP_4_15_FN, GPSR4_15,
5232 GP_4_14_FN, GPSR4_14,
5233 GP_4_13_FN, GPSR4_13,
5234 GP_4_12_FN, GPSR4_12,
5235 GP_4_11_FN, GPSR4_11,
5236 GP_4_10_FN, GPSR4_10,
5237 GP_4_9_FN, GPSR4_9,
5238 GP_4_8_FN, GPSR4_8,
5239 GP_4_7_FN, GPSR4_7,
5240 GP_4_6_FN, GPSR4_6,
5241 GP_4_5_FN, GPSR4_5,
5242 GP_4_4_FN, GPSR4_4,
5243 GP_4_3_FN, GPSR4_3,
5244 GP_4_2_FN, GPSR4_2,
5245 GP_4_1_FN, GPSR4_1,
5246 GP_4_0_FN, GPSR4_0, }
5247 },
5248 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
5249 0, 0,
5250 0, 0,
5251 0, 0,
5252 0, 0,
5253 0, 0,
5254 0, 0,
5255 GP_5_25_FN, GPSR5_25,
5256 GP_5_24_FN, GPSR5_24,
5257 GP_5_23_FN, GPSR5_23,
5258 GP_5_22_FN, GPSR5_22,
5259 GP_5_21_FN, GPSR5_21,
5260 GP_5_20_FN, GPSR5_20,
5261 GP_5_19_FN, GPSR5_19,
5262 GP_5_18_FN, GPSR5_18,
5263 GP_5_17_FN, GPSR5_17,
5264 GP_5_16_FN, GPSR5_16,
5265 GP_5_15_FN, GPSR5_15,
5266 GP_5_14_FN, GPSR5_14,
5267 GP_5_13_FN, GPSR5_13,
5268 GP_5_12_FN, GPSR5_12,
5269 GP_5_11_FN, GPSR5_11,
5270 GP_5_10_FN, GPSR5_10,
5271 GP_5_9_FN, GPSR5_9,
5272 GP_5_8_FN, GPSR5_8,
5273 GP_5_7_FN, GPSR5_7,
5274 GP_5_6_FN, GPSR5_6,
5275 GP_5_5_FN, GPSR5_5,
5276 GP_5_4_FN, GPSR5_4,
5277 GP_5_3_FN, GPSR5_3,
5278 GP_5_2_FN, GPSR5_2,
5279 GP_5_1_FN, GPSR5_1,
5280 GP_5_0_FN, GPSR5_0, }
5281 },
5282 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
5283 GP_6_31_FN, GPSR6_31,
5284 GP_6_30_FN, GPSR6_30,
5285 GP_6_29_FN, GPSR6_29,
5286 GP_6_28_FN, GPSR6_28,
5287 GP_6_27_FN, GPSR6_27,
5288 GP_6_26_FN, GPSR6_26,
5289 GP_6_25_FN, GPSR6_25,
5290 GP_6_24_FN, GPSR6_24,
5291 GP_6_23_FN, GPSR6_23,
5292 GP_6_22_FN, GPSR6_22,
5293 GP_6_21_FN, GPSR6_21,
5294 GP_6_20_FN, GPSR6_20,
5295 GP_6_19_FN, GPSR6_19,
5296 GP_6_18_FN, GPSR6_18,
5297 GP_6_17_FN, GPSR6_17,
5298 GP_6_16_FN, GPSR6_16,
5299 GP_6_15_FN, GPSR6_15,
5300 GP_6_14_FN, GPSR6_14,
5301 GP_6_13_FN, GPSR6_13,
5302 GP_6_12_FN, GPSR6_12,
5303 GP_6_11_FN, GPSR6_11,
5304 GP_6_10_FN, GPSR6_10,
5305 GP_6_9_FN, GPSR6_9,
5306 GP_6_8_FN, GPSR6_8,
5307 GP_6_7_FN, GPSR6_7,
5308 GP_6_6_FN, GPSR6_6,
5309 GP_6_5_FN, GPSR6_5,
5310 GP_6_4_FN, GPSR6_4,
5311 GP_6_3_FN, GPSR6_3,
5312 GP_6_2_FN, GPSR6_2,
5313 GP_6_1_FN, GPSR6_1,
5314 GP_6_0_FN, GPSR6_0, }
5315 },
5316 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
5317 0, 0,
5318 0, 0,
5319 0, 0,
5320 0, 0,
5321 0, 0,
5322 0, 0,
5323 0, 0,
5324 0, 0,
5325 0, 0,
5326 0, 0,
5327 0, 0,
5328 0, 0,
5329 0, 0,
5330 0, 0,
5331 0, 0,
5332 0, 0,
5333 0, 0,
5334 0, 0,
5335 0, 0,
5336 0, 0,
5337 0, 0,
5338 0, 0,
5339 0, 0,
5340 0, 0,
5341 0, 0,
5342 0, 0,
5343 0, 0,
5344 0, 0,
5345 GP_7_3_FN, GPSR7_3,
5346 GP_7_2_FN, GPSR7_2,
5347 GP_7_1_FN, GPSR7_1,
5348 GP_7_0_FN, GPSR7_0, }
5349 },
5350#undef F_
5351#undef FM
5352
5353#define F_(x, y) x,
5354#define FM(x) FN_##x,
5355 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
5356 IP0_31_28
5357 IP0_27_24
5358 IP0_23_20
5359 IP0_19_16
5360 IP0_15_12
5361 IP0_11_8
5362 IP0_7_4
5363 IP0_3_0 }
5364 },
5365 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
5366 IP1_31_28
5367 IP1_27_24
5368 IP1_23_20
5369 IP1_19_16
5370 IP1_15_12
5371 IP1_11_8
5372 IP1_7_4
5373 IP1_3_0 }
5374 },
5375 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
5376 IP2_31_28
5377 IP2_27_24
5378 IP2_23_20
5379 IP2_19_16
5380 IP2_15_12
5381 IP2_11_8
5382 IP2_7_4
5383 IP2_3_0 }
5384 },
5385 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
5386 IP3_31_28
5387 IP3_27_24
5388 IP3_23_20
5389 IP3_19_16
5390 IP3_15_12
5391 IP3_11_8
5392 IP3_7_4
5393 IP3_3_0 }
5394 },
5395 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
5396 IP4_31_28
5397 IP4_27_24
5398 IP4_23_20
5399 IP4_19_16
5400 IP4_15_12
5401 IP4_11_8
5402 IP4_7_4
5403 IP4_3_0 }
5404 },
5405 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
5406 IP5_31_28
5407 IP5_27_24
5408 IP5_23_20
5409 IP5_19_16
5410 IP5_15_12
5411 IP5_11_8
5412 IP5_7_4
5413 IP5_3_0 }
5414 },
5415 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
5416 IP6_31_28
5417 IP6_27_24
5418 IP6_23_20
5419 IP6_19_16
5420 IP6_15_12
5421 IP6_11_8
5422 IP6_7_4
5423 IP6_3_0 }
5424 },
5425 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
5426 IP7_31_28
5427 IP7_27_24
5428 IP7_23_20
5429 IP7_19_16
5430 /* IP7_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5431 IP7_11_8
5432 IP7_7_4
5433 IP7_3_0 }
5434 },
5435 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
5436 IP8_31_28
5437 IP8_27_24
5438 IP8_23_20
5439 IP8_19_16
5440 IP8_15_12
5441 IP8_11_8
5442 IP8_7_4
5443 IP8_3_0 }
5444 },
5445 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
5446 IP9_31_28
5447 IP9_27_24
5448 IP9_23_20
5449 IP9_19_16
5450 IP9_15_12
5451 IP9_11_8
5452 IP9_7_4
5453 IP9_3_0 }
5454 },
5455 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
5456 IP10_31_28
5457 IP10_27_24
5458 IP10_23_20
5459 IP10_19_16
5460 IP10_15_12
5461 IP10_11_8
5462 IP10_7_4
5463 IP10_3_0 }
5464 },
5465 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
5466 IP11_31_28
5467 IP11_27_24
5468 IP11_23_20
5469 IP11_19_16
5470 IP11_15_12
5471 IP11_11_8
5472 IP11_7_4
5473 IP11_3_0 }
5474 },
5475 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
5476 IP12_31_28
5477 IP12_27_24
5478 IP12_23_20
5479 IP12_19_16
5480 IP12_15_12
5481 IP12_11_8
5482 IP12_7_4
5483 IP12_3_0 }
5484 },
5485 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
5486 IP13_31_28
5487 IP13_27_24
5488 IP13_23_20
5489 IP13_19_16
5490 IP13_15_12
5491 IP13_11_8
5492 IP13_7_4
5493 IP13_3_0 }
5494 },
5495 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
5496 IP14_31_28
5497 IP14_27_24
5498 IP14_23_20
5499 IP14_19_16
5500 IP14_15_12
5501 IP14_11_8
5502 IP14_7_4
5503 IP14_3_0 }
5504 },
5505 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
5506 IP15_31_28
5507 IP15_27_24
5508 IP15_23_20
5509 IP15_19_16
5510 IP15_15_12
5511 IP15_11_8
5512 IP15_7_4
5513 IP15_3_0 }
5514 },
5515 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
5516 IP16_31_28
5517 IP16_27_24
5518 IP16_23_20
5519 IP16_19_16
5520 IP16_15_12
5521 IP16_11_8
5522 IP16_7_4
5523 IP16_3_0 }
5524 },
5525 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
5526 IP17_31_28
5527 IP17_27_24
5528 IP17_23_20
5529 IP17_19_16
5530 IP17_15_12
5531 IP17_11_8
5532 IP17_7_4
5533 IP17_3_0 }
5534 },
5535 { PINMUX_CFG_REG("IPSR18", 0xe6060248, 32, 4) {
5536 /* IP18_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5537 /* IP18_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5538 /* IP18_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5539 /* IP18_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5540 /* IP18_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5541 /* IP18_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5542 IP18_7_4
5543 IP18_3_0 }
5544 },
5545#undef F_
5546#undef FM
5547
5548#define F_(x, y) x,
5549#define FM(x) FN_##x,
5550 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
5551 3, 2, 3, 1, 1, 1, 1, 1, 2, 1,
5552 1, 2, 1, 1, 1, 2, 2, 1, 2, 3) {
5553 MOD_SEL0_31_30_29
5554 MOD_SEL0_28_27
5555 MOD_SEL0_26_25_24
5556 MOD_SEL0_23
5557 MOD_SEL0_22
5558 MOD_SEL0_21
5559 MOD_SEL0_20
5560 MOD_SEL0_19
5561 MOD_SEL0_18_17
5562 MOD_SEL0_16
5563 0, 0, /* RESERVED 15 */
5564 MOD_SEL0_14_13
5565 MOD_SEL0_12
5566 MOD_SEL0_11
5567 MOD_SEL0_10
5568 MOD_SEL0_9_8
5569 MOD_SEL0_7_6
5570 MOD_SEL0_5
5571 MOD_SEL0_4_3
5572 /* RESERVED 2, 1, 0 */
5573 0, 0, 0, 0, 0, 0, 0, 0 }
5574 },
5575 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
5576 2, 3, 1, 2, 3, 1, 1, 2, 1,
5577 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
5578 MOD_SEL1_31_30
5579 MOD_SEL1_29_28_27
5580 MOD_SEL1_26
5581 MOD_SEL1_25_24
5582 MOD_SEL1_23_22_21
5583 MOD_SEL1_20
5584 MOD_SEL1_19
5585 MOD_SEL1_18_17
5586 MOD_SEL1_16
5587 MOD_SEL1_15_14
5588 MOD_SEL1_13
5589 MOD_SEL1_12
5590 MOD_SEL1_11
5591 MOD_SEL1_10
5592 MOD_SEL1_9
5593 0, 0, 0, 0, /* RESERVED 8, 7 */
5594 MOD_SEL1_6
5595 MOD_SEL1_5
5596 MOD_SEL1_4
5597 MOD_SEL1_3
5598 MOD_SEL1_2
5599 MOD_SEL1_1
5600 MOD_SEL1_0 }
5601 },
5602 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
5603 1, 1, 1, 2, 1, 3, 1, 1, 1, 1, 1, 1, 1,
5604 4, 4, 4, 3, 1) {
5605 MOD_SEL2_31
5606 MOD_SEL2_30
5607 MOD_SEL2_29
5608 MOD_SEL2_28_27
5609 MOD_SEL2_26
5610 MOD_SEL2_25_24_23
5611 /* RESERVED 22 */
5612 0, 0,
5613 MOD_SEL2_21
5614 MOD_SEL2_20
5615 MOD_SEL2_19
5616 MOD_SEL2_18
5617 MOD_SEL2_17
5618 /* RESERVED 16 */
5619 0, 0,
5620 /* RESERVED 15, 14, 13, 12 */
5621 0, 0, 0, 0, 0, 0, 0, 0,
5622 0, 0, 0, 0, 0, 0, 0, 0,
5623 /* RESERVED 11, 10, 9, 8 */
5624 0, 0, 0, 0, 0, 0, 0, 0,
5625 0, 0, 0, 0, 0, 0, 0, 0,
5626 /* RESERVED 7, 6, 5, 4 */
5627 0, 0, 0, 0, 0, 0, 0, 0,
5628 0, 0, 0, 0, 0, 0, 0, 0,
5629 /* RESERVED 3, 2, 1 */
5630 0, 0, 0, 0, 0, 0, 0, 0,
5631 MOD_SEL2_0 }
5632 },
5633 { },
5634};
5635
5636static const struct pinmux_drive_reg pinmux_drive_regs[] = {
5637 { PINMUX_DRIVE_REG("DRVCTRL0", 0xe6060300) {
5638 { PIN_NUMBER('W', 3), 28, 2 }, /* QSPI0_SPCLK */
5639 { PIN_A_NUMBER('C', 5), 24, 2 }, /* QSPI0_MOSI_IO0 */
5640 { PIN_A_NUMBER('B', 4), 20, 2 }, /* QSPI0_MISO_IO1 */
5641 { PIN_NUMBER('Y', 6), 16, 2 }, /* QSPI0_IO2 */
5642 { PIN_A_NUMBER('B', 6), 12, 2 }, /* QSPI0_IO3 */
5643 { PIN_NUMBER('Y', 3), 8, 2 }, /* QSPI0_SSL */
5644 { PIN_NUMBER('V', 3), 4, 2 }, /* QSPI1_SPCLK */
5645 { PIN_A_NUMBER('C', 7), 0, 2 }, /* QSPI1_MOSI_IO0 */
5646 } },
5647 { PINMUX_DRIVE_REG("DRVCTRL1", 0xe6060304) {
5648 { PIN_A_NUMBER('E', 5), 28, 2 }, /* QSPI1_MISO_IO1 */
5649 { PIN_A_NUMBER('E', 4), 24, 2 }, /* QSPI1_IO2 */
5650 { PIN_A_NUMBER('C', 3), 20, 2 }, /* QSPI1_IO3 */
5651 { PIN_NUMBER('V', 5), 16, 2 }, /* QSPI1_SSL */
5652 { PIN_NUMBER('Y', 7), 12, 2 }, /* RPC_INT# */
5653 { PIN_NUMBER('V', 6), 8, 2 }, /* RPC_WP# */
5654 { PIN_NUMBER('V', 7), 4, 2 }, /* RPC_RESET# */
5655 { PIN_NUMBER('A', 16), 0, 3 }, /* AVB_RX_CTL */
5656 } },
5657 { PINMUX_DRIVE_REG("DRVCTRL2", 0xe6060308) {
5658 { PIN_NUMBER('B', 19), 28, 3 }, /* AVB_RXC */
5659 { PIN_NUMBER('A', 13), 24, 3 }, /* AVB_RD0 */
5660 { PIN_NUMBER('B', 13), 20, 3 }, /* AVB_RD1 */
5661 { PIN_NUMBER('A', 14), 16, 3 }, /* AVB_RD2 */
5662 { PIN_NUMBER('B', 14), 12, 3 }, /* AVB_RD3 */
5663 { PIN_NUMBER('A', 8), 8, 3 }, /* AVB_TX_CTL */
5664 { PIN_NUMBER('A', 19), 4, 3 }, /* AVB_TXC */
5665 { PIN_NUMBER('A', 18), 0, 3 }, /* AVB_TD0 */
5666 } },
5667 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
5668 { PIN_NUMBER('B', 18), 28, 3 }, /* AVB_TD1 */
5669 { PIN_NUMBER('A', 17), 24, 3 }, /* AVB_TD2 */
5670 { PIN_NUMBER('B', 17), 20, 3 }, /* AVB_TD3 */
5671 { PIN_NUMBER('A', 12), 16, 3 }, /* AVB_TXCREFCLK */
5672 { PIN_NUMBER('A', 9), 12, 3 }, /* AVB_MDIO */
5673 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
5674 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
5675 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
5676 } },
5677 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
5678 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
5679 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
5680 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
5681 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
5682 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
5683 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
5684 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
5685 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
5686 } },
5687 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
5688 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
5689 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
5690 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
5691 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
5692 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
5693 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
5694 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
5695 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
5696 } },
5697 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
5698 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
5699 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
5700 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
5701 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
5702 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
5703 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
5704 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
5705 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
5706 } },
5707 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
5708 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
5709 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
5710 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
5711 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
5712 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
5713 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
5714 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
5715 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
5716 } },
5717 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]5718 { RCAR_GP_PIN(1, 28), 28, 3 }, /* CLKOUT */
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]5719 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
5720 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
5721 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
5722 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
5723 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
5724 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
5725 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
5726 } },
5727 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
5728 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
5729 { PIN_NUMBER('C', 1), 24, 3 }, /* PRESETOUT# */
5730 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
5731 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
5732 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
5733 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
5734 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
5735 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
5736 } },
5737 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
5738 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
5739 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
5740 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
5741 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
5742 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
5743 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
5744 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
5745 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
5746 } },
5747 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
5748 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
5749 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
5750 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
5751 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
5752 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
5753 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
5754 { PIN_A_NUMBER('P', 7), 4, 2 }, /* DU_DOTCLKIN0 */
5755 { PIN_A_NUMBER('P', 8), 0, 2 }, /* DU_DOTCLKIN1 */
5756 } },
5757 { PINMUX_DRIVE_REG("DRVCTRL12", 0xe6060330) {
5758 { PIN_A_NUMBER('R', 7), 28, 2 }, /* DU_DOTCLKIN2 */
5759 { PIN_A_NUMBER('R', 8), 24, 2 }, /* DU_DOTCLKIN3 */
5760 { PIN_A_NUMBER('D', 38), 20, 2 }, /* FSCLKST# */
5761 { PIN_A_NUMBER('R', 30), 4, 2 }, /* TMS */
5762 } },
5763 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
5764 { PIN_A_NUMBER('T', 28), 28, 2 }, /* TDO */
5765 { PIN_A_NUMBER('T', 30), 24, 2 }, /* ASEBRK */
5766 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
5767 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
5768 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
5769 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
5770 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
5771 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
5772 } },
5773 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
5774 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
5775 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
5776 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
5777 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
5778 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
5779 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
5780 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
5781 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
5782 } },
5783 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
5784 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
5785 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
5786 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
5787 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
5788 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
5789 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
5790 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
5791 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
5792 } },
5793 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
5794 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
5795 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
5796 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
5797 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
5798 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
5799 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
5800 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
5801 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
5802 } },
5803 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
5804 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
5805 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
5806 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
5807 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
5808 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
5809 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
5810 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
5811 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
5812 } },
5813 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]5814 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0 */
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]5815 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
5816 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
5817 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]5818 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1 */
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]5819 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
5820 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
5821 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
5822 } },
5823 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
5824 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
5825 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
5826 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
5827 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
5828 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
5829 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
5830 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
5831 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
5832 } },
5833 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
5834 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
5835 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
5836 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
5837 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
5838 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
5839 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
5840 { PIN_NUMBER('H', 37), 4, 3 }, /* MLB_REF */
5841 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
5842 } },
5843 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
5844 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
5845 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
5846 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
5847 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
5848 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK349 */
5849 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS349 */
5850 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
5851 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
5852 } },
5853 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
5854 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
5855 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
5856 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
5857 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
5858 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
5859 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
5860 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
5861 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
5862 } },
5863 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
5864 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
5865 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
5866 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
5867 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
5868 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
5869 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
5870 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
5871 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
5872 } },
5873 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
5874 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
5875 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
5876 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
5877 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
5878 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
5879 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB2_CH3_PWEN */
5880 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB2_CH3_OVC */
5881 } },
5882 { },
5883};
5884
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]5885enum ioctrl_regs {
5886 POCCTRL,
5887};
5888
5889static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = {
5890 [POCCTRL] = { 0xe6060380, },
5891 { /* sentinel */ },
5892};
5893
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]5894static int r8a7795_pin_to_pocctrl(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl)
5895{
5896 int bit = -EINVAL;
5897
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]5898 *pocctrl = pinmux_ioctrl_regs[POCCTRL].reg;
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]5899
5900 if (pin >= RCAR_GP_PIN(3, 0) && pin <= RCAR_GP_PIN(3, 11))
5901 bit = pin & 0x1f;
5902
5903 if (pin >= RCAR_GP_PIN(4, 0) && pin <= RCAR_GP_PIN(4, 17))
5904 bit = (pin & 0x1f) + 12;
5905
5906 return bit;
5907}
5908
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]5909static const struct pinmux_bias_reg pinmux_bias_regs[] = {
5910 { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) {
5911 [ 0] = PIN_NUMBER('W', 3), /* QSPI0_SPCLK */
5912 [ 1] = PIN_A_NUMBER('C', 5), /* QSPI0_MOSI_IO0 */
5913 [ 2] = PIN_A_NUMBER('B', 4), /* QSPI0_MISO_IO1 */
5914 [ 3] = PIN_NUMBER('Y', 6), /* QSPI0_IO2 */
5915 [ 4] = PIN_A_NUMBER('B', 6), /* QSPI0_IO3 */
5916 [ 5] = PIN_NUMBER('Y', 3), /* QSPI0_SSL */
5917 [ 6] = PIN_NUMBER('V', 3), /* QSPI1_SPCLK */
5918 [ 7] = PIN_A_NUMBER('C', 7), /* QSPI1_MOSI_IO0 */
5919 [ 8] = PIN_A_NUMBER('E', 5), /* QSPI1_MISO_IO1 */
5920 [ 9] = PIN_A_NUMBER('E', 4), /* QSPI1_IO2 */
5921 [10] = PIN_A_NUMBER('C', 3), /* QSPI1_IO3 */
5922 [11] = PIN_NUMBER('V', 5), /* QSPI1_SSL */
5923 [12] = PIN_NUMBER('Y', 7), /* RPC_INT# */
5924 [13] = PIN_NUMBER('V', 6), /* RPC_WP# */
5925 [14] = PIN_NUMBER('V', 7), /* RPC_RESET# */
5926 [15] = PIN_NUMBER('A', 16), /* AVB_RX_CTL */
5927 [16] = PIN_NUMBER('B', 19), /* AVB_RXC */
5928 [17] = PIN_NUMBER('A', 13), /* AVB_RD0 */
5929 [18] = PIN_NUMBER('B', 13), /* AVB_RD1 */
5930 [19] = PIN_NUMBER('A', 14), /* AVB_RD2 */
5931 [20] = PIN_NUMBER('B', 14), /* AVB_RD3 */
5932 [21] = PIN_NUMBER('A', 8), /* AVB_TX_CTL */
5933 [22] = PIN_NUMBER('A', 19), /* AVB_TXC */
5934 [23] = PIN_NUMBER('A', 18), /* AVB_TD0 */
5935 [24] = PIN_NUMBER('B', 18), /* AVB_TD1 */
5936 [25] = PIN_NUMBER('A', 17), /* AVB_TD2 */
5937 [26] = PIN_NUMBER('B', 17), /* AVB_TD3 */
5938 [27] = PIN_NUMBER('A', 12), /* AVB_TXCREFCLK */
5939 [28] = PIN_NUMBER('A', 9), /* AVB_MDIO */
5940 [29] = RCAR_GP_PIN(2, 9), /* AVB_MDC */
5941 [30] = RCAR_GP_PIN(2, 10), /* AVB_MAGIC */
5942 [31] = RCAR_GP_PIN(2, 11), /* AVB_PHY_INT */
5943 } },
5944 { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) {
5945 [ 0] = RCAR_GP_PIN(2, 12), /* AVB_LINK */
5946 [ 1] = RCAR_GP_PIN(2, 13), /* AVB_AVTP_MATCH_A */
5947 [ 2] = RCAR_GP_PIN(2, 14), /* AVB_AVTP_CAPTURE_A */
5948 [ 3] = RCAR_GP_PIN(2, 0), /* IRQ0 */
5949 [ 4] = RCAR_GP_PIN(2, 1), /* IRQ1 */
5950 [ 5] = RCAR_GP_PIN(2, 2), /* IRQ2 */
5951 [ 6] = RCAR_GP_PIN(2, 3), /* IRQ3 */
5952 [ 7] = RCAR_GP_PIN(2, 4), /* IRQ4 */
5953 [ 8] = RCAR_GP_PIN(2, 5), /* IRQ5 */
5954 [ 9] = RCAR_GP_PIN(2, 6), /* PWM0 */
5955 [10] = RCAR_GP_PIN(2, 7), /* PWM1_A */
5956 [11] = RCAR_GP_PIN(2, 8), /* PWM2_A */
5957 [12] = RCAR_GP_PIN(1, 0), /* A0 */
5958 [13] = RCAR_GP_PIN(1, 1), /* A1 */
5959 [14] = RCAR_GP_PIN(1, 2), /* A2 */
5960 [15] = RCAR_GP_PIN(1, 3), /* A3 */
5961 [16] = RCAR_GP_PIN(1, 4), /* A4 */
5962 [17] = RCAR_GP_PIN(1, 5), /* A5 */
5963 [18] = RCAR_GP_PIN(1, 6), /* A6 */
5964 [19] = RCAR_GP_PIN(1, 7), /* A7 */
5965 [20] = RCAR_GP_PIN(1, 8), /* A8 */
5966 [21] = RCAR_GP_PIN(1, 9), /* A9 */
5967 [22] = RCAR_GP_PIN(1, 10), /* A10 */
5968 [23] = RCAR_GP_PIN(1, 11), /* A11 */
5969 [24] = RCAR_GP_PIN(1, 12), /* A12 */
5970 [25] = RCAR_GP_PIN(1, 13), /* A13 */
5971 [26] = RCAR_GP_PIN(1, 14), /* A14 */
5972 [27] = RCAR_GP_PIN(1, 15), /* A15 */
5973 [28] = RCAR_GP_PIN(1, 16), /* A16 */
5974 [29] = RCAR_GP_PIN(1, 17), /* A17 */
5975 [30] = RCAR_GP_PIN(1, 18), /* A18 */
5976 [31] = RCAR_GP_PIN(1, 19), /* A19 */
5977 } },
5978 { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) {
5979 [ 0] = RCAR_GP_PIN(1, 28), /* CLKOUT */
5980 [ 1] = RCAR_GP_PIN(1, 20), /* CS0_N */
5981 [ 2] = RCAR_GP_PIN(1, 21), /* CS1_N */
5982 [ 3] = RCAR_GP_PIN(1, 22), /* BS_N */
5983 [ 4] = RCAR_GP_PIN(1, 23), /* RD_N */
5984 [ 5] = RCAR_GP_PIN(1, 24), /* RD_WR_N */
5985 [ 6] = RCAR_GP_PIN(1, 25), /* WE0_N */
5986 [ 7] = RCAR_GP_PIN(1, 26), /* WE1_N */
5987 [ 8] = RCAR_GP_PIN(1, 27), /* EX_WAIT0_A */
5988 [ 9] = PIN_NUMBER('C', 1), /* PRESETOUT# */
5989 [10] = RCAR_GP_PIN(0, 0), /* D0 */
5990 [11] = RCAR_GP_PIN(0, 1), /* D1 */
5991 [12] = RCAR_GP_PIN(0, 2), /* D2 */
5992 [13] = RCAR_GP_PIN(0, 3), /* D3 */
5993 [14] = RCAR_GP_PIN(0, 4), /* D4 */
5994 [15] = RCAR_GP_PIN(0, 5), /* D5 */
5995 [16] = RCAR_GP_PIN(0, 6), /* D6 */
5996 [17] = RCAR_GP_PIN(0, 7), /* D7 */
5997 [18] = RCAR_GP_PIN(0, 8), /* D8 */
5998 [19] = RCAR_GP_PIN(0, 9), /* D9 */
5999 [20] = RCAR_GP_PIN(0, 10), /* D10 */
6000 [21] = RCAR_GP_PIN(0, 11), /* D11 */
6001 [22] = RCAR_GP_PIN(0, 12), /* D12 */
6002 [23] = RCAR_GP_PIN(0, 13), /* D13 */
6003 [24] = RCAR_GP_PIN(0, 14), /* D14 */
6004 [25] = RCAR_GP_PIN(0, 15), /* D15 */
6005 [26] = RCAR_GP_PIN(7, 0), /* AVS1 */
6006 [27] = RCAR_GP_PIN(7, 1), /* AVS2 */
6007 [28] = RCAR_GP_PIN(7, 2), /* HDMI0_CEC */
6008 [29] = RCAR_GP_PIN(7, 3), /* HDMI1_CEC */
6009 [30] = PIN_A_NUMBER('P', 7), /* DU_DOTCLKIN0 */
6010 [31] = PIN_A_NUMBER('P', 8), /* DU_DOTCLKIN1 */
6011 } },
6012 { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) {
6013 [ 0] = PIN_A_NUMBER('R', 7), /* DU_DOTCLKIN2 */
6014 [ 1] = PIN_A_NUMBER('R', 8), /* DU_DOTCLKIN3 */
6015 [ 2] = PIN_A_NUMBER('D', 38), /* FSCLKST# */
6016 [ 3] = PIN_A_NUMBER('D', 39), /* EXTALR*/
6017 [ 4] = PIN_A_NUMBER('R', 26), /* TRST# */
6018 [ 5] = PIN_A_NUMBER('T', 27), /* TCK */
6019 [ 6] = PIN_A_NUMBER('R', 30), /* TMS */
6020 [ 7] = PIN_A_NUMBER('R', 29), /* TDI */
6021 [ 8] = PIN_NONE,
6022 [ 9] = PIN_A_NUMBER('T', 30), /* ASEBRK */
6023 [10] = RCAR_GP_PIN(3, 0), /* SD0_CLK */
6024 [11] = RCAR_GP_PIN(3, 1), /* SD0_CMD */
6025 [12] = RCAR_GP_PIN(3, 2), /* SD0_DAT0 */
6026 [13] = RCAR_GP_PIN(3, 3), /* SD0_DAT1 */
6027 [14] = RCAR_GP_PIN(3, 4), /* SD0_DAT2 */
6028 [15] = RCAR_GP_PIN(3, 5), /* SD0_DAT3 */
6029 [16] = RCAR_GP_PIN(3, 6), /* SD1_CLK */
6030 [17] = RCAR_GP_PIN(3, 7), /* SD1_CMD */
6031 [18] = RCAR_GP_PIN(3, 8), /* SD1_DAT0 */
6032 [19] = RCAR_GP_PIN(3, 9), /* SD1_DAT1 */
6033 [20] = RCAR_GP_PIN(3, 10), /* SD1_DAT2 */
6034 [21] = RCAR_GP_PIN(3, 11), /* SD1_DAT3 */
6035 [22] = RCAR_GP_PIN(4, 0), /* SD2_CLK */
6036 [23] = RCAR_GP_PIN(4, 1), /* SD2_CMD */
6037 [24] = RCAR_GP_PIN(4, 2), /* SD2_DAT0 */
6038 [25] = RCAR_GP_PIN(4, 3), /* SD2_DAT1 */
6039 [26] = RCAR_GP_PIN(4, 4), /* SD2_DAT2 */
6040 [27] = RCAR_GP_PIN(4, 5), /* SD2_DAT3 */
6041 [28] = RCAR_GP_PIN(4, 6), /* SD2_DS */
6042 [29] = RCAR_GP_PIN(4, 7), /* SD3_CLK */
6043 [30] = RCAR_GP_PIN(4, 8), /* SD3_CMD */
6044 [31] = RCAR_GP_PIN(4, 9), /* SD3_DAT0 */
6045 } },
6046 { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) {
6047 [ 0] = RCAR_GP_PIN(4, 10), /* SD3_DAT1 */
6048 [ 1] = RCAR_GP_PIN(4, 11), /* SD3_DAT2 */
6049 [ 2] = RCAR_GP_PIN(4, 12), /* SD3_DAT3 */
6050 [ 3] = RCAR_GP_PIN(4, 13), /* SD3_DAT4 */
6051 [ 4] = RCAR_GP_PIN(4, 14), /* SD3_DAT5 */
6052 [ 5] = RCAR_GP_PIN(4, 15), /* SD3_DAT6 */
6053 [ 6] = RCAR_GP_PIN(4, 16), /* SD3_DAT7 */
6054 [ 7] = RCAR_GP_PIN(4, 17), /* SD3_DS */
6055 [ 8] = RCAR_GP_PIN(3, 12), /* SD0_CD */
6056 [ 9] = RCAR_GP_PIN(3, 13), /* SD0_WP */
6057 [10] = RCAR_GP_PIN(3, 14), /* SD1_CD */
6058 [11] = RCAR_GP_PIN(3, 15), /* SD1_WP */
6059 [12] = RCAR_GP_PIN(5, 0), /* SCK0 */
6060 [13] = RCAR_GP_PIN(5, 1), /* RX0 */
6061 [14] = RCAR_GP_PIN(5, 2), /* TX0 */
6062 [15] = RCAR_GP_PIN(5, 3), /* CTS0_N */
6063 [16] = RCAR_GP_PIN(5, 4), /* RTS0_N */
6064 [17] = RCAR_GP_PIN(5, 5), /* RX1_A */
6065 [18] = RCAR_GP_PIN(5, 6), /* TX1_A */
6066 [19] = RCAR_GP_PIN(5, 7), /* CTS1_N */
6067 [20] = RCAR_GP_PIN(5, 8), /* RTS1_N */
6068 [21] = RCAR_GP_PIN(5, 9), /* SCK2 */
6069 [22] = RCAR_GP_PIN(5, 10), /* TX2_A */
6070 [23] = RCAR_GP_PIN(5, 11), /* RX2_A */
6071 [24] = RCAR_GP_PIN(5, 12), /* HSCK0 */
6072 [25] = RCAR_GP_PIN(5, 13), /* HRX0 */
6073 [26] = RCAR_GP_PIN(5, 14), /* HTX0 */
6074 [27] = RCAR_GP_PIN(5, 15), /* HCTS0_N */
6075 [28] = RCAR_GP_PIN(5, 16), /* HRTS0_N */
6076 [29] = RCAR_GP_PIN(5, 17), /* MSIOF0_SCK */
6077 [30] = RCAR_GP_PIN(5, 18), /* MSIOF0_SYNC */
6078 [31] = RCAR_GP_PIN(5, 19), /* MSIOF0_SS1 */
6079 } },
6080 { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD5", 0xe6060454) {
6081 [ 0] = RCAR_GP_PIN(5, 20), /* MSIOF0_TXD */
6082 [ 1] = RCAR_GP_PIN(5, 21), /* MSIOF0_SS2 */
6083 [ 2] = RCAR_GP_PIN(5, 22), /* MSIOF0_RXD */
6084 [ 3] = RCAR_GP_PIN(5, 23), /* MLB_CLK */
6085 [ 4] = RCAR_GP_PIN(5, 24), /* MLB_SIG */
6086 [ 5] = RCAR_GP_PIN(5, 25), /* MLB_DAT */
6087 [ 6] = PIN_NUMBER('H', 37), /* MLB_REF */
6088 [ 7] = RCAR_GP_PIN(6, 0), /* SSI_SCK01239 */
6089 [ 8] = RCAR_GP_PIN(6, 1), /* SSI_WS01239 */
6090 [ 9] = RCAR_GP_PIN(6, 2), /* SSI_SDATA0 */
6091 [10] = RCAR_GP_PIN(6, 3), /* SSI_SDATA1_A */
6092 [11] = RCAR_GP_PIN(6, 4), /* SSI_SDATA2_A */
6093 [12] = RCAR_GP_PIN(6, 5), /* SSI_SCK349 */
6094 [13] = RCAR_GP_PIN(6, 6), /* SSI_WS349 */
6095 [14] = RCAR_GP_PIN(6, 7), /* SSI_SDATA3 */
6096 [15] = RCAR_GP_PIN(6, 8), /* SSI_SCK4 */
6097 [16] = RCAR_GP_PIN(6, 9), /* SSI_WS4 */
6098 [17] = RCAR_GP_PIN(6, 10), /* SSI_SDATA4 */
6099 [18] = RCAR_GP_PIN(6, 11), /* SSI_SCK5 */
6100 [19] = RCAR_GP_PIN(6, 12), /* SSI_WS5 */
6101 [20] = RCAR_GP_PIN(6, 13), /* SSI_SDATA5 */
6102 [21] = RCAR_GP_PIN(6, 14), /* SSI_SCK6 */
6103 [22] = RCAR_GP_PIN(6, 15), /* SSI_WS6 */
6104 [23] = RCAR_GP_PIN(6, 16), /* SSI_SDATA6 */
6105 [24] = RCAR_GP_PIN(6, 17), /* SSI_SCK78 */
6106 [25] = RCAR_GP_PIN(6, 18), /* SSI_WS78 */
6107 [26] = RCAR_GP_PIN(6, 19), /* SSI_SDATA7 */
6108 [27] = RCAR_GP_PIN(6, 20), /* SSI_SDATA8 */
6109 [28] = RCAR_GP_PIN(6, 21), /* SSI_SDATA9_A */
6110 [29] = RCAR_GP_PIN(6, 22), /* AUDIO_CLKA_A */
6111 [30] = RCAR_GP_PIN(6, 23), /* AUDIO_CLKB_B */
6112 [31] = RCAR_GP_PIN(6, 24), /* USB0_PWEN */
6113 } },
6114 { PINMUX_BIAS_REG("PUEN6", 0xe6060418, "PUD6", 0xe6060458) {
6115 [ 0] = RCAR_GP_PIN(6, 25), /* USB0_OVC */
6116 [ 1] = RCAR_GP_PIN(6, 26), /* USB1_PWEN */
6117 [ 2] = RCAR_GP_PIN(6, 27), /* USB1_OVC */
6118 [ 3] = RCAR_GP_PIN(6, 28), /* USB30_PWEN */
6119 [ 4] = RCAR_GP_PIN(6, 29), /* USB30_OVC */
6120 [ 5] = RCAR_GP_PIN(6, 30), /* USB2_CH3_PWEN */
6121 [ 6] = RCAR_GP_PIN(6, 31), /* USB2_CH3_OVC */
6122 [ 7] = PIN_NONE,
6123 [ 8] = PIN_NONE,
6124 [ 9] = PIN_NONE,
6125 [10] = PIN_NONE,
6126 [11] = PIN_NONE,
6127 [12] = PIN_NONE,
6128 [13] = PIN_NONE,
6129 [14] = PIN_NONE,
6130 [15] = PIN_NONE,
6131 [16] = PIN_NONE,
6132 [17] = PIN_NONE,
6133 [18] = PIN_NONE,
6134 [19] = PIN_NONE,
6135 [20] = PIN_NONE,
6136 [21] = PIN_NONE,
6137 [22] = PIN_NONE,
6138 [23] = PIN_NONE,
6139 [24] = PIN_NONE,
6140 [25] = PIN_NONE,
6141 [26] = PIN_NONE,
6142 [27] = PIN_NONE,
6143 [28] = PIN_NONE,
6144 [29] = PIN_NONE,
6145 [30] = PIN_NONE,
6146 [31] = PIN_NONE,
6147 } },
6148 { /* sentinel */ },
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]6149};
6150
6151static unsigned int r8a7795_pinmux_get_bias(struct sh_pfc *pfc,
6152 unsigned int pin)
6153{
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]6154 const struct pinmux_bias_reg *reg;
6155 unsigned int bit;
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]6156
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]6157 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6158 if (!reg)
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]6159 return PIN_CONFIG_BIAS_DISABLE;
6160
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]6161 if (!(sh_pfc_read(pfc, reg->puen) & BIT(bit)))
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]6162 return PIN_CONFIG_BIAS_DISABLE;
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]6163 else if (sh_pfc_read(pfc, reg->pud) & BIT(bit))
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]6164 return PIN_CONFIG_BIAS_PULL_UP;
6165 else
6166 return PIN_CONFIG_BIAS_PULL_DOWN;
6167}
6168
6169static void r8a7795_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
6170 unsigned int bias)
6171{
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]6172 const struct pinmux_bias_reg *reg;
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]6173 u32 enable, updown;
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]6174 unsigned int bit;
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]6175
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]6176 reg = sh_pfc_pin_to_bias_reg(pfc, pin, &bit);
6177 if (!reg)
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]6178 return;
6179
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]6180 enable = sh_pfc_read(pfc, reg->puen) & ~BIT(bit);
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]6181 if (bias != PIN_CONFIG_BIAS_DISABLE)
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]6182 enable |= BIT(bit);
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]6183
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]6184 updown = sh_pfc_read(pfc, reg->pud) & ~BIT(bit);
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]6185 if (bias == PIN_CONFIG_BIAS_PULL_UP)
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]6186 updown |= BIT(bit);
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]6187
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]6188 sh_pfc_write(pfc, reg->pud, updown);
6189 sh_pfc_write(pfc, reg->puen, enable);
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]6190}
6191
6192static const struct sh_pfc_soc_operations r8a7795_pinmux_ops = {
6193 .pin_to_pocctrl = r8a7795_pin_to_pocctrl,
6194 .get_bias = r8a7795_pinmux_get_bias,
6195 .set_bias = r8a7795_pinmux_set_bias,
6196};
6197
6198const struct sh_pfc_soc_info r8a7795_pinmux_info = {
6199 .name = "r8a77951_pfc",
6200 .ops = &r8a7795_pinmux_ops,
6201 .unlock_reg = 0xe6060000, /* PMMR */
6202
6203 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
6204
6205 .pins = pinmux_pins,
6206 .nr_pins = ARRAY_SIZE(pinmux_pins),
6207 .groups = pinmux_groups,
6208 .nr_groups = ARRAY_SIZE(pinmux_groups),
6209 .functions = pinmux_functions,
6210 .nr_functions = ARRAY_SIZE(pinmux_functions),
6211
6212 .cfg_regs = pinmux_config_regs,
6213 .drive_regs = pinmux_drive_regs,
Marek Vasutbf8d2da2018-06-10 16:05:48 +0200[diff] [blame^]6214 .bias_regs = pinmux_bias_regs,
6215 .ioctrl_regs = pinmux_ioctrl_regs,
Marek Vasut910df4d2017-09-15 21:13:55 +0200[diff] [blame]6216
6217 .pinmux_data = pinmux_data,
6218 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
6219};