| TsiChung Liew | bf9a521 | 2009-06-12 11:29:00 +0000 | [diff] [blame^] | 1 | /* |
| 2 | * m520x.h -- Definitions for Freescale Coldfire 520x |
| 3 | * |
| 4 | * Copyright (C) 2004-2009 Freescale Semiconductor, Inc. |
| 5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| 6 | * |
| 7 | * See file CREDITS for list of people who contributed to this |
| 8 | * project. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA |
| 24 | */ |
| 25 | |
| 26 | #ifndef __M520X__ |
| 27 | #define __M520X__ |
| 28 | |
| 29 | /* *** System Control Module (SCM) *** */ |
| 30 | #define SCM_MPR_MPROT0(x) (((x) & 0x0F) << 28) |
| 31 | #define SCM_MPR_MPROT1(x) (((x) & 0x0F) << 24) |
| 32 | #define SCM_MPR_MPROT2(x) (((x) & 0x0F) << 20) |
| 33 | #define MPROT_MTR 4 |
| 34 | #define MPROT_MTW 2 |
| 35 | #define MPROT_MPL 1 |
| 36 | |
| 37 | #define SCM_PACRA_PACR0(x) (((x) & 0x0F) << 28) |
| 38 | #define SCM_PACRA_PACR1(x) (((x) & 0x0F) << 24) |
| 39 | #define SCM_PACRA_PACR2(x) (((x) & 0x0F) << 20) |
| 40 | |
| 41 | #define SCM_PACRB_PACR12(x) (((x) & 0x0F) << 12) |
| 42 | |
| 43 | #define SCM_PACRC_PACR16(x) (((x) & 0x0F) << 28) |
| 44 | #define SCM_PACRC_PACR17(x) (((x) & 0x0F) << 24) |
| 45 | #define SCM_PACRC_PACR18(x) (((x) & 0x0F) << 20) |
| 46 | #define SCM_PACRC_PACR21(x) (((x) & 0x0F) << 8) |
| 47 | #define SCM_PACRC_PACR22(x) (((x) & 0x0F) << 4) |
| 48 | #define SCM_PACRC_PACR23(x) ((x) & 0x0F) |
| 49 | |
| 50 | #define SCM_PACRD_PACR24(x) (((x) & 0x0F) << 28) |
| 51 | #define SCM_PACRD_PACR25(x) (((x) & 0x0F) << 24) |
| 52 | #define SCM_PACRD_PACR26(x) (((x) & 0x0F) << 20) |
| 53 | #define SCM_PACRD_PACR28(x) (((x) & 0x0F) << 12) |
| 54 | #define SCM_PACRD_PACR29(x) (((x) & 0x0F) << 8) |
| 55 | #define SCM_PACRD_PACR30(x) (((x) & 0x0F) << 4) |
| 56 | #define SCM_PACRD_PACR31(x) ((x) & 0x0F) |
| 57 | |
| 58 | #define SCM_PACRE_PACR32(x) (((x) & 0x0F) << 28) |
| 59 | #define SCM_PACRE_PACR33(x) (((x) & 0x0F) << 24) |
| 60 | #define SCM_PACRE_PACR34(x) (((x) & 0x0F) << 20) |
| 61 | #define SCM_PACRE_PACR35(x) (((x) & 0x0F) << 16) |
| 62 | #define SCM_PACRE_PACR36(x) (((x) & 0x0F) << 12) |
| 63 | |
| 64 | #define SCM_PACRF_PACR40(x) (((x) & 0x0F) << 28) |
| 65 | #define SCM_PACRF_PACR41(x) (((x) & 0x0F) << 24) |
| 66 | #define SCM_PACRF_PACR42(x) (((x) & 0x0F) << 20) |
| 67 | |
| 68 | #define PACR_SP 4 |
| 69 | #define PACR_WP 2 |
| 70 | #define PACR_TP 1 |
| 71 | |
| 72 | #define SCM_BMT_BME (0x00000008) |
| 73 | #define SCM_BMT_BMT_MASK (0x07) |
| 74 | #define SCM_BMT_BMT(x) ((x) & 0x07) |
| 75 | #define SCM_BMT_BMT1024 (0x0000) |
| 76 | #define SCM_BMT_BMT512 (0x0001) |
| 77 | #define SCM_BMT_BMT256 (0x0002) |
| 78 | #define SCM_BMT_BMT128 (0x0003) |
| 79 | #define SCM_BMT_BMT64 (0x0004) |
| 80 | #define SCM_BMT_BMT32 (0x0005) |
| 81 | #define SCM_BMT_BMT16 (0x0006) |
| 82 | #define SCM_BMT_BMT8 (0x0007) |
| 83 | |
| 84 | #define SCM_CWCR_RO (0x8000) |
| 85 | #define SCM_CWCR_CWR_WH (0x0100) |
| 86 | #define SCM_CWCR_CWE (0x0080) |
| 87 | #define SCM_CWRI_WINDOW (0x0060) |
| 88 | #define SCM_CWRI_RESET (0x0040) |
| 89 | #define SCM_CWRI_INT_RESET (0x0020) |
| 90 | #define SCM_CWRI_INT (0x0000) |
| 91 | #define SCM_CWCR_CWT(x) (((x) & 0x001F)) |
| 92 | |
| 93 | #define SCM_ISR_CFEI (0x02) |
| 94 | #define SCM_ISR_CWIC (0x01) |
| 95 | |
| 96 | #define SCM_CFIER_ECFEI (0x01) |
| 97 | |
| 98 | #define SCM_CFLOC_LOC (0x80) |
| 99 | |
| 100 | #define SCM_CFATR_WRITE (0x80) |
| 101 | #define SCM_CFATR_SZ32 (0x20) |
| 102 | #define SCM_CFATR_SZ16 (0x10) |
| 103 | #define SCM_CFATR_SZ08 (0x00) |
| 104 | #define SCM_CFATR_CACHE (0x08) |
| 105 | #define SCM_CFATR_MODE (0x02) |
| 106 | #define SCM_CFATR_TYPE (0x01) |
| 107 | |
| 108 | /* *** Interrupt Controller (INTC) *** */ |
| 109 | #define INT0_LO_RSVD0 (0) |
| 110 | #define INT0_LO_EPORT_F1 (1) |
| 111 | #define INT0_LO_EPORT_F4 (2) |
| 112 | #define INT0_LO_EPORT_F7 (3) |
| 113 | #define INT1_LO_PIT0 (4) |
| 114 | #define INT1_LO_PIT1 (5) |
| 115 | /* 6 - 7 rsvd */ |
| 116 | #define INT0_LO_EDMA_00 (8) |
| 117 | #define INT0_LO_EDMA_01 (9) |
| 118 | #define INT0_LO_EDMA_02 (10) |
| 119 | #define INT0_LO_EDMA_03 (11) |
| 120 | #define INT0_LO_EDMA_04 (12) |
| 121 | #define INT0_LO_EDMA_05 (13) |
| 122 | #define INT0_LO_EDMA_06 (14) |
| 123 | #define INT0_LO_EDMA_07 (15) |
| 124 | #define INT0_LO_EDMA_08 (16) |
| 125 | #define INT0_LO_EDMA_09 (17) |
| 126 | #define INT0_LO_EDMA_10 (18) |
| 127 | #define INT0_LO_EDMA_11 (19) |
| 128 | #define INT0_LO_EDMA_12 (20) |
| 129 | #define INT0_LO_EDMA_13 (21) |
| 130 | #define INT0_LO_EDMA_14 (22) |
| 131 | #define INT0_LO_EDMA_15 (23) |
| 132 | #define INT0_LO_EDMA_ERR (24) |
| 133 | #define INT0_LO_SCM_CWIC (25) |
| 134 | #define INT0_LO_UART0 (26) |
| 135 | #define INT0_LO_UART1 (27) |
| 136 | #define INT0_LO_UART2 (28) |
| 137 | /* 29 rsvd */ |
| 138 | #define INT0_LO_I2C (30) |
| 139 | #define INT0_LO_QSPI (31) |
| 140 | |
| 141 | #define INT0_HI_DTMR0 (32) |
| 142 | #define INT0_HI_DTMR1 (33) |
| 143 | #define INT0_HI_DTMR2 (34) |
| 144 | #define INT0_HI_DTMR3 (35) |
| 145 | #define INT0_HI_FEC0_TXF (36) |
| 146 | #define INT0_HI_FEC0_TXB (37) |
| 147 | #define INT0_HI_FEC0_UN (38) |
| 148 | #define INT0_HI_FEC0_RL (39) |
| 149 | #define INT0_HI_FEC0_RXF (40) |
| 150 | #define INT0_HI_FEC0_RXB (41) |
| 151 | #define INT0_HI_FEC0_MII (42) |
| 152 | #define INT0_HI_FEC0_LC (43) |
| 153 | #define INT0_HI_FEC0_HBERR (44) |
| 154 | #define INT0_HI_FEC0_GRA (45) |
| 155 | #define INT0_HI_FEC0_EBERR (46) |
| 156 | #define INT0_HI_FEC0_BABT (47) |
| 157 | #define INT0_HI_FEC0_BABR (48) |
| 158 | /* 49 - 61 rsvd */ |
| 159 | #define INT0_HI_SCMISR_CFEI (62) |
| 160 | |
| 161 | /* *** Reset Controller Module (RCM) *** */ |
| 162 | #define RCM_RCR_SOFTRST (0x80) |
| 163 | #define RCM_RCR_FRCRSTOUT (0x40) |
| 164 | |
| 165 | #define RCM_RSR_SOFT (0x20) |
| 166 | #define RCM_RSR_WDOG (0x10) |
| 167 | #define RCM_RSR_POR (0x08) |
| 168 | #define RCM_RSR_EXT (0x04) |
| 169 | #define RCM_RSR_WDR_CORE (0x02) |
| 170 | #define RCM_RSR_LOL (0x01) |
| 171 | |
| 172 | /* *** Chip Configuration Module (CCM) *** */ |
| 173 | #define CCM_CCR_CSC (0x0200) |
| 174 | #define CCM_CCR_OSCFREQ (0x0080) |
| 175 | #define CCM_CCR_LIMP (0x0040) |
| 176 | #define CCM_CCR_LOAD (0x0020) |
| 177 | #define CCM_CCR_BOOTPS(x) (((x) & 0x0003) << 3) |
| 178 | #define CCM_CCR_OSC_MODE (0x0004) |
| 179 | #define CCM_CCR_PLL_MODE (0x0002) |
| 180 | #define CCM_CCR_RESERVED (0x0001) |
| 181 | |
| 182 | #define CCM_CIR_PIN(x) (((x) & 0x03FF) << 6) |
| 183 | #define CCM_CIR_PRN(x) ((x) & 0x003F) |
| 184 | |
| 185 | /* *** General Purpose I/O (GPIO) *** */ |
| 186 | #define GPIO_PDR_BUSCTL(x) ((x) & 0x0F) |
| 187 | #define GPIO_PDR_BE(x) ((x) & 0x0F) |
| 188 | #define GPIO_PDR_CS(x) (((x) & 0x07) << 1) |
| 189 | #define GPIO_PDR_FECI2C(x) ((x) & 0x0F) |
| 190 | #define GPIO_PDR_QSPI(x) ((x) & 0x0F) |
| 191 | #define GPIO_PDR_TIMER(x) ((x) & 0x0F) |
| 192 | #define GPIO_PDR_UART(x) ((x) & 0xFF) |
| 193 | #define GPIO_PDR_FECH(x) ((x) & 0xFF) |
| 194 | #define GPIO_PDR_FECL(x) ((x) & 0xFF) |
| 195 | |
| 196 | #define GPIO_PAR_FBCTL_OE (0x10) |
| 197 | #define GPIO_PAR_FBCTL_TA (0x08) |
| 198 | #define GPIO_PAR_FBCTL_RWB (0x04) |
| 199 | #define GPIO_PAR_FBCTL_TS_MASK (0xFC) |
| 200 | #define GPIO_PAR_FBCTL_TS_TS (0x03) |
| 201 | #define GPIO_PAR_FBCTL_TS_DMA (0x02) |
| 202 | |
| 203 | #define GPIO_PAR_BE3 (0x08) |
| 204 | #define GPIO_PAR_BE2 (0x04) |
| 205 | #define GPIO_PAR_BE1 (0x02) |
| 206 | #define GPIO_PAR_BE0 (0x01) |
| 207 | |
| 208 | #define GPIO_PAR_CS3 (0x08) |
| 209 | #define GPIO_PAR_CS2 (0x04) |
| 210 | #define GPIO_PAR_CS1_MASK (0xFC) |
| 211 | #define GPIO_PAR_CS1_CS1 (0x03) |
| 212 | #define GPIO_PAR_CS1_SDCS1 (0x02) |
| 213 | |
| 214 | #define GPIO_PAR_FECI2C_RMII_MASK (0x0F) |
| 215 | #define GPIO_PAR_FECI2C_MDC_MASK (0x3F) |
| 216 | #define GPIO_PAR_FECI2C_MDC_MDC (0xC0) |
| 217 | #define GPIO_PAR_FECI2C_MDC_SCL (0x80) |
| 218 | #define GPIO_PAR_FECI2C_MDC_U2TXD (0x40) |
| 219 | #define GPIO_PAR_FECI2C_MDIO_MASK (0xCF) |
| 220 | #define GPIO_PAR_FECI2C_MDIO_MDIO (0x30) |
| 221 | #define GPIO_PAR_FECI2C_MDIO_SDA (0x20) |
| 222 | #define GPIO_PAR_FECI2C_MDIO_U2RXD (0x10) |
| 223 | #define GPIO_PAR_FECI2C_I2C_MASK (0xF0) |
| 224 | #define GPIO_PAR_FECI2C_SCL_MASK (0xF3) |
| 225 | #define GPIO_PAR_FECI2C_SCL_SCL (0x0C) |
| 226 | #define GPIO_PAR_FECI2C_SCL_U2RXD (0x04) |
| 227 | #define GPIO_PAR_FECI2C_SDA_MASK (0xFC) |
| 228 | #define GPIO_PAR_FECI2C_SDA_SDA (0x03) |
| 229 | #define GPIO_PAR_FECI2C_SDA_U2TXD (0x01) |
| 230 | |
| 231 | #define GPIO_PAR_QSPI_PCS2_MASK (0x3F) |
| 232 | #define GPIO_PAR_QSPI_PCS2_PCS2 (0xC0) |
| 233 | #define GPIO_PAR_QSPI_PCS2_DACK0 (0x80) |
| 234 | #define GPIO_PAR_QSPI_PCS2_U2RTS (0x40) |
| 235 | #define GPIO_PAR_QSPI_DIN_MASK (0xCF) |
| 236 | #define GPIO_PAR_QSPI_DIN_DIN (0x30) |
| 237 | #define GPIO_PAR_QSPI_DIN_DREQ0 (0x20) |
| 238 | #define GPIO_PAR_QSPI_DIN_U2CTS (0x10) |
| 239 | #define GPIO_PAR_QSPI_DOUT_MASK (0xF3) |
| 240 | #define GPIO_PAR_QSPI_DOUT_DOUT (0x0C) |
| 241 | #define GPIO_PAR_QSPI_DOUT_SDA (0x08) |
| 242 | #define GPIO_PAR_QSPI_SCK_MASK (0xFC) |
| 243 | #define GPIO_PAR_QSPI_SCK_SCK (0x03) |
| 244 | #define GPIO_PAR_QSPI_SCK_SCL (0x02) |
| 245 | |
| 246 | #define GPIO_PAR_TMR_TIN3(x) (((x) & 0x03) << 6) |
| 247 | #define GPIO_PAR_TMR_TIN2(x) (((x) & 0x03) << 4) |
| 248 | #define GPIO_PAR_TMR_TIN1(x) (((x) & 0x03) << 2) |
| 249 | #define GPIO_PAR_TMR_TIN0(x) ((x) & 0x03) |
| 250 | #define GPIO_PAR_TMR_TIN3_MASK (0x3F) |
| 251 | #define GPIO_PAR_TMR_TIN3_TIN3 (0xC0) |
| 252 | #define GPIO_PAR_TMR_TIN3_TOUT3 (0x80) |
| 253 | #define GPIO_PAR_TMR_TIN3_U2CTS (0x40) |
| 254 | #define GPIO_PAR_TMR_TIN2_MASK (0xCF) |
| 255 | #define GPIO_PAR_TMR_TIN2_TIN2 (0x30) |
| 256 | #define GPIO_PAR_TMR_TIN2_TOUT2 (0x20) |
| 257 | #define GPIO_PAR_TMR_TIN2_U2RTS (0x10) |
| 258 | #define GPIO_PAR_TMR_TIN1_MASK (0xF3) |
| 259 | #define GPIO_PAR_TMR_TIN1_TIN1 (0x0C) |
| 260 | #define GPIO_PAR_TMR_TIN1_TOUT1 (0x08) |
| 261 | #define GPIO_PAR_TMR_TIN1_U2RXD (0x04) |
| 262 | #define GPIO_PAR_TMR_TIN0_MASK (0xFC) |
| 263 | #define GPIO_PAR_TMR_TIN0_TIN0 (0x03) |
| 264 | #define GPIO_PAR_TMR_TIN0_TOUT0 (0x02) |
| 265 | #define GPIO_PAR_TMR_TIN0_U2TXD (0x01) |
| 266 | |
| 267 | #define GPIO_PAR_UART1_MASK (0xF03F) |
| 268 | #define GPIO_PAR_UART0_MASK (0xFFC0) |
| 269 | #define GPIO_PAR_UART_U1CTS_MASK (0xF3FF) |
| 270 | #define GPIO_PAR_UART_U1CTS_U1CTS (0x0C00) |
| 271 | #define GPIO_PAR_UART_U1CTS_TIN1 (0x0800) |
| 272 | #define GPIO_PAR_UART_U1CTS_PCS1 (0x0400) |
| 273 | #define GPIO_PAR_UART_U1RTS_MASK (0xFCFF) |
| 274 | #define GPIO_PAR_UART_U1RTS_U1RTS (0x0300) |
| 275 | #define GPIO_PAR_UART_U1RTS_TOUT1 (0x0200) |
| 276 | #define GPIO_PAR_UART_U1RTS_PCS1 (0x0100) |
| 277 | #define GPIO_PAR_UART_U1TXD (0x0080) |
| 278 | #define GPIO_PAR_UART_U1RXD (0x0040) |
| 279 | #define GPIO_PAR_UART_U0CTS_MASK (0xFFCF) |
| 280 | #define GPIO_PAR_UART_U0CTS_U0CTS (0x0030) |
| 281 | #define GPIO_PAR_UART_U0CTS_TIN0 (0x0020) |
| 282 | #define GPIO_PAR_UART_U0CTS_PCS0 (0x0010) |
| 283 | #define GPIO_PAR_UART_U0RTS_MASK (0xFFF3) |
| 284 | #define GPIO_PAR_UART_U0RTS_U0RTS (0x000C) |
| 285 | #define GPIO_PAR_UART_U0RTS_TOUT0 (0x0008) |
| 286 | #define GPIO_PAR_UART_U0RTS_PCS0 (0x0004) |
| 287 | #define GPIO_PAR_UART_U0TXD (0x0002) |
| 288 | #define GPIO_PAR_UART_U0RXD (0x0001) |
| 289 | |
| 290 | #define GPIO_PAR_FEC_7W_MASK (0xF3) |
| 291 | #define GPIO_PAR_FEC_7W_FEC (0x0C) |
| 292 | #define GPIO_PAR_FEC_7W_U1RTS (0x04) |
| 293 | #define GPIO_PAR_FEC_MII_MASK (0xFC) |
| 294 | #define GPIO_PAR_FEC_MII_FEC (0x03) |
| 295 | #define GPIO_PAR_FEC_MII_UnCTS (0x01) |
| 296 | |
| 297 | #define GPIO_PAR_IRQ_IRQ4 (0x01) |
| 298 | |
| 299 | #define GPIO_MSCR_FB_FBCLK(x) (((x) & 0x03) << 6) |
| 300 | #define GPIO_MSCR_FB_DUP(x) (((x) & 0x03) << 4) |
| 301 | #define GPIO_MSCR_FB_DLO(x) (((x) & 0x03) << 2) |
| 302 | #define GPIO_MSCR_FB_ADRCTL(x) ((x) & 0x03) |
| 303 | #define GPIO_MSCR_FB_FBCLK_MASK (0x3F) |
| 304 | #define GPIO_MSCR_FB_DUP_MASK (0xCF) |
| 305 | #define GPIO_MSCR_FB_DLO_MASK (0xF3) |
| 306 | #define GPIO_MSCR_FB_ADRCTL_MASK (0xFC) |
| 307 | |
| 308 | #define GPIO_MSCR_SDR_SDCLKB(x) (((x) & 0x03) << 4) |
| 309 | #define GPIO_MSCR_SDR_SDCLK(x) (((x) & 0x03) << 2) |
| 310 | #define GPIO_MSCR_SDR_SDRAM(x) ((x) & 0x03) |
| 311 | #define GPIO_MSCR_SDR_SDCLKB_MASK (0xCF) |
| 312 | #define GPIO_MSCR_SDR_SDCLK_MASK (0xF3) |
| 313 | #define GPIO_MSCR_SDR_SDRAM_MASK (0xFC) |
| 314 | |
| 315 | #define MSCR_25VDDR (0x03) |
| 316 | #define MSCR_18VDDR_FULL (0x02) |
| 317 | #define MSCR_OPENDRAIN (0x01) |
| 318 | #define MSCR_18VDDR_HALF (0x00) |
| 319 | |
| 320 | #define GPIO_DSCR_I2C(x) ((x) & 0x03) |
| 321 | #define GPIO_DSCR_I2C_MASK (0xFC) |
| 322 | |
| 323 | #define GPIO_DSCR_MISC_DBG(x) (((x) & 0x03) << 4) |
| 324 | #define GPIO_DSCR_MISC_DBG_MASK (0xCF) |
| 325 | #define GPIO_DSCR_MISC_RSTOUT(x) (((x) & 0x03) << 2) |
| 326 | #define GPIO_DSCR_MISC_RSTOUT_MASK (0xF3) |
| 327 | #define GPIO_DSCR_MISC_TIMER(x) ((x) & 0x03) |
| 328 | #define GPIO_DSCR_MISC_TIMER_MASK (0xFC) |
| 329 | |
| 330 | #define GPIO_DSCR_FEC(x) ((x) & 0x03) |
| 331 | #define GPIO_DSCR_FEC_MASK (0xFC) |
| 332 | |
| 333 | #define GPIO_DSCR_UART_UART1(x) (((x) & 0x03) << 4) |
| 334 | #define GPIO_DSCR_UART_UART1_MASK (0xCF) |
| 335 | #define GPIO_DSCR_UART_UART0(x) (((x) & 0x03) << 2) |
| 336 | #define GPIO_DSCR_UART_UART0_MASK (0xF3) |
| 337 | #define GPIO_DSCR_UART_IRQ(x) ((x) & 0x03) |
| 338 | #define GPIO_DSCR_UART_IRQ_MASK (0xFC) |
| 339 | |
| 340 | #define GPIO_DSCR_QSPI(x) ((x) & 0x03) |
| 341 | #define GPIO_DSCR_QSPI_MASK (0xFC) |
| 342 | |
| 343 | #define DSCR_50PF (0x03) |
| 344 | #define DSCR_30PF (0x02) |
| 345 | #define DSCR_20PF (0x01) |
| 346 | #define DSCR_10PF (0x00) |
| 347 | |
| 348 | /* *** Phase Locked Loop (PLL) *** */ |
| 349 | #define PLL_PODR_CPUDIV(x) (((x) & 0x0F) << 4) |
| 350 | #define PLL_PODR_CPUDIV_MASK (0x0F) |
| 351 | #define PLL_PODR_BUSDIV(x) ((x) & 0x0F) |
| 352 | #define PLL_PODR_BUSDIV_MASK (0xF0) |
| 353 | |
| 354 | #define PLL_PCR_DITHEN (0x80) |
| 355 | #define PLL_PCR_DITHDEV(x) ((x) & 0x07) |
| 356 | #define PLL_PCR_DITHDEV_MASK (0xF8) |
| 357 | |
| 358 | #endif /* __M520X__ */ |