blob: 194e43ecc612682d9b76366c3a0d94b417852a61 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefano Babicd81b27a2012-10-10 21:11:46 +00002/*
3 * (C) Copyright 2011, Stefano Babic <sbabic@denx.de>
4 *
5 * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
6 *
7 * Configuration for the woodburn board.
Stefano Babicd81b27a2012-10-10 21:11:46 +00008 */
9
10#ifndef __WOODBURN_COMMON_CONFIG_H
11#define __WOODBURN_COMMON_CONFIG_H
12
13#include <asm/arch/imx-regs.h>
14
15 /* High Level Configuration Options */
Stefano Babicd81b27a2012-10-10 21:11:46 +000016#define CONFIG_MX35
17#define CONFIG_MX35_HCLK_FREQ 24000000
Gong Qianyu18fb0e32015-10-26 19:47:42 +080018#define CONFIG_SYS_FSL_CLK
Stefano Babicd81b27a2012-10-10 21:11:46 +000019
Stefano Babicd81b27a2012-10-10 21:11:46 +000020#define CONFIG_MACH_TYPE MACH_TYPE_FLEA3
21
22/* This is required to setup the ESDC controller */
23
24#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
25#define CONFIG_REVISION_TAG
26#define CONFIG_SETUP_MEMORY_TAGS
27#define CONFIG_INITRD_TAG
28
29/*
30 * Size of malloc() pool
31 */
32#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
33
34/*
35 * Hardware drivers
36 */
tremb089d032013-09-21 18:13:36 +020037#define CONFIG_SYS_I2C
38#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)03544c62015-09-21 22:43:38 +020039#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
40#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
York Sunf8cb1012015-03-20 10:20:40 -070041#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
tremb089d032013-09-21 18:13:36 +020042#define CONFIG_SYS_SPD_BUS_NUM 0
Stefano Babicd81b27a2012-10-10 21:11:46 +000043
44/* PMIC Controller */
Stefano Babic05a860c2012-12-08 12:02:45 +010045#define CONFIG_POWER
46#define CONFIG_POWER_I2C
47#define CONFIG_POWER_FSL
Simon Glass913702c2014-05-20 06:01:34 -060048#define CONFIG_POWER_FSL_MC13892
Stefano Babicd81b27a2012-10-10 21:11:46 +000049#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8
50#define CONFIG_RTC_MC13XXX
51
Stefano Babicd81b27a2012-10-10 21:11:46 +000052/* mmc driver */
Stefano Babicd81b27a2012-10-10 21:11:46 +000053#define CONFIG_SYS_FSL_ESDHC_ADDR 0
54#define CONFIG_SYS_FSL_ESDHC_NUM 1
55
56/*
57 * UART (console)
58 */
59#define CONFIG_MXC_UART
60#define CONFIG_MXC_UART_BASE UART1_BASE
61
62/* allow to overwrite serial and ethaddr */
63#define CONFIG_ENV_OVERWRITE
Stefano Babicd81b27a2012-10-10 21:11:46 +000064
65/*
66 * Command definition
67 */
Stefano Babicd81b27a2012-10-10 21:11:46 +000068
Stefano Babicd81b27a2012-10-10 21:11:46 +000069#define CONFIG_NET_RETRY_COUNT 100
70
Stefano Babicd81b27a2012-10-10 21:11:46 +000071
72#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
73
Stefano Babicd81b27a2012-10-10 21:11:46 +000074/*
75 * Ethernet on SOC (FEC)
76 */
77#define CONFIG_FEC_MXC
78#define IMX_FEC_BASE FEC_BASE_ADDR
Stefano Babicd81b27a2012-10-10 21:11:46 +000079#define CONFIG_FEC_MXC_PHYADDR 0x1
80
Stefano Babicd81b27a2012-10-10 21:11:46 +000081#define CONFIG_DISCOVER_PHY
82
83#define CONFIG_ARP_TIMEOUT 200UL
84
85/*
86 * Miscellaneous configurable options
87 */
Stefano Babicd81b27a2012-10-10 21:11:46 +000088
89#define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
90#define CONFIG_SYS_MEMTEST_END 0x10000
91
Stefano Babicd81b27a2012-10-10 21:11:46 +000092#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
93
Stefano Babicd81b27a2012-10-10 21:11:46 +000094/*
Stefano Babicd81b27a2012-10-10 21:11:46 +000095 * Physical Memory Map
96 */
Stefano Babicd81b27a2012-10-10 21:11:46 +000097#define PHYS_SDRAM_1 CSD0_BASE_ADDR
98#define PHYS_SDRAM_1_SIZE (256 * 1024 * 1024)
99
100#define CONFIG_SYS_SDRAM_BASE CSD0_BASE_ADDR
101
102#define CONFIG_SYS_GBL_DATA_OFFSET (LOW_LEVEL_SRAM_STACK - \
103 IRAM_BASE_ADDR - \
104 GENERATED_GBL_DATA_SIZE)
105#define CONFIG_SYS_INIT_SP_ADDR (IRAM_BASE_ADDR + \
106 CONFIG_SYS_GBL_DATA_OFFSET)
107
108/*
109 * MTD Command for mtdparts
110 */
Stefano Babicd81b27a2012-10-10 21:11:46 +0000111
112/*
113 * FLASH and environment organization
114 */
115#define CONFIG_SYS_FLASH_BASE CS0_BASE_ADDR
116#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
117#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
118/* Monitor at beginning of flash */
119#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
120#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
121
Stefano Babicd81b27a2012-10-10 21:11:46 +0000122/* Address and size of Redundant Environment Sector */
Stefano Babicd81b27a2012-10-10 21:11:46 +0000123
Stefano Babicd81b27a2012-10-10 21:11:46 +0000124/*
125 * CFI FLASH driver setup
126 */
Stefano Babicd81b27a2012-10-10 21:11:46 +0000127
128/* A non-standard buffered write algorithm */
Stefano Babicd81b27a2012-10-10 21:11:46 +0000129
130/*
131 * NAND FLASH driver setup
132 */
Stefano Babicd81b27a2012-10-10 21:11:46 +0000133#define CONFIG_NAND_MXC_V1_1
134#define CONFIG_MXC_NAND_REGS_BASE (NFC_BASE_ADDR)
135#define CONFIG_SYS_MAX_NAND_DEVICE 1
136#define CONFIG_SYS_NAND_BASE (NFC_BASE_ADDR)
137#define CONFIG_MXC_NAND_HWECC
138#define CONFIG_SYS_NAND_LARGEPAGE
139
Stefano Babicd81b27a2012-10-10 21:11:46 +0000140#define CONFIG_SYS_NAND_ONFI_DETECTION
141
142/*
143 * Default environment and default scripts
144 * to update uboot and load kernel
145 */
Stefano Babicd81b27a2012-10-10 21:11:46 +0000146
Mario Six5bc05432018-03-28 14:38:20 +0200147#define CONFIG_HOSTNAME "woodburn"
Stefano Babicd81b27a2012-10-10 21:11:46 +0000148#define CONFIG_EXTRA_ENV_SETTINGS \
149 "netdev=eth0\0" \
150 "nfsargs=setenv bootargs root=/dev/nfs rw " \
151 "nfsroot=${serverip}:${rootpath}\0" \
152 "ramargs=setenv bootargs root=/dev/ram rw\0" \
153 "addip_sta=setenv bootargs ${bootargs} " \
154 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
155 ":${hostname}:${netdev}:off panic=1\0" \
156 "addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
157 "addip=if test -n ${ipdyn};then run addip_dyn;" \
158 "else run addip_sta;fi\0" \
159 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
160 "addtty=setenv bootargs ${bootargs}" \
161 " console=ttymxc0,${baudrate}\0" \
162 "addmisc=setenv bootargs ${bootargs} ${misc}\0" \
163 "loadaddr=80800000\0" \
164 "kernel_addr_r=80800000\0" \
Mario Six5bc05432018-03-28 14:38:20 +0200165 "hostname=" CONFIG_HOSTNAME "\0" \
166 "bootfile=" CONFIG_HOSTNAME "/uImage\0" \
167 "ramdisk_file=" CONFIG_HOSTNAME "/uRamdisk\0" \
Stefano Babicd81b27a2012-10-10 21:11:46 +0000168 "flash_self=run ramargs addip addtty addmtd addmisc;" \
169 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
170 "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
171 "bootm ${kernel_addr}\0" \
172 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \
173 "run nfsargs addip addtty addmtd addmisc;" \
174 "bootm ${kernel_addr_r}\0" \
175 "net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
176 "tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
177 "net_self=if run net_self_load;then " \
178 "run ramargs addip addtty addmtd addmisc;" \
179 "bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
180 "else echo Images not loades;fi\0" \
Mario Six5bc05432018-03-28 14:38:20 +0200181 "u-boot=" CONFIG_HOSTNAME "/u-boot.bin\0" \
Stefano Babicd81b27a2012-10-10 21:11:46 +0000182 "load=tftp ${loadaddr} ${u-boot}\0" \
Anatolij Gustschin4a8c3f62014-10-24 20:13:51 +0200183 "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
Stefano Babicd81b27a2012-10-10 21:11:46 +0000184 "update=protect off ${uboot_addr} +80000;" \
185 "erase ${uboot_addr} +80000;" \
186 "cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
187 "upd=if run load;then echo Updating u-boot;if run update;" \
188 "then echo U-Boot updated;" \
189 "else echo Error updating u-boot !;" \
190 "echo Board without bootloader !!;" \
191 "fi;" \
192 "else echo U-Boot not downloaded..exiting;fi\0" \
193 "bootcmd=run net_nfs\0"
194
195#endif /* __CONFIG_H */