blob: 140999994b1aac20dcf90595bb20f699f3ec6b1d [file] [log] [blame]
Patrice Chotardc0cdd5a2017-12-12 09:49:44 +01001/*
2 * Copyright (C) STMicroelectronics SA 2017
3 * Author(s): Patrice CHOTARD, <patrice.chotard@st.com> for STMicroelectronics.
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_STM32F4DISCOVERY
12
13#define CONFIG_MISC_INIT_R
14
15#define CONFIG_SYS_FLASH_BASE 0x08000000
16
17#define CONFIG_SYS_INIT_SP_ADDR 0x10010000
18#define CONFIG_SYS_TEXT_BASE 0x08000000
19
20#define CONFIG_SYS_ICACHE_OFF
21#define CONFIG_SYS_DCACHE_OFF
22
23/*
24 * Configuration of the external SDRAM memory
25 */
26#define CONFIG_NR_DRAM_BANKS 1
27#define CONFIG_SYS_RAM_FREQ_DIV 2
28#define CONFIG_SYS_RAM_BASE 0x00000000
29#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_RAM_BASE
30#define CONFIG_SYS_LOAD_ADDR 0x00400000
31#define CONFIG_LOADADDR 0x00400000
32
33#define CONFIG_SYS_MAX_FLASH_SECT 12
34#define CONFIG_SYS_MAX_FLASH_BANKS 2
35
36#define CONFIG_ENV_OFFSET (256 << 10)
37#define CONFIG_ENV_SECT_SIZE (128 << 10)
38#define CONFIG_ENV_SIZE (8 << 10)
39
40#define CONFIG_STM32_FLASH
41
42#define CONFIG_STM32_HSE_HZ 8000000
43#define CONFIG_SYS_CLK_FREQ 180000000 /* 180 MHz */
44#define CONFIG_SYS_HZ_CLOCK 1000000 /* Timer is clocked at 1MHz */
45
46#define CONFIG_CMDLINE_TAG
47#define CONFIG_SETUP_MEMORY_TAGS
48#define CONFIG_INITRD_TAG
49#define CONFIG_REVISION_TAG
50
51#define CONFIG_SYS_CBSIZE 1024
52
53#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024)
54
55#define CONFIG_BOOTCOMMAND \
56 "run boot_sd"
57
58#define CONFIG_EXTRA_ENV_SETTINGS \
59 "boot_sd=mmc dev 0;fatload mmc 0 0x00700000 stm32f469-disco.dtb; fatload mmc 0 0x00008000 zImage; icache off; bootz 0x00008000 - 0x00700000"
60
61/*
62 * Command line configuration.
63 */
64#define CONFIG_SYS_LONGHELP
65#define CONFIG_AUTO_COMPLETE
66#define CONFIG_CMDLINE_EDITING
67
68#endif /* __CONFIG_H */