blob: c03894a265afe9806bb705eabd8a98f1a2904ce1 [file] [log] [blame]
Shengzhou Liu48c6f322014-11-24 17:11:56 +08001/**
2 * Copyright 2014 Freescale Semiconductor
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 *
6 * Freescale T1024RDB board-specific CPLD controlling supports.
7 *
8 * The following macros need to be defined:
9 */
10
11#include <common.h>
12#include <command.h>
13#include <asm/io.h>
14#include "cpld.h"
15
16u8 cpld_read(unsigned int reg)
17{
18 void *p = (void *)CONFIG_SYS_CPLD_BASE;
19
20 return in_8(p + reg);
21}
22
23void cpld_write(unsigned int reg, u8 value)
24{
25 void *p = (void *)CONFIG_SYS_CPLD_BASE;
26
27 out_8(p + reg, value);
28}
29
30/**
31 * Set the boot bank to the alternate bank
32 */
33void cpld_set_altbank(void)
34{
35 u8 reg = CPLD_READ(flash_csr);
36
37 reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
38
39 CPLD_WRITE(flash_csr, reg);
40 CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
41}
42
43/**
44 * Set the boot bank to the default bank
45 */
46void cpld_set_defbank(void)
47{
48 u8 reg = CPLD_READ(flash_csr);
49
50 reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_DFLTBANK;
51
52 CPLD_WRITE(flash_csr, reg);
53 CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
54}
55
56static void cpld_dump_regs(void)
57{
58 printf("cpld_ver = 0x%02x\n", CPLD_READ(cpld_ver));
59 printf("cpld_ver_sub = 0x%02x\n", CPLD_READ(cpld_ver_sub));
60 printf("hw_ver = 0x%02x\n", CPLD_READ(hw_ver));
61 printf("sw_ver = 0x%02x\n", CPLD_READ(sw_ver));
62 printf("reset_ctl1 = 0x%02x\n", CPLD_READ(reset_ctl1));
63 printf("reset_ctl2 = 0x%02x\n", CPLD_READ(reset_ctl2));
64 printf("int_status = 0x%02x\n", CPLD_READ(int_status));
65 printf("flash_csr = 0x%02x\n", CPLD_READ(flash_csr));
66 printf("fan_ctl_status = 0x%02x\n", CPLD_READ(fan_ctl_status));
67 printf("led_ctl_status = 0x%02x\n", CPLD_READ(led_ctl_status));
68 printf("sfp_ctl_status = 0x%02x\n", CPLD_READ(sfp_ctl_status));
69 printf("misc_ctl_status = 0x%02x\n", CPLD_READ(misc_ctl_status));
70 printf("boot_override = 0x%02x\n", CPLD_READ(boot_override));
71 printf("boot_config1 = 0x%02x\n", CPLD_READ(boot_config1));
72 printf("boot_config2 = 0x%02x\n", CPLD_READ(boot_config2));
73 putc('\n');
74}
75
76int do_cpld(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
77{
78 int rc = 0;
79
80 if (argc <= 1)
81 return cmd_usage(cmdtp);
82
83 if (strcmp(argv[1], "reset") == 0) {
84 if (strcmp(argv[2], "altbank") == 0)
85 cpld_set_altbank();
86 else
87 cpld_set_defbank();
88 } else if (strcmp(argv[1], "dump") == 0) {
89 cpld_dump_regs();
90 } else {
91 rc = cmd_usage(cmdtp);
92 }
93
94 return rc;
95}
96
97U_BOOT_CMD(
98 cpld, CONFIG_SYS_MAXARGS, 1, do_cpld,
99 "Reset the board or alternate bank",
100 "reset - hard reset to default bank\n"
101 "cpld reset altbank - reset to alternate bank\n"
102 "cpld dump - display the CPLD registers\n"
103 );