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Stefan Roese6e7fb6e2005-11-29 18:18:21 +01001/*
2 * (C) Copyright 2005
3 * John Otken, jotken@softadvances.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <command.h>
26#include <ppc4xx.h>
27#include <asm/processor.h>
28#include <spd_sdram.h>
29#include "epld.h"
30
Wolfgang Denkd87080b2006-03-31 18:32:53 +020031DECLARE_GLOBAL_DATA_PTR;
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010032
33extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
34
35
36/*************************************************************************
37 * int board_early_init_f()
38 *
39 ************************************************************************/
40int board_early_init_f(void)
41{
Stefan Roesea27044b2007-12-06 05:58:43 +010042 u32 mfr;
43
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010044 mtebc( pb0ap, 0x03800000 ); /* set chip selects */
45 mtebc( pb0cr, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */
46 mtebc( pb1ap, 0x03800000 );
47 mtebc( pb1cr, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */
48 mtebc( pb2ap, 0x03800000 );
49 mtebc( pb2cr, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */
50
51 mtdcr( uic1sr, 0xffffffff ); /* Clear all interrupts */
52 mtdcr( uic1er, 0x00000000 ); /* disable all interrupts */
53 mtdcr( uic1cr, 0x00000000 ); /* Set Critical / Non Critical interrupts */
54 mtdcr( uic1pr, 0x7fff83ff ); /* Set Interrupt Polarities */
55 mtdcr( uic1tr, 0x001f8000 ); /* Set Interrupt Trigger Levels */
56 mtdcr( uic1vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
57 mtdcr( uic1sr, 0x00000000 ); /* clear all interrupts */
58 mtdcr( uic1sr, 0xffffffff );
59
60 mtdcr( uic0sr, 0xffffffff ); /* Clear all interrupts */
61 mtdcr( uic0er, 0x00000000 ); /* disable all interrupts excepted cascade */
62 mtdcr( uic0cr, 0x00000001 ); /* Set Critical / Non Critical interrupts */
63 mtdcr( uic0pr, 0xffffffff ); /* Set Interrupt Polarities */
64 mtdcr( uic0tr, 0x01000004 ); /* Set Interrupt Trigger Levels */
65 mtdcr( uic0vr, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */
66 mtdcr( uic0sr, 0x00000000 ); /* clear all interrupts */
67 mtdcr( uic0sr, 0xffffffff );
68
Stefan Roesea27044b2007-12-06 05:58:43 +010069 mfsdr(sdr_mfr, mfr);
70 mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */
71 mtsdr(sdr_mfr, mfr);
72
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010073 return 0;
74}
75
76
77/*************************************************************************
78 * int misc_init_r()
79 *
80 ************************************************************************/
81int misc_init_r(void)
82{
83 volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
Grzegorz Bernacki2db64782007-10-01 09:51:50 +020084
85 /* set modes of operation */
86 x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
87 EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE;
88 /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */
89 x->ethuart &= ~EPLD2_ETH_AUTO_NEGO;
Stefan Roese738815c2007-10-02 11:44:46 +020090
Grzegorz Bernacki2db64782007-10-01 09:51:50 +020091 /* put Ethernet+PHY in reset */
92 x->ethuart &= ~EPLD2_RESET_ETH_N;
93 udelay(10000);
94 /* take Ethernet+PHY out of reset */
95 x->ethuart |= EPLD2_RESET_ETH_N;
Stefan Roese6e7fb6e2005-11-29 18:18:21 +010096
97 return 0;
98}
99
100
101/*************************************************************************
102 * int checkboard()
103 *
104 ************************************************************************/
105int checkboard(void)
106{
107 char *s = getenv("serial#");
108
109 printf("Board: Luan - AMCC PPC440SP Evaluation Board");
110
111 if (s != NULL) {
112 puts(", serial# ");
113 puts(s);
114 }
115 putc('\n');
116
117 return 0;
118}
119
Stefan Roese2a49fc12007-07-16 10:01:38 +0200120/*
121 * Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
122 * board specific values.
123 */
124u32 ddr_clktr(u32 default_val) {
125 return (SDRAM_CLKTR_CLKP_180_DEG_ADV);
126}
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100127
128/*************************************************************************
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100129 * pci_pre_init
130 *
131 * This routine is called just prior to registering the hose and gives
132 * the board the opportunity to check things. Returning a value of zero
133 * indicates that things are bad & PCI initialization should be aborted.
134 *
135 * Different boards may wish to customize the pci controller structure
136 * (add regions, override default access routines, etc) or perform
137 * certain pre-initialization actions.
138 *
139 ************************************************************************/
Stefan Roese466fff12007-06-25 15:57:39 +0200140#if defined(CONFIG_PCI)
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100141int pci_pre_init( struct pci_controller *hose )
142{
143 unsigned long strap;
144
145 /*--------------------------------------------------------------------------+
146 * The luan board is always configured as the host & requires the
147 * PCI arbiter to be enabled.
148 *--------------------------------------------------------------------------*/
149 mfsdr(sdr_sdstp1, strap);
150 if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) {
151 printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
152
153 return 0;
154 }
155
156 return 1;
157}
Stefan Roese466fff12007-06-25 15:57:39 +0200158#endif /* defined(CONFIG_PCI) */
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100159
160
161/*************************************************************************
162 * pci_target_init
163 *
164 * The bootstrap configuration provides default settings for the pci
165 * inbound map (PIM). But the bootstrap config choices are limited and
166 * may not be sufficient for a given board.
167 *
168 ************************************************************************/
169#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
170void pci_target_init(struct pci_controller *hose)
171{
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100172 /*--------------------------------------------------------------------------+
173 * Disable everything
174 *--------------------------------------------------------------------------*/
175 out32r( PCIX0_PIM0SA, 0 ); /* disable */
176 out32r( PCIX0_PIM1SA, 0 ); /* disable */
177 out32r( PCIX0_PIM2SA, 0 ); /* disable */
178 out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
179
180 /*--------------------------------------------------------------------------+
181 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
182 * options to not support sizes such as 128/256 MB.
183 *--------------------------------------------------------------------------*/
184 out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
185 out32r( PCIX0_PIM0LAH, 0 );
186 out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
187
188 out32r( PCIX0_BAR0, 0 );
189
190 /*--------------------------------------------------------------------------+
191 * Program the board's subsystem id/vendor id
192 *--------------------------------------------------------------------------*/
193 out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
194 out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
195
196 out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
197}
198#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
199
200
201/*************************************************************************
202 * is_pci_host
203 *
204 * This routine is called to determine if a pci scan should be
205 * performed. With various hardware environments (especially cPCI and
206 * PPMC) it's insufficient to depend on the state of the arbiter enable
207 * bit in the strap register, or generic host/adapter assumptions.
208 *
209 * Rather than hard-code a bad assumption in the general 440 code, the
210 * 440 pci code requires the board to decide at runtime.
211 *
212 * Return 0 for adapter mode, non-zero for host (monarch) mode.
213 *
214 *
215 ************************************************************************/
216#if defined(CONFIG_PCI)
217int is_pci_host(struct pci_controller *hose)
218{
219 return 1;
220}
221#endif /* defined(CONFIG_PCI) */
222
223
224/*************************************************************************
225 * hw_watchdog_reset
226 *
227 * This routine is called to reset (keep alive) the watchdog timer
228 *
229 ************************************************************************/
230#if defined(CONFIG_HW_WATCHDOG)
231void hw_watchdog_reset(void)
232{
233}
234#endif
235
236
237/*************************************************************************
238 * int on_off()
239 *
240 ************************************************************************/
241static int on_off( const char *s )
242{
243 if (strcmp(s, "on") == 0) {
244 return 1;
245 } else if (strcmp(s, "off") == 0) {
246 return 0;
247 }
248 return -1;
249}
250
251
252/*************************************************************************
253 * void l2cache_disable()
254 *
255 ************************************************************************/
256static void l2cache_disable(void)
257{
258 mtdcr( l2_cache_cfg, 0 );
259}
260
261
262/*************************************************************************
263 * void l2cache_enable()
264 *
265 ************************************************************************/
266static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */
267{
268 mtdcr( l2_cache_cfg, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */
269
270 mtdcr( l2_cache_addr, 0 ); /* set L2_ADDR with all zeros */
271
272 mtdcr( l2_cache_cmd, 0x80000000 ); /* issue HCLEAR command via L2_CMD */
273
274 while (!(mfdcr( l2_cache_stat ) & 0x80000000 )) ;; /* poll L2_SR for completion */
275
276 mtdcr( l2_cache_cmd, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */
277
278 mtdcr( l2_cache_cmd, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */
279
280 mtdcr( l2_cache_snp0, 0 ); /* snoop registers */
281 mtdcr( l2_cache_snp1, 0 );
282
283 __asm__ volatile ("sync"); /* msync */
284
285 mtdcr( l2_cache_cfg, 0xe0000000 ); /* inst and data use L2 */
286
287 __asm__ volatile ("sync");
288}
289
290
291/*************************************************************************
292 * int l2cache_status()
293 *
294 ************************************************************************/
295static int l2cache_status(void)
296{
297 return (mfdcr( l2_cache_cfg ) & 0x60000000) != 0;
298}
299
300
301/*************************************************************************
302 * int do_l2cache()
303 *
304 ************************************************************************/
305int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[] )
306{
307 switch (argc) {
308 case 2: /* on / off */
309 switch (on_off(argv[1])) {
310 case 0: l2cache_disable();
311 break;
312 case 1: l2cache_enable();
313 break;
314 }
315 /* FALL TROUGH */
316 case 1: /* get status */
317 printf ("L2 Cache is %s\n",
318 l2cache_status() ? "ON" : "OFF");
319 return 0;
320 default:
321 printf ("Usage:\n%s\n", cmdtp->usage);
322 return 1;
323 }
324
325 return 0;
326}
327
328
329U_BOOT_CMD(
330 l2cache, 2, 1, do_l2cache,
331 "l2cache - enable or disable L2 cache\n",
332 "[on, off]\n"
333 " - enable or disable L2 cache\n"
334 );