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Dirk Eibach255ef4d2011-10-20 11:12:55 +02001/*
2 * (C) Copyright 2011
3 * Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
4 *
5 * based on kilauea.h
6 * by Stefan Roese, DENX Software Engineering, sr@denx.de.
7 * and Grant Erickson <gerickson@nuovations.com>
8 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02009 * SPDX-License-Identifier: GPL-2.0+
Dirk Eibach255ef4d2011-10-20 11:12:55 +020010 */
11
12/************************************************************************
13 * io64.h - configuration for Guntermann & Drunck Io64 (405EX)
14 ***********************************************************************/
15
16#ifndef __CONFIG_H
17#define __CONFIG_H
18
19/*-----------------------------------------------------------------------
20 * High Level Configuration Options
21 *----------------------------------------------------------------------*/
22#define CONFIG_IO64 1 /* Board is Io64 */
Dirk Eibach255ef4d2011-10-20 11:12:55 +020023#define CONFIG_405EX 1 /* Specifc 405EX support*/
24#define CONFIG_SYS_CLK_FREQ 33333333 /* ext frequency to pll */
25
26#ifndef CONFIG_SYS_TEXT_BASE
27#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
28#endif
29
30/*
31 * CHIP_21 errata
32 */
33#define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
34
35/*
36 * Include common defines/options for all AMCC eval boards
37 */
38#define CONFIG_HOSTNAME io64
Dirk Eibach255ef4d2011-10-20 11:12:55 +020039#include "amcc-common.h"
40
Dirk Eibach255ef4d2011-10-20 11:12:55 +020041#define CONFIG_BOARD_EARLY_INIT_R
42#define CONFIG_MISC_INIT_R
43#define CONFIG_LAST_STAGE_INIT
44
Dirk Eibach255ef4d2011-10-20 11:12:55 +020045/*-----------------------------------------------------------------------
46 * Base addresses -- Note these are effective addresses where the
47 * actual resources get mapped (not physical addresses)
48 *----------------------------------------------------------------------*/
49#define CONFIG_SYS_FLASH_BASE 0xFC000000
50#define CONFIG_SYS_NVRAM_BASE 0xF0000000
51#define CONFIG_SYS_FPGA0_BASE 0xF0100000
52#define CONFIG_SYS_FPGA1_BASE 0xF0108000
53#define CONFIG_SYS_LATCH_BASE 0xF0200000
54
55/*-----------------------------------------------------------------------
56 * Initial RAM & Stack Pointer Configuration Options
57 *
58 * There are traditionally three options for the primordial
59 * (i.e. initial) stack usage on the 405-series:
60 *
61 * 1) On-chip Memory (OCM) (i.e. SRAM)
62 * 2) Data cache
63 * 3) SDRAM
64 *
65 * For the 405EX(r), there is no OCM, so we are left with (2) or (3)
66 * the latter of which is less than desireable since it requires
67 * setting up the SDRAM and ECC in assembly code.
68 *
69 * To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
70 * select on the External Bus Controller (EBC) and then select a
71 * value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
72 * physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
73 * select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
74 * physical SDRAM to use (3).
75 *-----------------------------------------------------------------------*/
76
77#define CONFIG_SYS_INIT_DCACHE_CS 4
78
79#if defined(CONFIG_SYS_INIT_DCACHE_CS)
80#define CONFIG_SYS_INIT_RAM_ADDR \
81 (CONFIG_SYS_SDRAM_BASE + (1 << 30)) /* 1 GiB */
82#else
83#define CONFIG_SYS_INIT_RAM_ADDR \
84 (CONFIG_SYS_SDRAM_BASE + (32 << 20)) /* 32 MiB */
85#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
86
87#define CONFIG_SYS_INIT_RAM_SIZE \
88 (4 << 10) /* 4 KiB */
89#define CONFIG_SYS_GBL_DATA_OFFSET \
90 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
91
92/*
93 * If the data cache is being used for the primordial stack and global
94 * data area, the POST word must be placed somewhere else. The General
95 * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
96 * its compare and mask register contents across reset, so it is used
97 * for the POST word.
98 */
99
100#if defined(CONFIG_SYS_INIT_DCACHE_CS)
101# define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
102# define CONFIG_SYS_POST_WORD_ADDR \
103 (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
104#else
105# define CONFIG_SYS_INIT_EXTRA_SIZE 16
106# define CONFIG_SYS_INIT_SP_OFFSET \
107 (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
108# define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_INIT_RAM_ADDR
109#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
110
111/*-----------------------------------------------------------------------
112 * Serial Port
113 *----------------------------------------------------------------------*/
114#define CONFIG_CONS_INDEX 1 /* Use UART0 */
115#define CONFIG_SYS_BASE_BAUD 691200
116
117/*-----------------------------------------------------------------------
118 * Environment
119 *----------------------------------------------------------------------*/
120#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
121
122/*-----------------------------------------------------------------------
123 * FLASH related
124 *----------------------------------------------------------------------*/
125#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
126#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
127
128#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
129#define CONFIG_SYS_MAX_FLASH_BANKS 1
130#define CONFIG_SYS_MAX_FLASH_SECT 512
131
132#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
133#define CONFIG_SYS_FLASH_WRITE_TOUT 500
134
135#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
136#define CONFIG_SYS_FLASH_EMPTY_INFO
137
138#ifdef CONFIG_ENV_IS_IN_FLASH
139#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
140#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
141#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
142
143/* Address and size of Redundant Environment Sector */
144#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
145#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
146#endif /* CONFIG_ENV_IS_IN_FLASH */
147
148/* Gbit PHYs */
149#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
150#define CONFIG_BITBANGMII_MULTI
151
152#define CONFIG_SYS_MDIO_PIN (0x80000000 >> 12) /* MDIO is GPIO12 */
153#define CONFIG_SYS_MDC_PIN (0x80000000 >> 13) /* MDC is GPIO13 */
154
155#define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy0"
156
157#define CONFIG_SYS_MDIO1_PIN (0x80000000 >> 2) /* MDIO is GPIO2 */
158#define CONFIG_SYS_MDC1_PIN (0x80000000 >> 3) /* MDC is GPIO3 */
159
160#define CONFIG_SYS_GBIT_MII1_BUSNAME "io_miiphy1"
161
162/*-----------------------------------------------------------------------
163 * DDR SDRAM
164 *----------------------------------------------------------------------*/
165#define CONFIG_SYS_MBYTES_SDRAM (128) /* 128MB */
166
167/*
168 * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
169 *
170 * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
171 * SDRAM Controller DDR autocalibration values and takes a lot longer
172 * to run than Method_B.
173 * (See the Method_A and Method_B algorithm discription in the file:
174 * arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
175 * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
176 *
177 * DDR Autocalibration Method_B is the default.
178 */
179#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION
180#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION
181#undef CONFIG_PPC4xx_DDR_METHOD_A
182
183#define CONFIG_SYS_SDRAM0_MB0CF_BASE ((0 << 20) + CONFIG_SYS_SDRAM_BASE)
184
185/* DDR1/2 SDRAM Device Control Register Data Values */
186#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
187 SDRAM_RXBAS_SDSZ_128MB | \
188 SDRAM_RXBAS_SDAM_MODE2 | \
189 SDRAM_RXBAS_SDBE_ENABLE)
190#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
191#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
192#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
193#define CONFIG_SYS_SDRAM0_MCOPT1 (SDRAM_MCOPT1_PMU_OPEN | \
194 SDRAM_MCOPT1_4_BANKS | \
195 SDRAM_MCOPT1_DDR2_TYPE | \
196 SDRAM_MCOPT1_QDEP | \
197 SDRAM_MCOPT1_DCOO_DISABLED)
198#define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
199#define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
200 SDRAM_MODT_EB0R_ENABLE)
201#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
202#define CONFIG_SYS_SDRAM0_CODT (SDRAM_CODT_RK0R_ON | \
203 SDRAM_CODT_CKLZ_36OHM | \
204 SDRAM_CODT_DQS_1_8_V_DDR2 | \
205 SDRAM_CODT_IO_NMODE)
206#define CONFIG_SYS_SDRAM0_RTR SDRAM_RTR_RINT_ENCODE(1560)
207#define CONFIG_SYS_SDRAM0_INITPLR0 (SDRAM_INITPLR_ENABLE | \
208 SDRAM_INITPLR_IMWT_ENCODE(80) | \
209 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
210#define CONFIG_SYS_SDRAM0_INITPLR1 (SDRAM_INITPLR_ENABLE | \
211 SDRAM_INITPLR_IMWT_ENCODE(3) | \
212 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
213 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
214 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
215#define CONFIG_SYS_SDRAM0_INITPLR2 (SDRAM_INITPLR_ENABLE | \
216 SDRAM_INITPLR_IMWT_ENCODE(2) | \
217 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
218 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
219 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
220#define CONFIG_SYS_SDRAM0_INITPLR3 (SDRAM_INITPLR_ENABLE | \
221 SDRAM_INITPLR_IMWT_ENCODE(2) | \
222 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
223 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
224 SDRAM_INITPLR_IMA_ENCODE(0))
225#define CONFIG_SYS_SDRAM0_INITPLR4 (SDRAM_INITPLR_ENABLE | \
226 SDRAM_INITPLR_IMWT_ENCODE(2) | \
227 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
228 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
229 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
230 JEDEC_MA_EMR_RTT_75OHM))
231#define CONFIG_SYS_SDRAM0_INITPLR5 (SDRAM_INITPLR_ENABLE | \
232 SDRAM_INITPLR_IMWT_ENCODE(2) | \
233 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
234 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
235 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
236 JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
237 JEDEC_MA_MR_BLEN_4 | \
238 JEDEC_MA_MR_DLL_RESET))
239#define CONFIG_SYS_SDRAM0_INITPLR6 (SDRAM_INITPLR_ENABLE | \
240 SDRAM_INITPLR_IMWT_ENCODE(3) | \
241 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
242 SDRAM_INITPLR_IBA_ENCODE(0x0) | \
243 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
244#define CONFIG_SYS_SDRAM0_INITPLR7 (SDRAM_INITPLR_ENABLE | \
245 SDRAM_INITPLR_IMWT_ENCODE(26) | \
246 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
247#define CONFIG_SYS_SDRAM0_INITPLR8 (SDRAM_INITPLR_ENABLE | \
248 SDRAM_INITPLR_IMWT_ENCODE(26) | \
249 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
250#define CONFIG_SYS_SDRAM0_INITPLR9 (SDRAM_INITPLR_ENABLE | \
251 SDRAM_INITPLR_IMWT_ENCODE(26) | \
252 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
253#define CONFIG_SYS_SDRAM0_INITPLR10 (SDRAM_INITPLR_ENABLE | \
254 SDRAM_INITPLR_IMWT_ENCODE(26) | \
255 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
256#define CONFIG_SYS_SDRAM0_INITPLR11 (SDRAM_INITPLR_ENABLE | \
257 SDRAM_INITPLR_IMWT_ENCODE(2) | \
258 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
259 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
260 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
261 JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
262 JEDEC_MA_MR_BLEN_4))
263#define CONFIG_SYS_SDRAM0_INITPLR12 (SDRAM_INITPLR_ENABLE | \
264 SDRAM_INITPLR_IMWT_ENCODE(2) | \
265 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
266 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
267 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
268 JEDEC_MA_EMR_RDQS_DISABLE | \
269 JEDEC_MA_EMR_DQS_DISABLE | \
270 JEDEC_MA_EMR_RTT_DISABLED | \
271 JEDEC_MA_EMR_ODS_NORMAL))
272#define CONFIG_SYS_SDRAM0_INITPLR13 (SDRAM_INITPLR_ENABLE | \
273 SDRAM_INITPLR_IMWT_ENCODE(2) | \
274 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
275 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
276 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
277 JEDEC_MA_EMR_RDQS_DISABLE | \
278 JEDEC_MA_EMR_DQS_DISABLE | \
279 JEDEC_MA_EMR_RTT_DISABLED | \
280 JEDEC_MA_EMR_ODS_NORMAL))
281#define CONFIG_SYS_SDRAM0_INITPLR14 (SDRAM_INITPLR_DISABLE)
282#define CONFIG_SYS_SDRAM0_INITPLR15 (SDRAM_INITPLR_DISABLE)
283#define CONFIG_SYS_SDRAM0_RQDC (SDRAM_RQDC_RQDE_ENABLE | \
284 SDRAM_RQDC_RQFD_ENCODE(56))
285#define CONFIG_SYS_SDRAM0_RFDC SDRAM_RFDC_RFFD_ENCODE(521)
286#define CONFIG_SYS_SDRAM0_RDCC (SDRAM_RDCC_RDSS_T2)
287#define CONFIG_SYS_SDRAM0_DLCR (SDRAM_DLCR_DCLM_AUTO | \
288 SDRAM_DLCR_DLCS_CONT_DONE | \
289 SDRAM_DLCR_DLCV_ENCODE(165))
290#define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
291#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
292#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
293 SDRAM_SDTR1_RTW_2_CLK | \
294 SDRAM_SDTR1_WTWO_1_CLK | \
295 SDRAM_SDTR1_RTRO_1_CLK)
296#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
297 SDRAM_SDTR2_WTR_2_CLK | \
298 SDRAM_SDTR2_XSNR_32_CLK | \
299 SDRAM_SDTR2_WPC_4_CLK | \
300 SDRAM_SDTR2_RPC_2_CLK | \
301 SDRAM_SDTR2_RP_3_CLK | \
302 SDRAM_SDTR2_RRD_2_CLK)
303#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(9) | \
304 SDRAM_SDTR3_RC_ENCODE(12) | \
305 SDRAM_SDTR3_XCS | \
306 SDRAM_SDTR3_RFC_ENCODE(21))
307#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
308 SDRAM_MMODE_DCL_DDR2_5_0_CLK | \
309 SDRAM_MMODE_BLEN_4)
310#define CONFIG_SYS_SDRAM0_MEMODE (SDRAM_MEMODE_DQS_DISABLE | \
311 SDRAM_MEMODE_RTT_75OHM)
312
313/*-----------------------------------------------------------------------
314 * I2C
315 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000316#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
Dirk Eibach255ef4d2011-10-20 11:12:55 +0200317
318#define CONFIG_PCA9698 1 /* NXP PCA9698 */
319
320#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 /* I2C boot EEPROM (24C02BN) */
321#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
322#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
323#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
324
325/* I2C bootstrap EEPROM */
326#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
327#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
328#define CONFIG_4xx_CONFIG_BLOCKSIZE 16
329
Dirk Eibach255ef4d2011-10-20 11:12:55 +0200330/*-----------------------------------------------------------------------
331 * Ethernet
332 *----------------------------------------------------------------------*/
333#define CONFIG_M88E1111_PHY 1
334#define CONFIG_IBM_EMAC4_V4 1
335#define CONFIG_EMAC_PHY_MODE EMAC_PHY_MODE_RGMII_RGMII
336#define CONFIG_PHY_ADDR 0x12 /* PHY address, See schematics */
337
338#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
339#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
340
341#define CONFIG_HAS_ETH0 1
342
343#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
344#define CONFIG_PHY1_ADDR 0x13
345
346/* Debug messages for the DDR autocalibration */
347#define CONFIG_AUTOCALIB "silent\0"
348
349/*
350 * Default environment variables
351 */
352#define CONFIG_EXTRA_ENV_SETTINGS \
353 CONFIG_AMCC_DEF_ENV \
354 CONFIG_AMCC_DEF_ENV_POWERPC \
355 CONFIG_AMCC_DEF_ENV_PPC_OLD \
356 CONFIG_AMCC_DEF_ENV_NOR_UPD \
357 "logversion=2\0" \
358 "kernel_addr=fc000000\0" \
359 "fdt_addr=fc1e0000\0" \
360 "ramdisk_addr=fc200000\0" \
361 "pciconfighost=1\0" \
362 "pcie_mode=RP:RP\0" \
363 ""
364
365/*
366 * Commands additional to the ones defined in amcc-common.h
367 */
Dirk Eibach255ef4d2011-10-20 11:12:55 +0200368
369#define CONFIG_SYS_POST_MEMORY_ON CONFIG_SYS_POST_MEMORY
370
371/* POST support */
372#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
373 CONFIG_SYS_POST_CPU | \
374 CONFIG_SYS_POST_ETHER | \
375 CONFIG_SYS_POST_I2C | \
376 CONFIG_SYS_POST_MEMORY_ON | \
377 CONFIG_SYS_POST_UART)
378
379/* Define here the base-addresses of the UARTs to test in POST */
380#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
381 CONFIG_SYS_NS16550_COM2 }
382
383#define CONFIG_LOGBUFFER
384#define CONFIG_SYS_POST_CACHE_ADDR 0x00800000 /* free virtual address */
385
Dirk Eibach255ef4d2011-10-20 11:12:55 +0200386/*-----------------------------------------------------------------------
387 * External Bus Controller (EBC) Setup
388 *----------------------------------------------------------------------*/
389
390/* Memory Bank 0 (NOR-flash) */
391#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
392 EBC_BXAP_TWT_ENCODE(11) | \
393 EBC_BXAP_BCE_DISABLE | \
394 EBC_BXAP_BCT_2TRANS | \
395 EBC_BXAP_CSN_ENCODE(0) | \
396 EBC_BXAP_OEN_ENCODE(0) | \
397 EBC_BXAP_WBN_ENCODE(1) | \
398 EBC_BXAP_WBF_ENCODE(2) | \
399 EBC_BXAP_TH_ENCODE(2) | \
400 EBC_BXAP_RE_DISABLED | \
401 EBC_BXAP_SOR_NONDELAYED | \
402 EBC_BXAP_BEM_WRITEONLY | \
403 EBC_BXAP_PEN_DISABLED)
404#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
405 EBC_BXCR_BS_64MB | \
406 EBC_BXCR_BU_RW | \
407 EBC_BXCR_BW_16BIT)
408
409/* Memory Bank 1 (NVRAM/Uart) */
410#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_ENABLED | \
411 EBC_BXAP_FWT_ENCODE(8) | \
412 EBC_BXAP_BWT_ENCODE(4) | \
413 EBC_BXAP_BCE_DISABLE | \
414 EBC_BXAP_BCT_2TRANS | \
415 EBC_BXAP_CSN_ENCODE(0) | \
416 EBC_BXAP_OEN_ENCODE(1) | \
417 EBC_BXAP_WBN_ENCODE(1) | \
418 EBC_BXAP_WBF_ENCODE(1) | \
419 EBC_BXAP_TH_ENCODE(2) | \
420 EBC_BXAP_RE_DISABLED | \
421 EBC_BXAP_SOR_NONDELAYED | \
422 EBC_BXAP_BEM_WRITEONLY | \
423 EBC_BXAP_PEN_DISABLED)
424#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_NVRAM_BASE) | \
425 EBC_BXCR_BS_1MB | \
426 EBC_BXCR_BU_RW | \
427 EBC_BXCR_BW_8BIT)
428
429/* Memory Bank 2 (FPGA) */
430#define CONFIG_SYS_EBC_PB2AP (EBC_BXAP_BME_DISABLED | \
431 EBC_BXAP_TWT_ENCODE(5) | \
432 EBC_BXAP_BCE_DISABLE | \
433 EBC_BXAP_BCT_2TRANS | \
434 EBC_BXAP_CSN_ENCODE(0) | \
435 EBC_BXAP_OEN_ENCODE(2) | \
436 EBC_BXAP_WBN_ENCODE(1) | \
437 EBC_BXAP_WBF_ENCODE(1) | \
438 EBC_BXAP_TH_ENCODE(0) | \
439 EBC_BXAP_RE_DISABLED | \
440 EBC_BXAP_SOR_NONDELAYED | \
441 EBC_BXAP_BEM_WRITEONLY | \
442 EBC_BXAP_PEN_DISABLED)
443#define CONFIG_SYS_EBC_PB2CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
444 EBC_BXCR_BS_1MB | \
445 EBC_BXCR_BU_RW | \
446 EBC_BXCR_BW_16BIT)
447
448/* Memory Bank 3 (Latches) */
449#define CONFIG_SYS_EBC_PB3AP (EBC_BXAP_BME_ENABLED | \
450 EBC_BXAP_FWT_ENCODE(8) | \
451 EBC_BXAP_BWT_ENCODE(4) | \
452 EBC_BXAP_BCE_DISABLE | \
453 EBC_BXAP_BCT_2TRANS | \
454 EBC_BXAP_CSN_ENCODE(0) | \
455 EBC_BXAP_OEN_ENCODE(1) | \
456 EBC_BXAP_WBN_ENCODE(1) | \
457 EBC_BXAP_WBF_ENCODE(1) | \
458 EBC_BXAP_TH_ENCODE(2) | \
459 EBC_BXAP_RE_DISABLED | \
460 EBC_BXAP_SOR_NONDELAYED | \
461 EBC_BXAP_BEM_WRITEONLY | \
462 EBC_BXAP_PEN_DISABLED)
463#define CONFIG_SYS_EBC_PB3CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
464 EBC_BXCR_BS_1MB | \
465 EBC_BXCR_BU_RW | \
466 EBC_BXCR_BW_16BIT)
467
468/* EBC peripherals */
469
470#define CONFIG_SYS_FPGA_BASE(k) \
471 (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
472
473#define CONFIG_SYS_FPGA_DONE(k) \
474 (k ? 0x0040 : 0x0080)
475
476#define CONFIG_SYS_FPGA_COUNT 2
477
Dirk Eibachaba27ac2013-06-26 16:04:26 +0200478#define CONFIG_SYS_FPGA_PTR { \
479 (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, \
480 (struct ihs_fpga *)CONFIG_SYS_FPGA1_BASE }
481
482#define CONFIG_SYS_FPGA_COMMON
483
Dirk Eibach255ef4d2011-10-20 11:12:55 +0200484#define CONFIG_SYS_LATCH0_RESET 0xffff
485#define CONFIG_SYS_LATCH0_BOOT 0xffff
486#define CONFIG_SYS_LATCH1_RESET 0xffbf
487#define CONFIG_SYS_LATCH1_BOOT 0xffff
488
489/*-----------------------------------------------------------------------
490 * GPIO Setup
491 *----------------------------------------------------------------------*/
492#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO */ \
493{ \
494/* GPIO Core 0 */ \
495{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO0 */ \
496{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO1 */ \
497{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO2 */ \
498{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO3 */ \
499{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO4 */ \
500{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO5 */ \
501{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO6 */ \
502{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO7 */ \
503{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO8 */ \
504{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO9 */ \
505{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO10 */ \
506{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO11 */ \
507{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO12 */ \
508{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, /* GPIO13 */ \
509{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO14 */ \
510{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO15 */ \
511{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO16 */ \
512{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO17 */ \
513{GPIO0_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO18 */ \
514{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO19 */ \
515{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO20 */ \
516{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO21 */ \
517{GPIO0_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO22 */ \
518{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG}, /* GPIO23 */ \
519{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO24 */ \
520{GPIO0_BASE, GPIO_IN, GPIO_ALT3, GPIO_OUT_0 }, /* GPIO25 */ \
521{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0 }, /* GPIO26 */ \
522{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO27 */ \
523{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO28 */ \
524{GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0 }, /* GPIO29 */ \
525{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO30 */ \
526{GPIO0_BASE, GPIO_IN, GPIO_ALT2, GPIO_OUT_0 }, /* GPIO31 */ \
527} \
528}
529
530#define CONFIG_SYS_GPIO_STARTUP_FINISHED 15
531#define CONFIG_SYS_GPIO_STARTUP_FINISHED_N 14
532
533#endif /* __CONFIG_H */