blob: 4654b2f0c84d7270606c08b783795ab24b61c10f [file] [log] [blame]
Matthias Kaehlcke594d57d2010-01-31 17:39:49 +01001/*
2 * Copyright (C) 2009 Matthias Kaehlcke <matthias@kaehlcke.net>
3 *
4 * Copyright (C) 2004, 2005
5 * Cory T. Tusar, Videon Central, Inc., <ctusar@videon-central.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 *
25 */
26
27#ifndef _EP93XX_ETH_H
28#define _EP93XX_ETH_H
29
30#include <net.h>
31
32/**
33 * #define this to dump device status and queue info during initialization and
34 * following errors.
35 */
36#undef EP93XX_MAC_DEBUG
37
38/**
39 * Number of descriptor and status entries in our RX queues.
40 * It must be power of 2 !
41 */
42#define NUMRXDESC PKTBUFSRX
43
44/**
45 * Number of descriptor and status entries in our TX queues.
46 */
47#define NUMTXDESC 1
48
49/**
50 * 944 = (1024 - 64) - 16, Fifo size - Minframesize - 16 (Chip FACT)
51 */
52#define TXSTARTMAX 944
53
54/**
55 * Receive descriptor queue entry
56 */
57struct rx_descriptor {
58 uint32_t word1;
59 uint32_t word2;
60};
61
62/**
63 * Receive status queue entry
64 */
65struct rx_status {
66 uint32_t word1;
67 uint32_t word2;
68};
69
70#define RX_STATUS_RWE(rx_status) ((rx_status->word1 >> 30) & 0x01)
71#define RX_STATUS_RFP(rx_status) ((rx_status->word1 >> 31) & 0x01)
72#define RX_STATUS_FRAME_LEN(rx_status) (rx_status->word2 & 0xFFFF)
73
74/**
75 * Transmit descriptor queue entry
76 */
77struct tx_descriptor {
78 uint32_t word1;
79 uint32_t word2;
80};
81
82#define TX_DESC_EOF (1 << 31)
83
84/**
85 * Transmit status queue entry
86 */
87struct tx_status {
88 uint32_t word1;
89};
90
91#define TX_STATUS_TXWE(tx_status) (((tx_status)->word1 >> 30) & 0x01)
92#define TX_STATUS_TXFP(tx_status) (((tx_status)->word1 >> 31) & 0x01)
93
94/**
95 * Transmit descriptor queue
96 */
97struct tx_descriptor_queue {
98 struct tx_descriptor *base;
99 struct tx_descriptor *current;
100 struct tx_descriptor *end;
101};
102
103/**
104 * Transmit status queue
105 */
106struct tx_status_queue {
107 struct tx_status *base;
108 volatile struct tx_status *current;
109 struct tx_status *end;
110};
111
112/**
113 * Receive descriptor queue
114 */
115struct rx_descriptor_queue {
116 struct rx_descriptor *base;
117 struct rx_descriptor *current;
118 struct rx_descriptor *end;
119};
120
121/**
122 * Receive status queue
123 */
124struct rx_status_queue {
125 struct rx_status *base;
126 volatile struct rx_status *current;
127 struct rx_status *end;
128};
129
130/**
131 * EP93xx MAC private data structure
132 */
133struct ep93xx_priv {
134 struct rx_descriptor_queue rx_dq;
135 struct rx_status_queue rx_sq;
136 void *rx_buffer[NUMRXDESC];
137
138 struct tx_descriptor_queue tx_dq;
139 struct tx_status_queue tx_sq;
140
141 struct mac_regs *regs;
142};
143
144#endif