blob: 29681e18a6d0398558382e3944d063a0912db3d8 [file] [log] [blame]
Ruchika Guptab9eebfa2014-10-15 11:35:30 +05301/*
2 * Copyright 2008-2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 *
6 * Based on CAAM driver in drivers/crypto/caam in Linux
7 */
8
9#include <common.h>
10#include <malloc.h>
11#include "fsl_sec.h"
12#include "jr.h"
Ruchika Guptac5de15c2014-10-07 15:46:20 +053013#include "jobdesc.h"
Ruchika Guptab9eebfa2014-10-15 11:35:30 +053014
15#define CIRC_CNT(head, tail, size) (((head) - (tail)) & (size - 1))
16#define CIRC_SPACE(head, tail, size) CIRC_CNT((tail), (head) + 1, (size))
17
18struct jobring jr;
19
20static inline void start_jr0(void)
21{
22 ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
23 u32 ctpr_ms = sec_in32(&sec->ctpr_ms);
24 u32 scfgr = sec_in32(&sec->scfgr);
25
26 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_INCL) {
27 /* VIRT_EN_INCL = 1 & VIRT_EN_POR = 1 or
28 * VIRT_EN_INCL = 1 & VIRT_EN_POR = 0 & SEC_SCFGR_VIRT_EN = 1
29 */
30 if ((ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) ||
31 (!(ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR) &&
32 (scfgr & SEC_SCFGR_VIRT_EN)))
33 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
34 } else {
35 /* VIRT_EN_INCL = 0 && VIRT_EN_POR_VALUE = 1 */
36 if (ctpr_ms & SEC_CTPR_MS_VIRT_EN_POR)
37 sec_out32(&sec->jrstartr, CONFIG_JRSTARTR_JR0);
38 }
39}
40
41static inline void jr_reset_liodn(void)
42{
43 ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
44 sec_out32(&sec->jrliodnr[0].ls, 0);
45}
46
47static inline void jr_disable_irq(void)
48{
49 struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
50 uint32_t jrcfg = sec_in32(&regs->jrcfg1);
51
52 jrcfg = jrcfg | JR_INTMASK;
53
54 sec_out32(&regs->jrcfg1, jrcfg);
55}
56
57static void jr_initregs(void)
58{
59 struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
60 phys_addr_t ip_base = virt_to_phys((void *)jr.input_ring);
61 phys_addr_t op_base = virt_to_phys((void *)jr.output_ring);
62
63#ifdef CONFIG_PHYS_64BIT
64 sec_out32(&regs->irba_h, ip_base >> 32);
65#else
66 sec_out32(&regs->irba_h, 0x0);
67#endif
68 sec_out32(&regs->irba_l, (uint32_t)ip_base);
69#ifdef CONFIG_PHYS_64BIT
70 sec_out32(&regs->orba_h, op_base >> 32);
71#else
72 sec_out32(&regs->orba_h, 0x0);
73#endif
74 sec_out32(&regs->orba_l, (uint32_t)op_base);
75 sec_out32(&regs->ors, JR_SIZE);
76 sec_out32(&regs->irs, JR_SIZE);
77
78 if (!jr.irq)
79 jr_disable_irq();
80}
81
82static int jr_init(void)
83{
84 memset(&jr, 0, sizeof(struct jobring));
85
86 jr.jq_id = DEFAULT_JR_ID;
87 jr.irq = DEFAULT_IRQ;
88
89#ifdef CONFIG_FSL_CORENET
90 jr.liodn = DEFAULT_JR_LIODN;
91#endif
92 jr.size = JR_SIZE;
93 jr.input_ring = (dma_addr_t *)malloc(JR_SIZE * sizeof(dma_addr_t));
94 if (!jr.input_ring)
95 return -1;
96 jr.output_ring =
97 (struct op_ring *)malloc(JR_SIZE * sizeof(struct op_ring));
98 if (!jr.output_ring)
99 return -1;
100
101 memset(jr.input_ring, 0, JR_SIZE * sizeof(dma_addr_t));
102 memset(jr.output_ring, 0, JR_SIZE * sizeof(struct op_ring));
103
104 start_jr0();
105
106 jr_initregs();
107
108 return 0;
109}
110
111static int jr_sw_cleanup(void)
112{
113 jr.head = 0;
114 jr.tail = 0;
115 jr.read_idx = 0;
116 jr.write_idx = 0;
117 memset(jr.info, 0, sizeof(jr.info));
118 memset(jr.input_ring, 0, jr.size * sizeof(dma_addr_t));
119 memset(jr.output_ring, 0, jr.size * sizeof(struct op_ring));
120
121 return 0;
122}
123
124static int jr_hw_reset(void)
125{
126 struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
127 uint32_t timeout = 100000;
128 uint32_t jrint, jrcr;
129
130 sec_out32(&regs->jrcr, JRCR_RESET);
131 do {
132 jrint = sec_in32(&regs->jrint);
133 } while (((jrint & JRINT_ERR_HALT_MASK) ==
134 JRINT_ERR_HALT_INPROGRESS) && --timeout);
135
136 jrint = sec_in32(&regs->jrint);
137 if (((jrint & JRINT_ERR_HALT_MASK) !=
138 JRINT_ERR_HALT_INPROGRESS) && timeout == 0)
139 return -1;
140
141 timeout = 100000;
142 sec_out32(&regs->jrcr, JRCR_RESET);
143 do {
144 jrcr = sec_in32(&regs->jrcr);
145 } while ((jrcr & JRCR_RESET) && --timeout);
146
147 if (timeout == 0)
148 return -1;
149
150 return 0;
151}
152
153/* -1 --- error, can't enqueue -- no space available */
154static int jr_enqueue(uint32_t *desc_addr,
155 void (*callback)(uint32_t desc, uint32_t status, void *arg),
156 void *arg)
157{
158 struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
159 int head = jr.head;
160 dma_addr_t desc_phys_addr = virt_to_phys(desc_addr);
161
162 if (sec_in32(&regs->irsa) == 0 ||
163 CIRC_SPACE(jr.head, jr.tail, jr.size) <= 0)
164 return -1;
165
166 jr.input_ring[head] = desc_phys_addr;
167 jr.info[head].desc_phys_addr = desc_phys_addr;
168 jr.info[head].desc_addr = (uint32_t)desc_addr;
169 jr.info[head].callback = (void *)callback;
170 jr.info[head].arg = arg;
171 jr.info[head].op_done = 0;
172
173 jr.head = (head + 1) & (jr.size - 1);
174
175 sec_out32(&regs->irja, 1);
176
177 return 0;
178}
179
180static int jr_dequeue(void)
181{
182 struct jr_regs *regs = (struct jr_regs *)CONFIG_SYS_FSL_JR0_ADDR;
183 int head = jr.head;
184 int tail = jr.tail;
185 int idx, i, found;
186 void (*callback)(uint32_t desc, uint32_t status, void *arg);
187 void *arg = NULL;
188
189 while (sec_in32(&regs->orsf) && CIRC_CNT(jr.head, jr.tail, jr.size)) {
190 found = 0;
191
192 dma_addr_t op_desc = jr.output_ring[jr.tail].desc;
193 uint32_t status = jr.output_ring[jr.tail].status;
194 uint32_t desc_virt;
195
196 for (i = 0; CIRC_CNT(head, tail + i, jr.size) >= 1; i++) {
197 idx = (tail + i) & (jr.size - 1);
198 if (op_desc == jr.info[idx].desc_phys_addr) {
199 desc_virt = jr.info[idx].desc_addr;
200 found = 1;
201 break;
202 }
203 }
204
205 /* Error condition if match not found */
206 if (!found)
207 return -1;
208
209 jr.info[idx].op_done = 1;
210 callback = (void *)jr.info[idx].callback;
211 arg = jr.info[idx].arg;
212
213 /* When the job on tail idx gets done, increment
214 * tail till the point where job completed out of oredr has
215 * been taken into account
216 */
217 if (idx == tail)
218 do {
219 tail = (tail + 1) & (jr.size - 1);
220 } while (jr.info[tail].op_done);
221
222 jr.tail = tail;
223 jr.read_idx = (jr.read_idx + 1) & (jr.size - 1);
224
225 sec_out32(&regs->orjr, 1);
226 jr.info[idx].op_done = 0;
227
228 callback(desc_virt, status, arg);
229 }
230
231 return 0;
232}
233
234static void desc_done(uint32_t desc, uint32_t status, void *arg)
235{
236 struct result *x = arg;
237 x->status = status;
238 caam_jr_strstatus(status);
239 x->done = 1;
240}
241
242int run_descriptor_jr(uint32_t *desc)
243{
244 unsigned long long timeval = get_ticks();
245 unsigned long long timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
246 struct result op;
247 int ret = 0;
248
249 memset(&op, sizeof(op), 0);
250
251 ret = jr_enqueue(desc, desc_done, &op);
252 if (ret) {
253 debug("Error in SEC enq\n");
254 ret = JQ_ENQ_ERR;
255 goto out;
256 }
257
258 timeval = get_ticks();
259 timeout = usec2ticks(CONFIG_SEC_DEQ_TIMEOUT);
260 while (op.done != 1) {
261 ret = jr_dequeue();
262 if (ret) {
263 debug("Error in SEC deq\n");
264 ret = JQ_DEQ_ERR;
265 goto out;
266 }
267
268 if ((get_ticks() - timeval) > timeout) {
269 debug("SEC Dequeue timed out\n");
270 ret = JQ_DEQ_TO_ERR;
271 goto out;
272 }
273 }
274
275 if (!op.status) {
276 debug("Error %x\n", op.status);
277 ret = op.status;
278 }
279out:
280 return ret;
281}
282
283int jr_reset(void)
284{
285 if (jr_hw_reset() < 0)
286 return -1;
287
288 /* Clean up the jobring structure maintained by software */
289 jr_sw_cleanup();
290
291 return 0;
292}
293
294int sec_reset(void)
295{
296 ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
297 uint32_t mcfgr = sec_in32(&sec->mcfgr);
298 uint32_t timeout = 100000;
299
300 mcfgr |= MCFGR_SWRST;
301 sec_out32(&sec->mcfgr, mcfgr);
302
303 mcfgr |= MCFGR_DMA_RST;
304 sec_out32(&sec->mcfgr, mcfgr);
305 do {
306 mcfgr = sec_in32(&sec->mcfgr);
307 } while ((mcfgr & MCFGR_DMA_RST) == MCFGR_DMA_RST && --timeout);
308
309 if (timeout == 0)
310 return -1;
311
312 timeout = 100000;
313 do {
314 mcfgr = sec_in32(&sec->mcfgr);
315 } while ((mcfgr & MCFGR_SWRST) == MCFGR_SWRST && --timeout);
316
317 if (timeout == 0)
318 return -1;
319
320 return 0;
321}
322
Ruchika Guptac5de15c2014-10-07 15:46:20 +0530323static int instantiate_rng(void)
324{
325 struct result op;
326 u32 *desc;
327 u32 rdsta_val;
328 int ret = 0;
329 ccsr_sec_t __iomem *sec =
330 (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
331 struct rng4tst __iomem *rng =
332 (struct rng4tst __iomem *)&sec->rng;
333
334 memset(&op, 0, sizeof(struct result));
335
336 desc = malloc(sizeof(int) * 6);
337 if (!desc) {
338 printf("cannot allocate RNG init descriptor memory\n");
339 return -1;
340 }
341
342 inline_cnstr_jobdesc_rng_instantiation(desc);
343 ret = run_descriptor_jr(desc);
344
345 if (ret)
346 printf("RNG: Instantiation failed with error %x\n", ret);
347
348 rdsta_val = sec_in32(&rng->rdsta);
349 if (op.status || !(rdsta_val & RNG_STATE0_HANDLE_INSTANTIATED))
350 return -1;
351
352 return ret;
353}
354
355static u8 get_rng_vid(void)
356{
357 ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
358 u32 cha_vid = sec_in32(&sec->chavid_ls);
359
360 return (cha_vid & SEC_CHAVID_RNG_LS_MASK) >> SEC_CHAVID_LS_RNG_SHIFT;
361}
362
363/*
364 * By default, the TRNG runs for 200 clocks per sample;
365 * 1200 clocks per sample generates better entropy.
366 */
367static void kick_trng(int ent_delay)
368{
369 ccsr_sec_t __iomem *sec =
370 (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
371 struct rng4tst __iomem *rng =
372 (struct rng4tst __iomem *)&sec->rng;
373 u32 val;
374
375 /* put RNG4 into program mode */
376 sec_setbits32(&rng->rtmctl, RTMCTL_PRGM);
377 /* rtsdctl bits 0-15 contain "Entropy Delay, which defines the
378 * length (in system clocks) of each Entropy sample taken
379 * */
380 val = sec_in32(&rng->rtsdctl);
381 val = (val & ~RTSDCTL_ENT_DLY_MASK) |
382 (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
383 sec_out32(&rng->rtsdctl, val);
384 /* min. freq. count, equal to 1/4 of the entropy sample length */
385 sec_out32(&rng->rtfreqmin, ent_delay >> 2);
386 /* max. freq. count, equal to 8 times the entropy sample length */
387 sec_out32(&rng->rtfreqmax, ent_delay << 3);
388 /* put RNG4 into run mode */
389 sec_clrbits32(&rng->rtmctl, RTMCTL_PRGM);
390}
391
392static int rng_init(void)
393{
394 int ret, ent_delay = RTSDCTL_ENT_DLY_MIN;
395 ccsr_sec_t __iomem *sec =
396 (ccsr_sec_t __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
397 struct rng4tst __iomem *rng =
398 (struct rng4tst __iomem *)&sec->rng;
399
400 u32 rdsta = sec_in32(&rng->rdsta);
401
402 /* Check if RNG state 0 handler is already instantiated */
403 if (rdsta & RNG_STATE0_HANDLE_INSTANTIATED)
404 return 0;
405
406 do {
407 /*
408 * If either of the SH's were instantiated by somebody else
409 * then it is assumed that the entropy
410 * parameters are properly set and thus the function
411 * setting these (kick_trng(...)) is skipped.
412 * Also, if a handle was instantiated, do not change
413 * the TRNG parameters.
414 */
415 kick_trng(ent_delay);
416 ent_delay += 400;
417 /*
418 * if instantiate_rng(...) fails, the loop will rerun
419 * and the kick_trng(...) function will modfiy the
420 * upper and lower limits of the entropy sampling
421 * interval, leading to a sucessful initialization of
422 * the RNG.
423 */
424 ret = instantiate_rng();
425 } while ((ret == -1) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
426 if (ret) {
427 printf("RNG: Failed to instantiate RNG\n");
428 return ret;
429 }
430
431 /* Enable RDB bit so that RNG works faster */
432 sec_setbits32(&sec->scfgr, SEC_SCFGR_RDBENABLE);
433
434 return ret;
435}
436
Ruchika Guptab9eebfa2014-10-15 11:35:30 +0530437int sec_init(void)
438{
439 int ret = 0;
440
441#ifdef CONFIG_PHYS_64BIT
442 ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
443 uint32_t mcr = sec_in32(&sec->mcfgr);
444
445 sec_out32(&sec->mcfgr, mcr | 1 << MCFGR_PS_SHIFT);
446#endif
447 ret = jr_init();
Ruchika Guptac5de15c2014-10-07 15:46:20 +0530448 if (ret < 0) {
449 printf("SEC initialization failed\n");
Ruchika Guptab9eebfa2014-10-15 11:35:30 +0530450 return -1;
Ruchika Guptac5de15c2014-10-07 15:46:20 +0530451 }
452
453 if (get_rng_vid() >= 4) {
454 if (rng_init() < 0) {
455 printf("RNG instantiation failed\n");
456 return -1;
457 }
458 printf("SEC: RNG instantiated\n");
459 }
Ruchika Guptab9eebfa2014-10-15 11:35:30 +0530460
461 return ret;
462}