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wdenk63f34912004-01-02 15:01:32 +00001/*
2 * rtl8139.c : U-Boot driver for the RealTek RTL8139
3 *
4 * Masami Komiya (mkomiya@sonare.it)
5 *
6 * Most part is taken from rtl8139.c of etherboot
7 *
8 */
9
10/* rtl8139.c - etherboot driver for the Realtek 8139 chipset
11
12 ported from the linux driver written by Donald Becker
13 by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
14
15 This software may be used and distributed according to the terms
16 of the GNU Public License, incorporated herein by reference.
17
18 changes to the original driver:
19 - removed support for interrupts, switching to polling mode (yuck!)
20 - removed support for the 8129 chip (external MII)
21
22*/
23
24/*********************************************************************/
25/* Revision History */
26/*********************************************************************/
27
28/*
29 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap)
30 Put in virt_to_bus calls to allow Etherboot relocation.
31
32 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap)
33 Following email from Hyun-Joon Cha, added a disable routine, otherwise
34 NIC remains live and can crash the kernel later.
35
36 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
37 Shuffled things around, removed the leftovers from the 8129 support
38 that was in the Linux driver and added a bit more 8139 definitions.
39 Moved the 8K receive buffer to a fixed, available address outside the
40 0x98000-0x9ffff range. This is a bit of a hack, but currently the only
41 way to make room for the Etherboot features that need substantial amounts
42 of code like the ANSI console support. Currently the buffer is just below
43 0x10000, so this even conforms to the tagged boot image specification,
44 which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My
45 interpretation of this "reserved" is that Etherboot may do whatever it
46 likes, as long as its environment is kept intact (like the BIOS
wdenkb6e4c402004-01-02 16:05:07 +000047 variables). Hopefully fixed rtl_poll() once and for all. The symptoms
wdenk63f34912004-01-02 15:01:32 +000048 were that if Etherboot was left at the boot menu for several minutes, the
49 first eth_poll failed. Seems like I am the only person who does this.
50 First of all I fixed the debugging code and then set out for a long bug
51 hunting session. It took me about a week full time work - poking around
52 various places in the driver, reading Don Becker's and Jeff Garzik's Linux
53 driver and even the FreeBSD driver (what a piece of crap!) - and
54 eventually spotted the nasty thing: the transmit routine was acknowledging
55 each and every interrupt pending, including the RxOverrun and RxFIFIOver
wdenkb6e4c402004-01-02 16:05:07 +000056 interrupts. This confused the RTL8139 thoroughly. It destroyed the
wdenk63f34912004-01-02 15:01:32 +000057 Rx ring contents by dumping the 2K FIFO contents right where we wanted to
58 get the next packet. Oh well, what fun.
59
wdenkb6e4c402004-01-02 16:05:07 +000060 18 Jan 2000 mdc@thinguin.org (Marty Connor)
wdenk63f34912004-01-02 15:01:32 +000061 Drastically simplified error handling. Basically, if any error
62 in transmission or reception occurs, the card is reset.
63 Also, pointed all transmit descriptors to the same buffer to
wdenkb6e4c402004-01-02 16:05:07 +000064 save buffer space. This should decrease driver size and avoid
wdenk63f34912004-01-02 15:01:32 +000065 corruption because of exceeding 32K during runtime.
66
wdenkb6e4c402004-01-02 16:05:07 +000067 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
wdenk63f34912004-01-02 15:01:32 +000068 rtl_poll was quite broken: it used the RxOK interrupt flag instead
69 of the RxBufferEmpty flag which often resulted in very bad
70 transmission performace - below 1kBytes/s.
71
72*/
73
74#include <common.h>
75#include <malloc.h>
76#include <net.h>
77#include <asm/io.h>
78#include <pci.h>
79
wdenk63f34912004-01-02 15:01:32 +000080#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
81 defined(CONFIG_RTL8139)
82
83#define TICKS_PER_SEC CFG_HZ
84#define TICKS_PER_MS (TICKS_PER_SEC/1000)
85
86#define RTL_TIMEOUT (1*TICKS_PER_SEC)
87
88#define ETH_FRAME_LEN 1514
89#define ETH_ALEN 6
90#define ETH_ZLEN 60
91
92/* PCI Tuning Parameters
93 Threshold is bytes transferred to chip before transmission starts. */
wdenkb6e4c402004-01-02 16:05:07 +000094#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
95#define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
96#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
97#define TX_DMA_BURST 4 /* Calculate as 16<<val. */
98#define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */
wdenk63f34912004-01-02 15:01:32 +000099#define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */
100#define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */
101#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
102
103#undef DEBUG_TX
104#undef DEBUG_RX
105
106#define currticks() get_timer(0)
wdenkb6e4c402004-01-02 16:05:07 +0000107#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
108#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
wdenk63f34912004-01-02 15:01:32 +0000109
110/* Symbolic offsets to registers. */
111enum RTL8139_registers {
112 MAC0=0, /* Ethernet hardware address. */
113 MAR0=8, /* Multicast filter. */
114 TxStatus0=0x10, /* Transmit status (four 32bit registers). */
115 TxAddr0=0x20, /* Tx descriptors (also four 32bit). */
116 RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36,
117 ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A,
118 IntrMask=0x3C, IntrStatus=0x3E,
119 TxConfig=0x40, RxConfig=0x44,
120 Timer=0x48, /* general-purpose counter. */
121 RxMissed=0x4C, /* 24 bits valid, write clears. */
122 Cfg9346=0x50, Config0=0x51, Config1=0x52,
123 TimerIntrReg=0x54, /* intr if gp counter reaches this value */
124 MediaStatus=0x58,
125 Config3=0x59,
126 MultiIntr=0x5C,
127 RevisionID=0x5E, /* revision of the RTL8139 chip */
128 TxSummary=0x60,
129 MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68,
130 NWayExpansion=0x6A,
131 DisconnectCnt=0x6C, FalseCarrierCnt=0x6E,
132 NWayTestReg=0x70,
133 RxCnt=0x72, /* packet received counter */
134 CSCR=0x74, /* chip status and configuration register */
135 PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80, /* undocumented */
136 /* from 0x84 onwards are a number of power management/wakeup frame
137 * definitions we will probably never need to know about. */
138};
139
140enum ChipCmdBits {
141 CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, };
142
143/* Interrupt register bits, using my own meaningful names. */
144enum IntrStatusBits {
145 PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000,
146 RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10,
147 TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01,
148};
149enum TxStatusBits {
150 TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000,
151 TxOutOfWindow=0x20000000, TxAborted=0x40000000,
152 TxCarrierLost=0x80000000,
153};
154enum RxStatusBits {
155 RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000,
156 RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004,
157 RxBadAlign=0x0002, RxStatusOK=0x0001,
158};
159
160enum MediaStatusBits {
161 MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08,
162 MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01,
163};
164
165enum MIIBMCRBits {
166 BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000,
167 BMCRRestartNWay=0x0200, BMCRDuplex=0x0100,
168};
169
170enum CSCRBits {
171 CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800,
172 CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0,
173 CSCR_LinkDownCmd=0x0f3c0,
174};
175
176/* Bits in RxConfig. */
177enum rx_mode_bits {
178 RxCfgWrap=0x80,
179 AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08,
180 AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01,
181};
182
183static int ioaddr;
184static unsigned int cur_rx,cur_tx;
185
186/* The RTL8139 can only transmit from a contiguous, aligned memory block. */
187static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4)));
188static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4)));
189
190static int rtl8139_probe(struct eth_device *dev, bd_t *bis);
191static int read_eeprom(int location, int addr_len);
192static void rtl_reset(struct eth_device *dev);
193static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length);
194static int rtl_poll(struct eth_device *dev);
195static void rtl_disable(struct eth_device *dev);
196
197static struct pci_device_id supported[] = {
198 {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
Jin Zhengxiongda012ab2006-06-28 08:43:56 -0500199 {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139},
wdenk63f34912004-01-02 15:01:32 +0000200 {}
201};
202
203int rtl8139_initialize(bd_t *bis)
204{
205 pci_dev_t devno;
206 int card_number = 0;
207 struct eth_device *dev;
208 u32 iobase;
209 int idx=0;
210
211 while(1){
212 /* Find RTL8139 */
213 if ((devno = pci_find_devices(supported, idx++)) < 0)
214 break;
215
216 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
217 iobase &= ~0xf;
218
219 debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
220
221 dev = (struct eth_device *)malloc(sizeof *dev);
222
223 sprintf (dev->name, "RTL8139#%d", card_number);
224
225 dev->priv = (void *) devno;
226 dev->iobase = (int)bus_to_phys(iobase);
227 dev->init = rtl8139_probe;
228 dev->halt = rtl_disable;
229 dev->send = rtl_transmit;
230 dev->recv = rtl_poll;
231
232 eth_register (dev);
233
234 card_number++;
235
236 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
237
238 udelay (10 * 1000);
239 }
240
241 return card_number;
242}
243
244static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
245{
246 int i;
247 int speed10, fullduplex;
248 int addr_len;
249 unsigned short *ap = (unsigned short *)dev->enetaddr;
250
251 ioaddr = dev->iobase;
252
253 /* Bring the chip out of low-power mode. */
254 outb(0x00, ioaddr + Config1);
255
256 addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6;
257 for (i = 0; i < 3; i++)
wdenk756f5862005-04-03 15:51:42 +0000258 *ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len));
wdenk63f34912004-01-02 15:01:32 +0000259
260 speed10 = inb(ioaddr + MediaStatus) & MSRSpeed10;
261 fullduplex = inw(ioaddr + MII_BMCR) & BMCRDuplex;
262
263 rtl_reset(dev);
264
265 if (inb(ioaddr + MediaStatus) & MSRLinkFail) {
266 printf("Cable not connected or other link failure\n");
267 return(0);
268 }
269
270 return 1;
271}
272
273/* Serial EEPROM section. */
274
275/* EEPROM_Ctrl bits. */
wdenkb6e4c402004-01-02 16:05:07 +0000276#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
277#define EE_CS 0x08 /* EEPROM chip select. */
278#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
279#define EE_WRITE_0 0x00
280#define EE_WRITE_1 0x02
281#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
wdenk63f34912004-01-02 15:01:32 +0000282#define EE_ENB (0x80 | EE_CS)
283
284/*
285 Delay between EEPROM clock transitions.
286 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
287*/
288
wdenkb6e4c402004-01-02 16:05:07 +0000289#define eeprom_delay() inl(ee_addr)
wdenk63f34912004-01-02 15:01:32 +0000290
291/* The EEPROM commands include the alway-set leading bit. */
wdenkb6e4c402004-01-02 16:05:07 +0000292#define EE_WRITE_CMD (5)
293#define EE_READ_CMD (6)
294#define EE_ERASE_CMD (7)
wdenk63f34912004-01-02 15:01:32 +0000295
296static int read_eeprom(int location, int addr_len)
297{
298 int i;
299 unsigned int retval = 0;
300 long ee_addr = ioaddr + Cfg9346;
301 int read_cmd = location | (EE_READ_CMD << addr_len);
302
303 outb(EE_ENB & ~EE_CS, ee_addr);
304 outb(EE_ENB, ee_addr);
305 eeprom_delay();
306
307 /* Shift the read command bits out. */
308 for (i = 4 + addr_len; i >= 0; i--) {
309 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
310 outb(EE_ENB | dataval, ee_addr);
311 eeprom_delay();
312 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
313 eeprom_delay();
314 }
315 outb(EE_ENB, ee_addr);
316 eeprom_delay();
317
318 for (i = 16; i > 0; i--) {
319 outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
320 eeprom_delay();
321 retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
322 outb(EE_ENB, ee_addr);
323 eeprom_delay();
324 }
325
326 /* Terminate the EEPROM access. */
327 outb(~EE_CS, ee_addr);
328 eeprom_delay();
329 return retval;
330}
331
332static const unsigned int rtl8139_rx_config =
333 (RX_BUF_LEN_IDX << 11) |
334 (RX_FIFO_THRESH << 13) |
335 (RX_DMA_BURST << 8);
336
337static void set_rx_mode(struct eth_device *dev) {
338 unsigned int mc_filter[2];
339 int rx_mode;
340 /* !IFF_PROMISC */
341 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
342 mc_filter[1] = mc_filter[0] = 0xffffffff;
343
344 outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig);
345
346 outl(mc_filter[0], ioaddr + MAR0 + 0);
347 outl(mc_filter[1], ioaddr + MAR0 + 4);
348}
349
350static void rtl_reset(struct eth_device *dev)
351{
352 int i;
353
354 outb(CmdReset, ioaddr + ChipCmd);
355
356 cur_rx = 0;
357 cur_tx = 0;
358
359 /* Give the chip 10ms to finish the reset. */
360 for (i=0; i<100; ++i){
361 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
362 udelay (100); /* wait 100us */
363 }
364
365
366 for (i = 0; i < ETH_ALEN; i++)
367 outb(dev->enetaddr[i], ioaddr + MAC0 + i);
368
369 /* Must enable Tx/Rx before setting transfer thresholds! */
370 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
371 outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8),
372 ioaddr + RxConfig); /* accept no frames yet! */
373 outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig);
374
375 /* The Linux driver changes Config1 here to use a different LED pattern
376 * for half duplex or full/autodetect duplex (for full/autodetect, the
377 * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses
378 * TX/RX, Link100, Link10). This is messy, because it doesn't match
379 * the inscription on the mounting bracket. It should not be changed
380 * from the configuration EEPROM default, because the card manufacturer
381 * should have set that to match the card. */
382
383#ifdef DEBUG_RX
384 printf("rx ring address is %X\n",(unsigned long)rx_ring);
385#endif
386 outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf);
387
388 /* If we add multicast support, the MAR0 register would have to be
389 * initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot
wdenkb6e4c402004-01-02 16:05:07 +0000390 * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */
wdenk63f34912004-01-02 15:01:32 +0000391
392 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
393
394 outl(rtl8139_rx_config, ioaddr + RxConfig);
395
396 /* Start the chip's Tx and Rx process. */
397 outl(0, ioaddr + RxMissed);
398
399 /* set_rx_mode */
400 set_rx_mode(dev);
401
402 /* Disable all known interrupts by setting the interrupt mask. */
403 outw(0, ioaddr + IntrMask);
404}
405
406static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length)
407{
408 unsigned int status, to;
409 unsigned long txstatus;
410 unsigned int len = length;
411
412 ioaddr = dev->iobase;
413
414 memcpy((char *)tx_buffer, (char *)packet, (int)length);
415
416#ifdef DEBUG_TX
417 printf("sending %d bytes\n", len);
418#endif
419
420 /* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
421 * bytes are sent automatically for the FCS, totalling to 64 bytes). */
422 while (len < ETH_ZLEN) {
423 tx_buffer[len++] = '\0';
424 }
425
426 outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4);
427 outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len,
428 ioaddr + TxStatus0 + cur_tx*4);
429
430 to = currticks() + RTL_TIMEOUT;
431
432 do {
433 status = inw(ioaddr + IntrStatus);
434 /* Only acknlowledge interrupt sources we can properly handle
435 * here - the RxOverflow/RxFIFOOver MUST be handled in the
wdenkb6e4c402004-01-02 16:05:07 +0000436 * rtl_poll() function. */
wdenk63f34912004-01-02 15:01:32 +0000437 outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus);
438 if ((status & (TxOK | TxErr | PCIErr)) != 0) break;
439 } while (currticks() < to);
440
441 txstatus = inl(ioaddr + TxStatus0 + cur_tx*4);
442
443 if (status & TxOK) {
444 cur_tx = (cur_tx + 1) % NUM_TX_DESC;
445#ifdef DEBUG_TX
446 printf("tx done (%d ticks), status %hX txstatus %X\n",
447 to-currticks(), status, txstatus);
448#endif
449 return length;
450 } else {
451#ifdef DEBUG_TX
452 printf("tx timeout/error (%d ticks), status %hX txstatus %X\n",
453 currticks()-to, status, txstatus);
454#endif
455 rtl_reset(dev);
456
457 return 0;
458 }
459}
460
461static int rtl_poll(struct eth_device *dev)
462{
463 unsigned int status;
464 unsigned int ring_offs;
465 unsigned int rx_size, rx_status;
466 int length=0;
467
468 ioaddr = dev->iobase;
469
470 if (inb(ioaddr + ChipCmd) & RxBufEmpty) {
471 return 0;
472 }
473
474 status = inw(ioaddr + IntrStatus);
475 /* See below for the rest of the interrupt acknowledges. */
476 outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
477
478#ifdef DEBUG_RX
479 printf("rtl_poll: int %hX ", status);
480#endif
481
482 ring_offs = cur_rx % RX_BUF_LEN;
483 rx_status = *(unsigned int*)KSEG1ADDR((rx_ring + ring_offs));
484 rx_size = rx_status >> 16;
485 rx_status &= 0xffff;
486
487 if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) ||
488 (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) {
489 printf("rx error %hX\n", rx_status);
wdenkb6e4c402004-01-02 16:05:07 +0000490 rtl_reset(dev); /* this clears all interrupts still pending */
wdenk63f34912004-01-02 15:01:32 +0000491 return 0;
492 }
493
494 /* Received a good packet */
495 length = rx_size - 4; /* no one cares about the FCS */
496 if (ring_offs+4+rx_size-4 > RX_BUF_LEN) {
497 int semi_count = RX_BUF_LEN - ring_offs - 4;
498 unsigned char rxdata[RX_BUF_LEN];
499
500 memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
501 memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count);
502
503 NetReceive(rxdata, length);
504#ifdef DEBUG_RX
505 printf("rx packet %d+%d bytes", semi_count,rx_size-4-semi_count);
506#endif
507 } else {
508 NetReceive(rx_ring + ring_offs + 4, length);
509#ifdef DEBUG_RX
510 printf("rx packet %d bytes", rx_size-4);
511#endif
512 }
513
514 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
515 outw(cur_rx - 16, ioaddr + RxBufPtr);
516 /* See RTL8139 Programming Guide V0.1 for the official handling of
517 * Rx overflow situations. The document itself contains basically no
518 * usable information, except for a few exception handling rules. */
519 outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
520 return length;
521}
522
523static void rtl_disable(struct eth_device *dev)
524{
525 int i;
526
wdenkb6e4c402004-01-02 16:05:07 +0000527 ioaddr = dev->iobase;
528
wdenk63f34912004-01-02 15:01:32 +0000529 /* reset the chip */
530 outb(CmdReset, ioaddr + ChipCmd);
531
532 /* Give the chip 10ms to finish the reset. */
533 for (i=0; i<100; ++i){
534 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
535 udelay (100); /* wait 100us */
536 }
537}
538#endif /* CFG_CMD_NET && CONFIG_NET_MULTI && CONFIG_RTL8139 */