blob: 58bc5d3f95696c08e919812d90fc004769c161f8 [file] [log] [blame]
wdenkf12e5682003-07-07 20:07:54 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2000-2005
wdenkf12e5682003-07-07 20:07:54 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
37#define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */
38
39#ifdef CONFIG_LCD /* with LCD controller ? */
wdenkfd3103b2003-11-25 16:55:19 +000040/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */
wdenkf12e5682003-07-07 20:07:54 +000041#endif
42
43#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
44#undef CONFIG_8xx_CONS_SMC2
45#undef CONFIG_8xx_CONS_NONE
46#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
wdenkf12e5682003-07-07 20:07:54 +000047
wdenkae3af052003-08-07 22:18:11 +000048#define CONFIG_BOOTCOUNT_LIMIT
49
50#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf12e5682003-07-07 20:07:54 +000051
52#define CONFIG_BOARD_TYPES 1 /* support board types */
53
54#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
55
56#undef CONFIG_BOOTARGS
57
58#define CONFIG_EXTRA_ENV_SETTINGS \
59 "netdev=eth0\0" \
60 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010061 "nfsroot=${serverip}:${rootpath}\0" \
wdenkf12e5682003-07-07 20:07:54 +000062 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010063 "addip=setenv bootargs ${bootargs} " \
64 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
65 ":${hostname}:${netdev}:off panic=1\0" \
wdenkf12e5682003-07-07 20:07:54 +000066 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010067 "bootm ${kernel_addr}\0" \
wdenkf12e5682003-07-07 20:07:54 +000068 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010069 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
70 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenkf12e5682003-07-07 20:07:54 +000071 "rootpath=/opt/eldk/ppc_8xx\0" \
72 "bootfile=/tftpboot/TQM823M/uImage\0" \
73 "kernel_addr=40080000\0" \
74 "ramdisk_addr=40180000\0" \
75 ""
76#define CONFIG_BOOTCOMMAND "run flash_self"
77
78#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
79#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
80
81#undef CONFIG_WATCHDOG /* watchdog disabled */
82
83#ifdef CONFIG_LCD
84# undef CONFIG_STATUS_LED /* disturbs display */
85#else
86# define CONFIG_STATUS_LED 1 /* Status LED enabled */
87#endif /* CONFIG_LCD */
88
89#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
90
Jon Loeliger37d4bb72007-07-09 21:38:02 -050091/*
92 * BOOTP options
93 */
94#define CONFIG_BOOTP_SUBNETMASK
95#define CONFIG_BOOTP_GATEWAY
96#define CONFIG_BOOTP_HOSTNAME
97#define CONFIG_BOOTP_BOOTPATH
98#define CONFIG_BOOTP_BOOTFILESIZE
99
wdenkf12e5682003-07-07 20:07:54 +0000100
101#define CONFIG_MAC_PARTITION
102#define CONFIG_DOS_PARTITION
103
104#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
105
wdenkf12e5682003-07-07 20:07:54 +0000106
Jon Loeliger26946902007-07-04 22:30:50 -0500107/*
108 * Command line configuration.
109 */
110#include <config_cmd_default.h>
111
112#define CONFIG_CMD_ASKENV
113#define CONFIG_CMD_DATE
114#define CONFIG_CMD_DHCP
115#define CONFIG_CMD_IDE
116#define CONFIG_CMD_NFS
117#define CONFIG_CMD_SNTP
118
wdenkf12e5682003-07-07 20:07:54 +0000119
120/*
121 * Miscellaneous configurable options
122 */
123#define CFG_LONGHELP /* undef to save memory */
124#define CFG_PROMPT "=> " /* Monitor Command Prompt */
125
Wolfgang Denk2751a952006-10-28 02:29:14 +0200126#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
127#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
wdenkf12e5682003-07-07 20:07:54 +0000128#ifdef CFG_HUSH_PARSER
129#define CFG_PROMPT_HUSH_PS2 "> "
130#endif
131
Jon Loeliger26946902007-07-04 22:30:50 -0500132#if defined(CONFIG_CMD_KGDB)
wdenkf12e5682003-07-07 20:07:54 +0000133#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
134#else
135#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
136#endif
137#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
138#define CFG_MAXARGS 16 /* max number of command args */
139#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
140
141#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
142#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
143
144#define CFG_LOAD_ADDR 0x100000 /* default load address */
145
146#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
147
148#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
149
150/*
151 * Low Level Configuration Settings
152 * (address mappings, register initial values, etc.)
153 * You should know what you are doing if you make changes here.
154 */
155/*-----------------------------------------------------------------------
156 * Internal Memory Mapped Register
157 */
158#define CFG_IMMR 0xFFF00000
159
160/*-----------------------------------------------------------------------
161 * Definitions for initial stack pointer and data area (in DPRAM)
162 */
163#define CFG_INIT_RAM_ADDR CFG_IMMR
164#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
165#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
166#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
167#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
168
169/*-----------------------------------------------------------------------
170 * Start addresses for the final memory configuration
171 * (Set up by the startup code)
172 * Please note that CFG_SDRAM_BASE _must_ start at 0
173 */
174#define CFG_SDRAM_BASE 0x00000000
175#define CFG_FLASH_BASE 0x40000000
176#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
177#define CFG_MONITOR_BASE CFG_FLASH_BASE
178#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
179
180/*
181 * For booting Linux, the board info and command line data
182 * have to be in the first 8 MB of memory, since this is
183 * the maximum mapped by the Linux kernel during initialization.
184 */
185#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
186
187/*-----------------------------------------------------------------------
188 * FLASH organization
189 */
190#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
191#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
192
193#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
194#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
195
196#define CFG_ENV_IS_IN_FLASH 1
197#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
198#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
199#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */
200
201/* Address and size of Redundant Environment Sector */
202#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
203#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
204
205/*-----------------------------------------------------------------------
206 * Hardware Information Block
207 */
208#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
209#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
210#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
211
212/*-----------------------------------------------------------------------
213 * Cache Configuration
214 */
215#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500216#if defined(CONFIG_CMD_KGDB)
wdenkf12e5682003-07-07 20:07:54 +0000217#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
218#endif
219
220/*-----------------------------------------------------------------------
221 * SYPCR - System Protection Control 11-9
222 * SYPCR can only be written once after reset!
223 *-----------------------------------------------------------------------
224 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
225 */
226#if defined(CONFIG_WATCHDOG)
227#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
228 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
229#else
230#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
231#endif
232
233/*-----------------------------------------------------------------------
234 * SIUMCR - SIU Module Configuration 11-6
235 *-----------------------------------------------------------------------
236 * PCMCIA config., multi-function pin tri-state
237 */
238#ifndef CONFIG_CAN_DRIVER
239#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
240#else /* we must activate GPL5 in the SIUMCR for CAN */
241#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
242#endif /* CONFIG_CAN_DRIVER */
243
244/*-----------------------------------------------------------------------
245 * TBSCR - Time Base Status and Control 11-26
246 *-----------------------------------------------------------------------
247 * Clear Reference Interrupt Status, Timebase freezing enabled
248 */
249#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
250
251/*-----------------------------------------------------------------------
252 * RTCSC - Real-Time Clock Status and Control Register 11-27
253 *-----------------------------------------------------------------------
254 */
255#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
256
257/*-----------------------------------------------------------------------
258 * PISCR - Periodic Interrupt Status and Control 11-31
259 *-----------------------------------------------------------------------
260 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
261 */
262#define CFG_PISCR (PISCR_PS | PISCR_PITF)
263
264/*-----------------------------------------------------------------------
265 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
266 *-----------------------------------------------------------------------
267 * Reset PLL lock status sticky bit, timer expired status bit and timer
268 * interrupt status bit
wdenkf12e5682003-07-07 20:07:54 +0000269 */
wdenkf12e5682003-07-07 20:07:54 +0000270#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf12e5682003-07-07 20:07:54 +0000271
272/*-----------------------------------------------------------------------
273 * SCCR - System Clock and reset Control Register 15-27
274 *-----------------------------------------------------------------------
275 * Set clock output, timebase and RTC source and divider,
276 * power management and some other internal clocks
277 */
278#define SCCR_MASK SCCR_EBDF11
wdenke9132ea2004-04-24 23:23:30 +0000279#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf12e5682003-07-07 20:07:54 +0000280 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
281 SCCR_DFALCD00)
wdenkf12e5682003-07-07 20:07:54 +0000282
283/*-----------------------------------------------------------------------
284 * PCMCIA stuff
285 *-----------------------------------------------------------------------
286 *
287 */
288#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
289#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
290#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
291#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
292#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
293#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
294#define CFG_PCMCIA_IO_ADDR (0xEC000000)
295#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
296
297/*-----------------------------------------------------------------------
298 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
299 *-----------------------------------------------------------------------
300 */
301
302#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
303
304#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
305#undef CONFIG_IDE_LED /* LED for ide not supported */
306#undef CONFIG_IDE_RESET /* reset for ide not supported */
307
308#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
309#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
310
311#define CFG_ATA_IDE0_OFFSET 0x0000
312
313#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
314
315/* Offset for data I/O */
316#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
317
318/* Offset for normal register accesses */
319#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
320
321/* Offset for alternate registers */
322#define CFG_ATA_ALT_OFFSET 0x0100
323
324/*-----------------------------------------------------------------------
325 *
326 *-----------------------------------------------------------------------
327 *
328 */
329#define CFG_DER 0
330
331/*
332 * Init Memory Controller:
333 *
334 * BR0/1 and OR0/1 (FLASH)
335 */
336
337#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
338#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
339
340/* used to re-map FLASH both when starting from SRAM or FLASH:
341 * restrict access enough to keep SRAM working (if any)
342 * but not too much to meddle with FLASH accesses
343 */
344#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
345#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
346
347/*
348 * FLASH timing:
349 */
wdenkf12e5682003-07-07 20:07:54 +0000350#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
351 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf12e5682003-07-07 20:07:54 +0000352
353#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
354#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
355#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
356
357#define CFG_OR1_REMAP CFG_OR0_REMAP
358#define CFG_OR1_PRELIM CFG_OR0_PRELIM
359#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
360
361/*
362 * BR2/3 and OR2/3 (SDRAM)
363 *
364 */
365#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
366#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
367#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
368
369/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
370#define CFG_OR_TIMING_SDRAM 0x00000A00
371
372#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
373#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
374
375#ifndef CONFIG_CAN_DRIVER
376#define CFG_OR3_PRELIM CFG_OR2_PRELIM
377#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
378#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
379#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
380#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
381#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
382#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \
383 BR_PS_8 | BR_MS_UPMB | BR_V )
384#endif /* CONFIG_CAN_DRIVER */
385
386/*
387 * Memory Periodic Timer Prescaler
388 *
389 * The Divider for PTA (refresh timer) configuration is based on an
390 * example SDRAM configuration (64 MBit, one bank). The adjustment to
391 * the number of chip selects (NCS) and the actually needed refresh
392 * rate is done by setting MPTPR.
393 *
394 * PTA is calculated from
395 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
396 *
397 * gclk CPU clock (not bus clock!)
398 * Trefresh Refresh cycle * 4 (four word bursts used)
399 *
400 * 4096 Rows from SDRAM example configuration
401 * 1000 factor s -> ms
402 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
403 * 4 Number of refresh cycles per period
404 * 64 Refresh cycle in ms per number of rows
405 * --------------------------------------------
406 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
407 *
408 * 50 MHz => 50.000.000 / Divider = 98
409 * 66 Mhz => 66.000.000 / Divider = 129
410 * 80 Mhz => 80.000.000 / Divider = 156
411 */
wdenke9132ea2004-04-24 23:23:30 +0000412
413#define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
414#define CFG_MAMR_PTA 98
wdenkf12e5682003-07-07 20:07:54 +0000415
416/*
417 * For 16 MBit, refresh rates could be 31.3 us
418 * (= 64 ms / 2K = 125 / quad bursts).
419 * For a simpler initialization, 15.6 us is used instead.
420 *
421 * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
422 * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
423 */
424#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
425#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
426
427/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
428#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
429#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
430
431/*
432 * MAMR settings for SDRAM
433 */
434
435/* 8 column SDRAM */
436#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
437 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
438 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
439/* 9 column SDRAM */
440#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
441 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
442 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
443
444
445/*
446 * Internal Definitions
447 *
448 * Boot Flags
449 */
450#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
451#define BOOTFLAG_WARM 0x02 /* Software reboot */
452
453#endif /* __CONFIG_H */