blob: d1d1a5700034b77da0343812001826529950c34a [file] [log] [blame]
wdenk43c377f2002-07-20 10:56:28 +00001/*
2 * Memory Setup stuff - taken from ???
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23
24
25#include <config.h>
26#include <version.h>
27
28
29/* some parameters for the board */
30
31SYSCON2: .long 0x80001100
32MEMCFG1: .long 0x80000180
33MEMCFG2: .long 0x800001C0
34DRFPR: .long 0x80000200
35
36syscon2_mask: .long 0x00000004
37memcfg1_val: .long 0x160c1414
38memcfg2_mask: .long 0x0000ffff @ only set lower 16 bits
39memcfg2_val: .long 0x00000000 @ upper 16 bits are reserved for CS7 + CS6
40drfpr_val: .long 0x00000081
41/* setting up the memory */
42
43.globl memsetup
44memsetup:
45 /*
46 * DRFPR
47 * 64kHz DRAM refresh
48 */
49 ldr r0, DRFPR
50 ldr r1, drfpr_val
51 str r1, [r0]
52
53 /*
54 * SYSCON2: clear bit 2, DRAM is 32 bits wide
55 */
56 ldr r0, SYSCON2
57 ldr r2, [r0]
58 ldr r1, syscon2_mask
59 bic r2, r2, r1
60 str r2, [r0]
61
62 /*
63 * MEMCFG1
64 * Setting up Keyboard at CS3, 8 Bit, 3 Waitstates
65 * Setting up CS8900 (Ethernet) at CS2, 32 Bit, 5 Waitstates
66 * Setting up flash at CS0 and CS1, 32 Bit, 3 Waitstates
67 */
68 ldr r0, MEMCFG1
69 ldr r1, memcfg1_val
70 str r1, [r0]
71
72 /*
73 * MEMCFG2
74 * Setting up ? with 0
75 *
76 */
77 ldr r0, MEMCFG2
78 ldr r2, [r0]
79 ldr r1, memcfg2_mask
80 bic r2, r2, r1
81 ldr r1, memcfg2_val
82 orr r2, r2, r1
83 str r2, [r0]
84
85 /* everything is fine now */
86 mov pc, lr
87