blob: 5b710089c110a3c9f0beb7364f68ecc9b5ff714c [file] [log] [blame]
Chris Zankelc978b522016-08-10 18:36:44 +03001/*
2 * Copyright (C) 2016 Cadence Design Systems Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _XTENSA_SYSTEM_H
8#define _XTENSA_SYSTEM_H
9
10#include <asm/arch/core.h>
11
12#if XCHAL_HAVE_INTERRUPTS
13#define local_irq_save(flags) \
14 __asm__ __volatile__ ("rsil %0, %1" \
15 : "=a"(flags) \
16 : "I"(XCHAL_EXCM_LEVEL) \
17 : "memory")
18#define local_irq_restore(flags) \
19 __asm__ __volatile__ ("wsr %0, ps\n\t" \
20 "rsync" \
21 :: "a"(flags) : "memory")
22#else
23#define local_irq_save(flags) ((void)(flags))
24#define local_irq_restore(flags) ((void)(flags))
25#endif
26
27#endif