blob: c2379804aca2e9cf18d35ca955224ea7e9682dcd [file] [log] [blame]
Fabio Estevam860b32e2011-05-13 03:15:11 +00001/*
2 * (C) Copyright 2011 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <asm/io.h>
25#include <asm/arch/imx-regs.h>
26#include <asm/arch/mx5x_pins.h>
27#include <asm/arch/sys_proto.h>
28#include <asm/arch/crm_regs.h>
29#include <asm/arch/iomux.h>
30#include <asm/errno.h>
31#include <netdev.h>
32#include <mmc.h>
33#include <fsl_esdhc.h>
Stefano Babic04e25fd2011-08-21 10:56:57 +020034#include <asm/gpio.h>
Fabio Estevam860b32e2011-05-13 03:15:11 +000035
36DECLARE_GLOBAL_DATA_PTR;
37
Fabio Estevam860b32e2011-05-13 03:15:11 +000038int dram_init(void)
39{
40 u32 size1, size2;
41
Albert ARIBAUDa55d23c2011-07-03 05:55:33 +000042 size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
43 size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
Fabio Estevam860b32e2011-05-13 03:15:11 +000044
45 gd->ram_size = size1 + size2;
46
47 return 0;
48}
49void dram_init_banksize(void)
50{
51 gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
52 gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
53
54 gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
55 gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
56}
57
58static void setup_iomux_uart(void)
59{
60 /* UART1 RXD */
61 mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
62 mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
63 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
64 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
65 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
66 PAD_CTL_ODE_OPENDRAIN_ENABLE);
67 mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
68
69 /* UART1 TXD */
70 mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
71 mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
72 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
73 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
74 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
75 PAD_CTL_ODE_OPENDRAIN_ENABLE);
76}
77
78static void setup_iomux_fec(void)
79{
80 /*FEC_MDIO*/
81 mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
82 mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
83 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
84 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
85 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
86 mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
87
88 /*FEC_MDC*/
89 mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
90 mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
91
92 /* FEC RXD1 */
93 mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
94 mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
95 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
96
97 /* FEC RXD0 */
98 mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
99 mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
100 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
101
102 /* FEC TXD1 */
103 mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
104 mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
105
106 /* FEC TXD0 */
107 mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
108 mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
109
110 /* FEC TX_EN */
111 mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
112 mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
113
114 /* FEC TX_CLK */
115 mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
116 mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
117 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
118
119 /* FEC RX_ER */
120 mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
121 mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
122 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
123
124 /* FEC CRS */
125 mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
126 mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
127 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
128}
129
130#ifdef CONFIG_FSL_ESDHC
131struct fsl_esdhc_cfg esdhc_cfg[1] = {
132 {MMC_SDHC1_BASE_ADDR, 1},
133};
134
Thierry Reding314284b2012-01-02 01:15:36 +0000135int board_mmc_getcd(struct mmc *mmc)
Fabio Estevam860b32e2011-05-13 03:15:11 +0000136{
Fabio Estevam3ee37292011-11-15 05:51:32 +0000137 mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
Fabio Estevamc9d5fd12012-02-08 02:34:44 +0000138 gpio_direction_input(77);
Thierry Reding314284b2012-01-02 01:15:36 +0000139 return !gpio_get_value(77); /* GPIO3_13 */
Fabio Estevam860b32e2011-05-13 03:15:11 +0000140}
141
142int board_mmc_init(bd_t *bis)
143{
144 u32 index;
145 s32 status = 0;
146
147 for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
148 switch (index) {
149 case 0:
150 mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
151 mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
152 mxc_request_iomux(MX53_PIN_SD1_DATA0,
153 IOMUX_CONFIG_ALT0);
154 mxc_request_iomux(MX53_PIN_SD1_DATA1,
155 IOMUX_CONFIG_ALT0);
156 mxc_request_iomux(MX53_PIN_SD1_DATA2,
157 IOMUX_CONFIG_ALT0);
158 mxc_request_iomux(MX53_PIN_SD1_DATA3,
159 IOMUX_CONFIG_ALT0);
160 mxc_request_iomux(MX53_PIN_EIM_DA13,
161 IOMUX_CONFIG_ALT1);
162
163 mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
164 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
165 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
166 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
167 mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
168 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
169 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
170 PAD_CTL_DRV_HIGH);
171 mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
172 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
173 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
174 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
175 mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
176 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
177 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
178 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
179 mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
180 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
181 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
182 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
183 mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
184 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
185 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
186 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
187 break;
188
189 default:
190 printf("Warning: you configured more ESDHC controller"
191 "(%d) as supported by the board(1)\n",
192 CONFIG_SYS_FSL_ESDHC_NUM);
193 return status;
194 }
195 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
196 }
197
198 return status;
199}
200#endif
201
202int board_early_init_f(void)
203{
204 setup_iomux_uart();
205 setup_iomux_fec();
206
207 return 0;
208}
209
210int board_init(void)
211{
Fabio Estevam860b32e2011-05-13 03:15:11 +0000212 /* address of boot parameters */
213 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
214
215 return 0;
216}
217
218int checkboard(void)
219{
220 puts("Board: MX53SMD\n");
221
222 return 0;
223}