blob: 365322c6a59788bffaa4cfc3e3a8cdeae74057f8 [file] [log] [blame]
Ira W. Snyder98397092011-11-23 08:25:58 -08001/*
2 * Copyright 2009-2010 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __CONFIG_H
24#define __CONFIG_H
25
26/* The P2020COME board is only booted via the Freescale On-Chip ROM */
27#define CONFIG_SYS_RAMBOOT
28#define CONFIG_SYS_EXTRA_ENV_RELOC
29
30#define CONFIG_SYS_TEXT_BASE 0xf8f80000
31#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
32
33#ifdef CONFIG_SDCARD
34#define CONFIG_RAMBOOT_SDCARD 1
35#endif
36
37#ifdef CONFIG_SPIFLASH
38#define CONFIG_RAMBOOT_SPIFLASH 1
39#endif
40
41#ifndef CONFIG_SYS_MONITOR_BASE
42#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
43#endif
44
45/* High Level Configuration Options */
46#define CONFIG_BOOKE 1 /* BOOKE */
47#define CONFIG_E500 1 /* BOOKE e500 family */
48#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/P1020/P2020,etc*/
49#define CONFIG_P2020 1
50#define CONFIG_P2020COME 1
51#define CONFIG_FSL_ELBC 1 /* Enable eLBC Support */
52#define CONFIG_MP
53
54#define CONFIG_PCI 1 /* Enable PCI/PCIE */
55#if defined(CONFIG_PCI)
56#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
57#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
58#define CONFIG_PCIE3 1 /* PCIE controller 3 (slot 3) */
59
60#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
61#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
62#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
63#endif /* #if defined(CONFIG_PCI) */
64#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
65#define CONFIG_TSEC_ENET /* tsec ethernet support */
66#define CONFIG_ENV_OVERWRITE
67
68#if defined(CONFIG_PCI)
69#define CONFIG_E1000 1 /* E1000 pci Ethernet card */
70#endif
71
72#ifndef __ASSEMBLY__
73extern unsigned long get_board_ddr_clk(unsigned long dummy);
74extern unsigned long get_board_sys_clk(unsigned long dummy);
75#endif
76
77/*
78 * For P2020COME DDRCLK and SYSCLK are from the same oscillator
79 * For DA phase the SYSCLK is 66MHz
80 * For EA phase the SYSCLK is 100MHz
81 */
82#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0)
83#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
84
85#define CONFIG_HWCONFIG
86
87/*
88 * These can be toggled for performance analysis, otherwise use default.
89 */
90#define CONFIG_L2_CACHE /* toggle L2 cache */
91#define CONFIG_BTB /* toggle branch prediction */
92
93#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
94
95#define CONFIG_ENABLE_36BIT_PHYS 1
96
97#ifdef CONFIG_PHYS_64BIT
98#define CONFIG_ADDR_MAP 1
99#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
100#endif
101
102#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
103#define CONFIG_SYS_MEMTEST_END 0x1fffffff
104#define CONFIG_PANIC_HANG /* do not reset board on panic */
105
Ira W. Snyder98397092011-11-23 08:25:58 -0800106 /*
107 * Config the L2 Cache as L2 SRAM
108 */
109#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
110#ifdef CONFIG_PHYS_64BIT
111#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
112#else
113#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
114#endif
115#define CONFIG_SYS_L2_SIZE (512 << 10)
116#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR \
117 + CONFIG_SYS_L2_SIZE)
118
119#define CONFIG_SYS_CCSRBAR 0xffe00000
120#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
121
122/* DDR Setup */
123#define CONFIG_FSL_DDR3
124#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
125#define CONFIG_DDR_SPD
126
127#define CONFIG_DDR_ECC
128#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
129#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
130
131#define CONFIG_SYS_SDRAM_SIZE 2048ULL /* DDR size on P2020COME */
132#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
133#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
134
135#define CONFIG_NUM_DDR_CONTROLLERS 1
136#define CONFIG_DIMM_SLOTS_PER_CTLR 1
137#define CONFIG_CHIP_SELECTS_PER_CTRL 2
138
139#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
140#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
141#define CONFIG_SYS_DDR_SBE 0x00ff0000
142
143#define CONFIG_SYS_SPD_BUS_NUM 1
144#define SPD_EEPROM_ADDRESS 0x53
145
146/*
147 * Memory map
148 *
149 * 0x0000_0000 0x7fff_ffff DDR3 2G Cacheable
150 * 0x8000_0000 0x9fff_ffff PCI Express 3 Mem 1G non-cacheable
151 * 0xa000_0000 0xbfff_ffff PCI Express 2 Mem 1G non-cacheable
152 * 0xc000_0000 0xdfff_ffff PCI Express 1 Mem 1G non-cacheable
153 * 0xffc1_0000 0xffc1_ffff PCI Express 3 IO 64K non-cacheable
154 * 0xffc2_0000 0xffc2_ffff PCI Express 2 IO 64K non-cacheable
155 * 0xffc3_0000 0xffc3_ffff PCI Express 1 IO 64K non-cacheable
156 *
157 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
158 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
159 */
160
161/*
162 * Local Bus Definitions
163 */
164
165/* There is no NOR Flash on P2020COME */
166#define CONFIG_SYS_NO_FLASH
167
168#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
169#define CONFIG_HWCONFIG
170
171#define CONFIG_SYS_INIT_RAM_LOCK 1
172#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
173#ifdef CONFIG_PHYS_64BIT
174#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
175#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
176/* the assembler doesn't like typecast */
177#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
178 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
179 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
180#else
181#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
182#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
183#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
184#endif
185#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
186
187#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
188 - GENERATED_GBL_DATA_SIZE)
189#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
190
191#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
192#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
193
194/* Serial Port - controlled on board with jumper J8
195 * open - index 2
196 * shorted - index 1
197 */
198#define CONFIG_CONS_INDEX 1
199#define CONFIG_SYS_NS16550
200#define CONFIG_SYS_NS16550_SERIAL
201#define CONFIG_SYS_NS16550_REG_SIZE 1
202#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
203
204#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
205#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
206
207#define CONFIG_SYS_BAUDRATE_TABLE \
208 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
209
210#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
211#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
212
213/* Use the HUSH parser */
214#define CONFIG_SYS_HUSH_PARSER
215#ifdef CONFIG_SYS_HUSH_PARSER
216#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
217#endif
218
219/*
220 * Pass open firmware flat tree
221 */
222#define CONFIG_OF_LIBFDT 1
223#define CONFIG_OF_BOARD_SETUP 1
224#define CONFIG_OF_STDOUT_VIA_ALIAS 1
225
226/* new uImage format support */
227#define CONFIG_FIT 1
228#define CONFIG_FIT_VERBOSE 1
229
230/* I2C */
231#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
232#define CONFIG_HARD_I2C /* I2C with hardware support */
233#undef CONFIG_SOFT_I2C /* I2C bit-banged */
234#define CONFIG_I2C_MULTI_BUS
235#define CONFIG_I2C_CMD_TREE
236#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address*/
237#define CONFIG_SYS_I2C_SLAVE 0x7F
238#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
239#define CONFIG_SYS_I2C_OFFSET 0x3000
240#define CONFIG_SYS_I2C2_OFFSET 0x3100
241
242/*
243 * I2C2 EEPROM
244 */
245#define CONFIG_ID_EEPROM
246#ifdef CONFIG_ID_EEPROM
247#define CONFIG_SYS_I2C_EEPROM_NXID
248#endif
249#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
250#define CONFIG_SYS_I2C_EEPROM_ADDR2 0x18
251#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
252#define CONFIG_SYS_EEPROM_BUS_NUM 0
253#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
254
255/*
256 * eSPI - Enhanced SPI
257 */
258#define CONFIG_FSL_ESPI
259#define CONFIG_SPI_FLASH
260#define CONFIG_SPI_FLASH_STMICRO
261#define CONFIG_CMD_SF
262#define CONFIG_SF_DEFAULT_SPEED 10000000
263#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
264
265/*
266 * General PCI
267 * Memory space is mapped 1-1, but I/O space must start from 0.
268 */
269#if defined(CONFIG_PCI)
270
271/* controller 3, Slot 3, tgtid 3, Base address 8000 */
272#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
273#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
274#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
275#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
276#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc10000
277#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
278#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc10000
279#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
280
281/* controller 2, Slot 2, tgtid 2, Base address 9000 */
282#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
283#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
284#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
285#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
286#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
287#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
288#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
289#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
290
291/* controller 1, Slot 1, tgtid 1, Base address a000 */
292#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
293#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
294#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
295#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
296#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc30000
297#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
298#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc30000
299#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
300
301#define CONFIG_PCI_PNP /* do pci plug-and-play */
302
303#undef CONFIG_EEPRO100
304#undef CONFIG_TULIP
305#undef CONFIG_RTL8139
306
307#ifdef CONFIG_RTL8139
308/* This macro is used by RTL8139 but not defined in PPC architecture */
309#define KSEG1ADDR(x) (x)
310#define _IO_BASE 0x00000000
311#endif
312
Ira W. Snyder98397092011-11-23 08:25:58 -0800313#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
314#define CONFIG_DOS_PARTITION
315
316#endif /* CONFIG_PCI */
317
318#if defined(CONFIG_TSEC_ENET)
319#define CONFIG_MII 1 /* MII PHY management */
320#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
321#define CONFIG_TSEC1 1
322#define CONFIG_TSEC1_NAME "eTSEC1"
323#define CONFIG_TSEC2 1
324#define CONFIG_TSEC2_NAME "eTSEC2"
325#define CONFIG_TSEC3 1
326#define CONFIG_TSEC3_NAME "eTSEC3"
327
328#define TSEC1_PHY_ADDR 0
329#define TSEC2_PHY_ADDR 2
330#define TSEC3_PHY_ADDR 1
331
332#undef CONFIG_VSC7385_ENET
333
334#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
335#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
336#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
337
338#define TSEC1_PHYIDX 0
339#define TSEC2_PHYIDX 0
340#define TSEC3_PHYIDX 0
341
342#define CONFIG_ETHPRIME "eTSEC1"
343
344#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
345
346#endif /* CONFIG_TSEC_ENET */
347
348/*
349 * Environment
350 */
351#if defined(CONFIG_RAMBOOT_SDCARD)
352 #define CONFIG_ENV_IS_IN_MMC 1
Fabio Estevam4394d0c2012-01-11 09:20:50 +0000353 #define CONFIG_FSL_FIXED_MMC_LOCATION
Ira W. Snyder98397092011-11-23 08:25:58 -0800354 #define CONFIG_ENV_SIZE 0x2000
355 #define CONFIG_SYS_MMC_ENV_DEV 0
356#elif defined(CONFIG_RAMBOOT_SPIFLASH)
357 #define CONFIG_ENV_IS_IN_SPI_FLASH
358 #define CONFIG_ENV_SPI_BUS 0
359 #define CONFIG_ENV_SPI_CS 0
360 #define CONFIG_ENV_SPI_MAX_HZ 10000000
361 #define CONFIG_ENV_SPI_MODE 0
362 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
363 #define CONFIG_ENV_SECT_SIZE 0x10000
364 #define CONFIG_ENV_SIZE 0x2000
365#endif
366
367#define CONFIG_LOADS_ECHO 1
368#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
369
370/*
371 * Command line configuration.
372 */
373#include <config_cmd_default.h>
374
375#define CONFIG_CMD_ELF
376#define CONFIG_CMD_I2C
377#define CONFIG_CMD_IRQ
378#define CONFIG_CMD_MII
379#define CONFIG_CMD_PING
380#define CONFIG_CMD_SETEXPR
381#define CONFIG_CMD_REGINFO
382
383#if defined(CONFIG_PCI)
384#define CONFIG_CMD_NET
385#define CONFIG_CMD_PCI
386#endif
387
388#undef CONFIG_WATCHDOG /* watchdog disabled */
389
390#define CONFIG_MMC 1
391
392#ifdef CONFIG_MMC
393#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
394#define CONFIG_CMD_MMC
395#define CONFIG_DOS_PARTITION
396#define CONFIG_FSL_ESDHC
397#define CONFIG_GENERIC_MMC
398#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
399#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
400#endif /* CONFIG_MMC */
401
402#define CONFIG_USB_EHCI
403
404#ifdef CONFIG_USB_EHCI
405#define CONFIG_CMD_USB
406#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
407#define CONFIG_USB_EHCI_FSL
408#define CONFIG_USB_STORAGE
409#define CONFIG_HAS_FSL_DR_USB
410#endif
411
412#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
413#define CONFIG_CMD_EXT2
414#define CONFIG_CMD_FAT
415#define CONFIG_DOS_PARTITION
416#endif
417
418/* Misc Extra Settings */
419#define CONFIG_SYS_64BIT_VSPRINTF 1
420#define CONFIG_SYS_64BIT_STRTOUL 1
421#define CONFIG_CMD_DHCP 1
422
423#define CONFIG_CMD_DATE 1
424#define CONFIG_RTC_M41T62 1
425#define CONFIG_SYS_RTC_BUS_NUM 1
426#define CONFIG_SYS_I2C_RTC_ADDR 0x68
427
428/*
429 * Miscellaneous configurable options
430 */
431#define CONFIG_SYS_LONGHELP /* undef to save memory */
432#define CONFIG_CMDLINE_EDITING /* Command-line editing */
433#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
434#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
435#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
436#if defined(CONFIG_CMD_KGDB)
437#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
438#else
439#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
440#endif
441#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
442 /* Print Buffer Size */
443#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
444#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
445#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
446
447/*
448 * For booting Linux, the board info and command line data
449 * have to be in the first 64 MB of memory, since this is
450 * the maximum mapped by the Linux kernel during initialization.
451 */
452#define CONFIG_SYS_BOOTMAPSZ (64 << 20)
453#define CONFIG_SYS_BOOTM_LEN (64 << 20)
454
455#if defined(CONFIG_CMD_KGDB)
456#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
457#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
458#endif
459
460/*
461 * Environment Configuration
462 */
463
464/* The mac addresses for all ethernet interface */
465#if defined(CONFIG_TSEC_ENET)
466#define CONFIG_HAS_ETH0
467#define CONFIG_HAS_ETH1
468#define CONFIG_HAS_ETH2
469#define CONFIG_HAS_ETH3
470#endif
471
472#define CONFIG_HOSTNAME unknown
473#define CONFIG_ROOTPATH "/opt/nfsroot"
474#define CONFIG_BOOTFILE "uImage"
475#define CONFIG_UBOOTPATH u-boot.bin
476
477/* default location for tftp and bootm */
478#define CONFIG_LOADADDR 1000000
479
480#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
481#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
482
483#define CONFIG_BAUDRATE 115200
484
485#define CONFIG_EXTRA_ENV_SETTINGS \
486 "hwconfig=fsl_ddr:ecc=on\0" \
487 "bootcmd=run sdboot\0" \
488 "sdboot=setenv bootargs root=/dev/mmcblk0p2 rw " \
489 "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
490 "$othbootargs; mmcinfo; " \
491 "ext2load mmc 0:2 $loadaddr /boot/$bootfile; " \
492 "ext2load mmc 0:2 $fdtaddr /boot/$fdtfile; " \
493 "bootm $loadaddr - $fdtaddr\0" \
494 "sdfatboot=setenv bootargs root=/dev/ram rw " \
495 "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
496 "$othbootargs; mmcinfo; " \
497 "fatload mmc 0:1 $loadaddr $bootfile; " \
498 "fatload mmc 0:1 $fdtaddr $fdtfile; " \
499 "fatload mmc 0:1 $ramdiskaddr $ramdiskfile; " \
500 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
501 "usbboot=setenv bootargs root=/dev/sda1 rw " \
502 "rootdelay=$rootdelaysecond console=$consoledev,$baudrate "\
503 "$othbootargs; " \
504 "usb start; " \
505 "ext2load usb 0:1 $loadaddr /boot/$bootfile; " \
506 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile; " \
507 "bootm $loadaddr - $fdtaddr\0" \
508 "usbfatboot=setenv bootargs root=/dev/ram rw " \
509 "console=$consoledev,$baudrate $othbootargs; " \
510 "usb start; " \
511 "fatload usb 0:2 $loadaddr $bootfile; " \
512 "fatload usb 0:2 $fdtaddr $fdtfile; " \
513 "fatload usb 0:2 $ramdiskaddr $ramdiskfile; " \
514 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
515 "usbext2boot=setenv bootargs root=/dev/ram rw " \
516 "console=$consoledev,$baudrate $othbootargs; " \
517 "usb start; " \
518 "ext2load usb 0:4 $loadaddr $bootfile; " \
519 "ext2load usb 0:4 $fdtaddr $fdtfile; " \
520 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile; " \
521 "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \
522 "upgradespi=sf probe 0; " \
523 "setenv startaddr 0; " \
524 "setenv erasesize a0000; " \
525 "tftp 1000000 $tftppath/$uboot_spi; " \
526 "sf erase $startaddr $erasesize; " \
527 "sf write 1000000 $startaddr $filesize; " \
528 "sf erase 100000 120000\0" \
529 "clearspienv=sf probe 0;sf erase 100000 20000\0" \
530 "othbootargs=ramdisk_size=700000 cache-sram-size=0x10000\0" \
531 "netdev=eth0\0" \
532 "rootdelaysecond=15\0" \
533 "uboot_nor=u-boot-nor.bin\0" \
534 "uboot_spi=u-boot-p2020.spi\0" \
535 "uboot_sd=u-boot-p2020.bin\0" \
536 "consoledev=ttyS0\0" \
537 "ramdiskaddr=2000000\0" \
538 "ramdiskfile=rootfs-dev.ext2.img\0" \
539 "fdtaddr=c00000\0" \
540 "fdtfile=uImage-2.6.32-p2020.dtb\0" \
541 "tftppath=p2020\0"
542
543#define CONFIG_HDBOOT \
544 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
545 "console=$consoledev,$baudrate $othbootargs;" \
546 "usb start;" \
547 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
548 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
549 "bootm $loadaddr - $fdtaddr"
550
551#define CONFIG_NFSBOOTCOMMAND \
552 "setenv bootargs root=/dev/nfs rw " \
553 "nfsroot=$serverip:$rootpath " \
554 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off "\
555 "console=$consoledev,$baudrate $othbootargs;" \
556 "tftp $loadaddr $tftppath/$bootfile;" \
557 "tftp $fdtaddr $tftppath/$fdtfile;" \
558 "bootm $loadaddr - $fdtaddr"
559
Wolfgang Denk6b62b9a2011-12-19 12:03:40 +0100560
Ira W. Snyder98397092011-11-23 08:25:58 -0800561#define CONFIG_RAMBOOTCOMMAND \
562 "setenv bootargs root=/dev/ram rw " \
563 "console=$consoledev,$baudrate $othbootargs;" \
564 "tftp $ramdiskaddr $tftppath/$ramdiskfile;" \
565 "tftp $loadaddr $tftppath/$bootfile;" \
566 "tftp $fdtaddr $tftppath/$fdtfile;" \
567 "bootm $loadaddr $ramdiskaddr $fdtaddr"
568
569#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
570
571#endif /* __CONFIG_H */