blob: abbaeaad10b00fc9c4b44e42bc9a9213733c0cc4 [file] [log] [blame]
Peter Tyserccf0fdd2008-12-17 16:36:23 -06001/*
2 * Copyright 2008 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Peter Tyserccf0fdd2008-12-17 16:36:23 -06006 */
7
8/*
Peter Tyserc00ac252010-10-22 00:20:26 -05009 * xpedite537x board configuration file
Peter Tyserccf0fdd2008-12-17 16:36:23 -060010 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * High Level Configuration Options
16 */
Peter Tyserccf0fdd2008-12-17 16:36:23 -060017#define CONFIG_SYS_BOARD_NAME "XPedite5370"
John Schmoller92af65492010-10-22 00:20:24 -050018#define CONFIG_SYS_FORM_3U_VPX 1
Peter Tyserccf0fdd2008-12-17 16:36:23 -060019#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
Peter Tyserccf0fdd2008-12-17 16:36:23 -060020
Wolfgang Denk2ae18242010-10-06 09:05:45 +020021#ifndef CONFIG_SYS_TEXT_BASE
22#define CONFIG_SYS_TEXT_BASE 0xfff80000
23#endif
24
Peter Tyserccf0fdd2008-12-17 16:36:23 -060025#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040026#define CONFIG_PCIE1 1 /* PCIE controller 1 */
27#define CONFIG_PCIE2 1 /* PCIE controller 2 */
Peter Tyserccf0fdd2008-12-17 16:36:23 -060028#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000029#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Peter Tyserccf0fdd2008-12-17 16:36:23 -060030#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
31#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Peter Tyserccf0fdd2008-12-17 16:36:23 -060032
33/*
Peter Tyser48618122009-10-23 15:55:48 -050034 * Multicore config
35 */
36#define CONFIG_MP
37#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
38#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
39
40/*
Peter Tyserccf0fdd2008-12-17 16:36:23 -060041 * DDR config
42 */
Peter Tyserccf0fdd2008-12-17 16:36:23 -060043#undef CONFIG_FSL_DDR_INTERACTIVE
44#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
45#define CONFIG_DDR_SPD
46#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
47#define SPD_EEPROM_ADDRESS1 0x54 /* Both channels use the */
48#define SPD_EEPROM_ADDRESS2 0x54 /* same SPD data */
49#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
Peter Tyserccf0fdd2008-12-17 16:36:23 -060050#define CONFIG_DIMM_SLOTS_PER_CTLR 1
51#define CONFIG_CHIP_SELECTS_PER_CTRL 1
52#define CONFIG_DDR_ECC
53#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
54#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
55#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
56#define CONFIG_VERY_BIG_RAM
57
58#ifndef __ASSEMBLY__
59extern unsigned long get_board_sys_clk(unsigned long dummy);
60extern unsigned long get_board_ddr_clk(unsigned long dummy);
61#endif
62
63#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
64#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
65
66/*
67 * These can be toggled for performance analysis, otherwise use default.
68 */
69#define CONFIG_L2_CACHE /* toggle L2 cache */
70#define CONFIG_BTB /* toggle branch predition */
71#define CONFIG_ENABLE_36BIT_PHYS 1
72
Timur Tabie46fedf2011-08-04 18:03:41 -050073#define CONFIG_SYS_CCSRBAR 0xef000000
74#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Peter Tyserccf0fdd2008-12-17 16:36:23 -060075
76/*
77 * Diagnostics
78 */
79#define CONFIG_SYS_ALT_MEMTEST
80#define CONFIG_SYS_MEMTEST_START 0x10000000
81#define CONFIG_SYS_MEMTEST_END 0x20000000
Peter Tyser66a8b442010-10-22 00:20:33 -050082#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
83 CONFIG_SYS_POST_I2C)
Peter Tyser66a8b442010-10-22 00:20:33 -050084/* The XPedite5370 can host an XMC which has an EEPROM at address 0x50 */
85#define I2C_ADDR_IGNORE_LIST {0x50}
Peter Tyserccf0fdd2008-12-17 16:36:23 -060086
87/*
88 * Memory map
89 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
90 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
91 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
92 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
93 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
94 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
Peter Tyser48618122009-10-23 15:55:48 -050095 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
Peter Tyserccf0fdd2008-12-17 16:36:23 -060096 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
97 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
98 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
99 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
100 */
101
Kumar Gala202d9482009-09-15 22:21:58 -0500102#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600103
104/*
105 * NAND flash configuration
106 */
107#define CONFIG_SYS_NAND_BASE 0xef800000
108#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
Peter Tyser0a6d0c62009-07-21 13:51:08 -0500109#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
110 CONFIG_SYS_NAND_BASE2}
111#define CONFIG_SYS_MAX_NAND_DEVICE 2
Peter Tyser0a6d0c62009-07-21 13:51:08 -0500112#define CONFIG_NAND_FSL_ELBC
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600113
114/*
115 * NOR flash configuration
116 */
117#define CONFIG_SYS_FLASH_BASE 0xf8000000
118#define CONFIG_SYS_FLASH_BASE2 0xf0000000
119#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
120#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
121#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
122#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
123#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
124#define CONFIG_FLASH_CFI_DRIVER
125#define CONFIG_SYS_FLASH_CFI
Peter Tyser5ff82102009-07-19 19:17:40 -0500126#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600127#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
128 {0xf7f40000, 0xc0000} }
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200129#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600130
131/*
132 * Chip select configuration
133 */
134/* NOR Flash 0 on CS0 */
135#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
136 BR_PS_16 | \
137 BR_V)
138#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
139 OR_GPCM_CSNT | \
140 OR_GPCM_XACS | \
141 OR_GPCM_ACS_DIV2 | \
142 OR_GPCM_SCY_8 | \
143 OR_GPCM_TRLX | \
144 OR_GPCM_EHTR | \
145 OR_GPCM_EAD)
146
147/* NOR Flash 1 on CS1 */
148#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
149 BR_PS_16 | \
150 BR_V)
151#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
152
153/* NAND flash on CS2 */
154#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
155 (2<<BR_DECC_SHIFT) | \
156 BR_PS_8 | \
157 BR_MS_FCM | \
158 BR_V)
159
160/* NAND flash on CS2 */
161#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
162 OR_FCM_PGS | \
163 OR_FCM_CSCT | \
164 OR_FCM_CST | \
165 OR_FCM_CHT | \
166 OR_FCM_SCY_1 | \
167 OR_FCM_TRLX | \
168 OR_FCM_EHTR)
169
170/* NAND flash on CS3 */
171#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
172 (2<<BR_DECC_SHIFT) | \
173 BR_PS_8 | \
174 BR_MS_FCM | \
175 BR_V)
176#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
177
178/*
179 * Use L1 as initial stack
180 */
181#define CONFIG_SYS_INIT_RAM_LOCK 1
182#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200183#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600184
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200185#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600186#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
187
188#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
189#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
190
191/*
192 * Serial Port
193 */
194#define CONFIG_CONS_INDEX 1
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600195#define CONFIG_SYS_NS16550_SERIAL
196#define CONFIG_SYS_NS16550_REG_SIZE 1
197#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
198#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
199#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
200#define CONFIG_SYS_BAUDRATE_TABLE \
201 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600202#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
203#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
204
205/*
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600206 * I2C
207 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200208#define CONFIG_SYS_I2C
209#define CONFIG_SYS_I2C_FSL
210#define CONFIG_SYS_FSL_I2C_SPEED 400000
211#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
212#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
213#define CONFIG_SYS_FSL_I2C2_SPEED 400000
214#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
215#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
216#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600217
218/* PEX8518 slave I2C interface */
219#define CONFIG_SYS_I2C_PEX8518_ADDR 0x70
220
221/* I2C DS1631 temperature sensor */
Peter Tyser66a8b442010-10-22 00:20:33 -0500222#define CONFIG_SYS_I2C_LM90_ADDR 0x4c
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600223
224/* I2C EEPROM - AT24C128B */
225#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
226#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
227#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
228#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
229
230/* I2C RTC */
231#define CONFIG_RTC_M41T11 1
232#define CONFIG_SYS_I2C_RTC_ADDR 0x68
233#define CONFIG_SYS_M41T11_BASE_YEAR 2000
234
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600235/* GPIO */
236#define CONFIG_PCA953X
237#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
238#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
239#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
240#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
241#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
242
243/*
244 * PU = pulled high, PD = pulled low
245 * I = input, O = output, IO = input/output
246 */
247/* PCA9557 @ 0x18*/
248#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
249#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select */
250#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
251#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select */
252#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
253#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Set to 0 to enable NVM writing */
254#define CONFIG_SYS_PCA953X_C0_VCORE_VID2 0x40 /* VID2 of ISL6262 */
255#define CONFIG_SYS_PCA953X_C0_VCORE_VID3 0x80 /* VID3 of ISL6262 */
256
257/* PCA9557 @ 0x1c*/
258#define CONFIG_SYS_PCA953X_XMC0_ROOT0 0x01 /* PU; Low if XMC is RC */
259#define CONFIG_SYS_PCA953X_XMC0_MVMR0 0x02 /* XMC EEPROM write protect */
260#define CONFIG_SYS_PCA953X_XMC0_WAKE 0x04 /* PU; XMC wake */
261#define CONFIG_SYS_PCA953X_XMC0_BIST 0x08 /* PU; XMC built in self test */
262#define CONFIG_SYS_PCA953X_XMC_PRESENT 0x10 /* PU; Low if XMC module installed */
263#define CONFIG_SYS_PCA953X_PMC_PRESENT 0x20 /* PU; Low if PMC module installed */
264#define CONFIG_SYS_PCA953X_PMC0_MONARCH 0x40 /* PMC monarch mode enable */
265#define CONFIG_SYS_PCA953X_PMC0_EREADY 0x80 /* PU; PMC PCI eready */
266
267/* PCA9557 @ 0x1e*/
268#define CONFIG_SYS_PCA953X_P0_GA0 0x01 /* PU; VPX Geographical address */
269#define CONFIG_SYS_PCA953X_P0_GA1 0x02 /* PU; VPX Geographical address */
270#define CONFIG_SYS_PCA953X_P0_GA2 0x04 /* PU; VPX Geographical address */
271#define CONFIG_SYS_PCA953X_P0_GA3 0x08 /* PU; VPX Geographical address */
272#define CONFIG_SYS_PCA953X_P0_GA4 0x10 /* PU; VPX Geographical address */
273#define CONFIG_SYS_PCA953X_P0_GAP 0x20 /* PU; tied to VPX P0.GAP */
274#define CONFIG_SYS_PCA953X_P1_SYSEN 0x80 /* PU; Pulled high; tied to VPX P1.SYSCON */
275
276/* PCA9557 @ 0x1f */
277#define CONFIG_SYS_PCA953X_GPIO_VPX0 0x01 /* PU */
278#define CONFIG_SYS_PCA953X_GPIO_VPX1 0x02 /* PU */
279#define CONFIG_SYS_PCA953X_GPIO_VPX2 0x04 /* PU */
280#define CONFIG_SYS_PCA953X_GPIO_VPX3 0x08 /* PU */
281#define CONFIG_SYS_PCA953X_VPX_FRU_WRCTL 0x10 /* PD; I2C master source for FRU SEEPROM */
282
283/*
284 * General PCI
285 * Memory space is mapped 1-1, but I/O space must start from 0.
286 */
287/* PCIE1 - VPX P1 */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500288#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
289#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600290#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500291#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600292#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
293#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
294
295/* PCIE2 - PEX8518 */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500296#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000
297#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600298#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
Peter Tyser9660c5d2010-10-22 00:20:22 -0500299#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600300#define CONFIG_SYS_PCIE2_IO_PHYS 0xe8800000
301#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 /* 8M */
302
303/*
304 * Networking options
305 */
306#define CONFIG_TSEC_ENET /* tsec ethernet support */
307#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600308#define CONFIG_TSEC_TBI
309#define CONFIG_MII 1 /* MII PHY management */
310#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
311#define CONFIG_ETHPRIME "eTSEC2"
312
Kumar Gala72c96a62010-12-01 22:55:54 -0600313/*
314 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
315 * 1000mbps SGMII link
316 */
317#define CONFIG_TSEC_TBICR_SETTINGS ( \
318 TBICR_PHY_RESET \
319 | TBICR_FULL_DUPLEX \
320 | TBICR_SPEED1_SET \
321 )
322
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600323#define CONFIG_TSEC1 1
324#define CONFIG_TSEC1_NAME "eTSEC1"
325#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
326#define TSEC1_PHY_ADDR 1
327#define TSEC1_PHYIDX 0
328#define CONFIG_HAS_ETH0
329
330#define CONFIG_TSEC2 1
331#define CONFIG_TSEC2_NAME "eTSEC2"
332#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
333#define TSEC2_PHY_ADDR 2
334#define TSEC2_PHYIDX 0
335#define CONFIG_HAS_ETH1
336
337/*
338 * Command configuration.
339 */
Peter Tyser0a6d0c62009-07-21 13:51:08 -0500340#define CONFIG_CMD_NAND
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600341#define CONFIG_CMD_PCA953X
342#define CONFIG_CMD_PCA953X_INFO
343#define CONFIG_CMD_PCI
John Schmoller96d61602010-10-22 00:20:23 -0500344#define CONFIG_CMD_PCI_ENUM
Becky Bruce199e2622010-06-17 11:37:25 -0500345#define CONFIG_CMD_REGINFO
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600346
347/*
348 * Miscellaneous configurable options
349 */
350#define CONFIG_SYS_LONGHELP /* undef to save memory */
351#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600352#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
353#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
354#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
355#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600356#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillips5be58f52010-07-14 19:47:18 -0500357#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600358#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600359#define CONFIG_PANIC_HANG /* do not reset board on panic */
360#define CONFIG_PREBOOT /* enable preboot variable */
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600361#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
362
363/*
364 * For booting Linux, the board info and command line data
365 * have to be in the first 16 MB of memory, since this is
366 * the maximum mapped by the Linux kernel during initialization.
367 */
368#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
Peter Tyser39121c02009-07-21 13:51:07 -0500369#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600370
371/*
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600372 * Environment Configuration
373 */
374#define CONFIG_ENV_IS_IN_FLASH 1
375#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
376#define CONFIG_ENV_SIZE 0x8000
377#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
378
379/*
380 * Flash memory map:
381 * fff80000 - ffffffff Pri U-Boot (512 KB)
382 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
383 * fff00000 - fff3ffff Pri FDT (256KB)
384 * fef00000 - ffefffff Pri OS image (16MB)
385 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
386 *
387 * f7f80000 - f7ffffff Sec U-Boot (512 KB)
388 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
389 * f7f00000 - f7f3ffff Sec FDT (256KB)
390 * f6f00000 - f7efffff Sec OS image (16MB)
391 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
392 */
Marek Vasut5368c552012-09-23 17:41:24 +0200393#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
394#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
395#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
396#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
397#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
398#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600399
400#define CONFIG_PROG_UBOOT1 \
401 "$download_cmd $loadaddr $ubootfile; " \
402 "if test $? -eq 0; then " \
403 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
404 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
405 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
406 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
407 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
408 "if test $? -ne 0; then " \
409 "echo PROGRAM FAILED; " \
410 "else; " \
411 "echo PROGRAM SUCCEEDED; " \
412 "fi; " \
413 "else; " \
414 "echo DOWNLOAD FAILED; " \
415 "fi;"
416
417#define CONFIG_PROG_UBOOT2 \
418 "$download_cmd $loadaddr $ubootfile; " \
419 "if test $? -eq 0; then " \
420 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
421 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
422 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
423 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
424 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
425 "if test $? -ne 0; then " \
426 "echo PROGRAM FAILED; " \
427 "else; " \
428 "echo PROGRAM SUCCEEDED; " \
429 "fi; " \
430 "else; " \
431 "echo DOWNLOAD FAILED; " \
432 "fi;"
433
434#define CONFIG_BOOT_OS_NET \
435 "$download_cmd $osaddr $osfile; " \
436 "if test $? -eq 0; then " \
437 "if test -n $fdtaddr; then " \
438 "$download_cmd $fdtaddr $fdtfile; " \
439 "if test $? -eq 0; then " \
440 "bootm $osaddr - $fdtaddr; " \
441 "else; " \
442 "echo FDT DOWNLOAD FAILED; " \
443 "fi; " \
444 "else; " \
445 "bootm $osaddr; " \
446 "fi; " \
447 "else; " \
448 "echo OS DOWNLOAD FAILED; " \
449 "fi;"
450
451#define CONFIG_PROG_OS1 \
452 "$download_cmd $osaddr $osfile; " \
453 "if test $? -eq 0; then " \
454 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
455 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
456 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
457 "if test $? -ne 0; then " \
458 "echo OS PROGRAM FAILED; " \
459 "else; " \
460 "echo OS PROGRAM SUCCEEDED; " \
461 "fi; " \
462 "else; " \
463 "echo OS DOWNLOAD FAILED; " \
464 "fi;"
465
466#define CONFIG_PROG_OS2 \
467 "$download_cmd $osaddr $osfile; " \
468 "if test $? -eq 0; then " \
469 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
470 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
471 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
472 "if test $? -ne 0; then " \
473 "echo OS PROGRAM FAILED; " \
474 "else; " \
475 "echo OS PROGRAM SUCCEEDED; " \
476 "fi; " \
477 "else; " \
478 "echo OS DOWNLOAD FAILED; " \
479 "fi;"
480
481#define CONFIG_PROG_FDT1 \
482 "$download_cmd $fdtaddr $fdtfile; " \
483 "if test $? -eq 0; then " \
484 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
485 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
486 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
487 "if test $? -ne 0; then " \
488 "echo FDT PROGRAM FAILED; " \
489 "else; " \
490 "echo FDT PROGRAM SUCCEEDED; " \
491 "fi; " \
492 "else; " \
493 "echo FDT DOWNLOAD FAILED; " \
494 "fi;"
495
496#define CONFIG_PROG_FDT2 \
497 "$download_cmd $fdtaddr $fdtfile; " \
498 "if test $? -eq 0; then " \
499 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
500 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
501 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
502 "if test $? -ne 0; then " \
503 "echo FDT PROGRAM FAILED; " \
504 "else; " \
505 "echo FDT PROGRAM SUCCEEDED; " \
506 "fi; " \
507 "else; " \
508 "echo FDT DOWNLOAD FAILED; " \
509 "fi;"
510
511#define CONFIG_EXTRA_ENV_SETTINGS \
512 "autoload=yes\0" \
513 "download_cmd=tftp\0" \
514 "console_args=console=ttyS0,115200\0" \
515 "root_args=root=/dev/nfs rw\0" \
516 "misc_args=ip=on\0" \
517 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
518 "bootfile=/home/user/file\0" \
Peter Tyserc00ac252010-10-22 00:20:26 -0500519 "osfile=/home/user/board.uImage\0" \
520 "fdtfile=/home/user/board.dtb\0" \
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600521 "ubootfile=/home/user/u-boot.bin\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500522 "fdtaddr=0x1e00000\0" \
Peter Tyserccf0fdd2008-12-17 16:36:23 -0600523 "osaddr=0x1000000\0" \
524 "loadaddr=0x1000000\0" \
525 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
526 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
527 "prog_os1="CONFIG_PROG_OS1"\0" \
528 "prog_os2="CONFIG_PROG_OS2"\0" \
529 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
530 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
531 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
532 "bootcmd_flash1=run set_bootargs; " \
533 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
534 "bootcmd_flash2=run set_bootargs; " \
535 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
536 "bootcmd=run bootcmd_flash1\0"
537#endif /* __CONFIG_H */