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wdenkc6097192002-11-03 00:24:07 +00001/*
stroesec231d002003-05-23 11:32:53 +00002 * (C) Copyright 2001-2003
wdenkc6097192002-11-03 00:24:07 +00003 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <asm/processor.h>
27#include <command.h>
28
29/* ------------------------------------------------------------------------- */
30
31#ifdef FPGA_DEBUG
32#define DBG(x...) printf(x)
33#else
34#define DBG(x...)
35#endif /* DEBUG */
36
37#define MAX_ONES 226
38
wdenkc6097192002-11-03 00:24:07 +000039#ifdef CFG_FPGA_PRG
40# define FPGA_PRG CFG_FPGA_PRG /* FPGA program pin (ppc output)*/
41# define FPGA_CLK CFG_FPGA_CLK /* FPGA clk pin (ppc output) */
42# define FPGA_DATA CFG_FPGA_DATA /* FPGA data pin (ppc output) */
43# define FPGA_DONE CFG_FPGA_DONE /* FPGA done pin (ppc input) */
44# define FPGA_INIT CFG_FPGA_INIT /* FPGA init pin (ppc input) */
45#else
46# define FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
47# define FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
48# define FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
49# define FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */
50# define FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */
51#endif
52
53#define ERROR_FPGA_PRG_INIT_LOW -1 /* Timeout after PRG* asserted */
54#define ERROR_FPGA_PRG_INIT_HIGH -2 /* Timeout after PRG* deasserted */
55#define ERROR_FPGA_PRG_DONE -3 /* Timeout after programming */
56
stroesec231d002003-05-23 11:32:53 +000057#define SET_FPGA(data) out32(GPIO0_OR, data)
wdenkc6097192002-11-03 00:24:07 +000058
59#define FPGA_WRITE_1 { \
wdenk8bde7f72003-06-27 21:31:46 +000060 SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
61 SET_FPGA(FPGA_PRG | FPGA_DATA); /* set data to 1 */ \
62 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set clock to 1 */ \
63 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
wdenkc6097192002-11-03 00:24:07 +000064
65#define FPGA_WRITE_0 { \
wdenk8bde7f72003-06-27 21:31:46 +000066 SET_FPGA(FPGA_PRG | FPGA_DATA); /* set clock to 0 */ \
67 SET_FPGA(FPGA_PRG); /* set data to 0 */ \
68 SET_FPGA(FPGA_PRG | FPGA_CLK); /* set clock to 1 */ \
69 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);} /* set data to 1 */
wdenkc6097192002-11-03 00:24:07 +000070
71
72static int fpga_boot(unsigned char *fpgadata, int size)
73{
74 int i,index,len;
75 int count;
76#ifdef CFG_FPGA_SPARTAN2
77 int j;
78#else
79 unsigned char b;
80 int bit;
81#endif
82
83 /* display infos on fpgaimage */
84 index = 15;
85 for (i=0; i<4; i++)
86 {
87 len = fpgadata[index];
88 DBG("FPGA: %s\n", &(fpgadata[index+1]));
89 index += len+3;
90 }
91
92#ifdef CFG_FPGA_SPARTAN2
93 /* search for preamble 0xFFFFFFFF */
94 while (1)
95 {
96 if ((fpgadata[index] == 0xff) && (fpgadata[index+1] == 0xff) &&
wdenk8bde7f72003-06-27 21:31:46 +000097 (fpgadata[index+2] == 0xff) && (fpgadata[index+3] == 0xff))
98 break; /* preamble found */
wdenkc6097192002-11-03 00:24:07 +000099 else
wdenk8bde7f72003-06-27 21:31:46 +0000100 index++;
wdenkc6097192002-11-03 00:24:07 +0000101 }
102#else
103 /* search for preamble 0xFF2X */
104 for (index = 0; index < size-1 ; index++)
105 {
106 if ((fpgadata[index] == 0xff) && ((fpgadata[index+1] & 0xf0) == 0x30))
107 break;
108 }
109 index += 2;
110#endif
111
112 DBG("FPGA: configdata starts at position 0x%x\n",index);
113 DBG("FPGA: length of fpga-data %d\n", size-index);
114
115 /*
116 * Setup port pins for fpga programming
117 */
stroesec231d002003-05-23 11:32:53 +0000118 out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
119 out32(GPIO0_TCR, in32(GPIO0_TCR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* setup for output */
120 out32(GPIO0_OR, in32(GPIO0_OR) | FPGA_PRG | FPGA_CLK | FPGA_DATA); /* set pins to high */
wdenkc6097192002-11-03 00:24:07 +0000121
stroesec231d002003-05-23 11:32:53 +0000122 DBG("%s, ",((in32(GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
123 DBG("%s\n",((in32(GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
wdenkc6097192002-11-03 00:24:07 +0000124
125 /*
126 * Init fpga by asserting and deasserting PROGRAM*
127 */
128 SET_FPGA(FPGA_CLK | FPGA_DATA);
129
130 /* Wait for FPGA init line low */
131 count = 0;
stroesec231d002003-05-23 11:32:53 +0000132 while (in32(GPIO0_IR) & FPGA_INIT)
wdenkc6097192002-11-03 00:24:07 +0000133 {
134 udelay(1000); /* wait 1ms */
135 /* Check for timeout - 100us max, so use 3ms */
136 if (count++ > 3)
wdenk8bde7f72003-06-27 21:31:46 +0000137 {
138 DBG("FPGA: Booting failed!\n");
139 return ERROR_FPGA_PRG_INIT_LOW;
140 }
wdenkc6097192002-11-03 00:24:07 +0000141 }
142
stroesec231d002003-05-23 11:32:53 +0000143 DBG("%s, ",((in32(GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
144 DBG("%s\n",((in32(GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
wdenkc6097192002-11-03 00:24:07 +0000145
146 /* deassert PROGRAM* */
147 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
148
149 /* Wait for FPGA end of init period . */
150 count = 0;
stroesec231d002003-05-23 11:32:53 +0000151 while (!(in32(GPIO0_IR) & FPGA_INIT))
wdenkc6097192002-11-03 00:24:07 +0000152 {
153 udelay(1000); /* wait 1ms */
154 /* Check for timeout */
155 if (count++ > 3)
wdenk8bde7f72003-06-27 21:31:46 +0000156 {
157 DBG("FPGA: Booting failed!\n");
158 return ERROR_FPGA_PRG_INIT_HIGH;
159 }
wdenkc6097192002-11-03 00:24:07 +0000160 }
161
stroesec231d002003-05-23 11:32:53 +0000162 DBG("%s, ",((in32(GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
163 DBG("%s\n",((in32(GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
wdenkc6097192002-11-03 00:24:07 +0000164
165 DBG("write configuration data into fpga\n");
166 /* write configuration-data into fpga... */
167
168#ifdef CFG_FPGA_SPARTAN2
169 /*
170 * Load uncompressed image into fpga
171 */
172 for (i=index; i<size; i++)
173 {
174 for (j=0; j<8; j++)
wdenk8bde7f72003-06-27 21:31:46 +0000175 {
176 if ((fpgadata[i] & 0x80) == 0x80)
wdenkc6097192002-11-03 00:24:07 +0000177 {
wdenk8bde7f72003-06-27 21:31:46 +0000178 FPGA_WRITE_1;
wdenkc6097192002-11-03 00:24:07 +0000179 }
wdenk8bde7f72003-06-27 21:31:46 +0000180 else
wdenkc6097192002-11-03 00:24:07 +0000181 {
wdenk8bde7f72003-06-27 21:31:46 +0000182 FPGA_WRITE_0;
wdenkc6097192002-11-03 00:24:07 +0000183 }
wdenk8bde7f72003-06-27 21:31:46 +0000184 fpgadata[i] <<= 1;
185 }
wdenkc6097192002-11-03 00:24:07 +0000186 }
187#else
188 /* send 0xff 0x20 */
189 FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1;
190 FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1; FPGA_WRITE_1;
191 FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_1; FPGA_WRITE_0;
192 FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_0; FPGA_WRITE_0;
193
194 /*
195 ** Bit_DeCompression
196 ** Code 1 .. maxOnes : n '1's followed by '0'
197 ** maxOnes + 1 .. maxOnes + 1 : n - 1 '1's no '0'
198 ** maxOnes + 2 .. 254 : n - (maxOnes + 2) '0's followed by '1'
199 ** 255 : '1'
200 */
201
202 for (i=index; i<size; i++)
203 {
204 b = fpgadata[i];
205 if ((b >= 1) && (b <= MAX_ONES))
206 {
207 for(bit=0; bit<b; bit++)
wdenk8bde7f72003-06-27 21:31:46 +0000208 {
209 FPGA_WRITE_1;
210 }
wdenkc6097192002-11-03 00:24:07 +0000211 FPGA_WRITE_0;
212 }
213 else if (b == (MAX_ONES+1))
214 {
215 for(bit=1; bit<b; bit++)
wdenk8bde7f72003-06-27 21:31:46 +0000216 {
217 FPGA_WRITE_1;
218 }
wdenkc6097192002-11-03 00:24:07 +0000219 }
220 else if ((b >= (MAX_ONES+2)) && (b <= 254))
221 {
222 for(bit=0; bit<(b-(MAX_ONES+2)); bit++)
wdenk8bde7f72003-06-27 21:31:46 +0000223 {
224 FPGA_WRITE_0;
225 }
226 FPGA_WRITE_1;
wdenkc6097192002-11-03 00:24:07 +0000227 }
228 else if (b == 255)
wdenk8bde7f72003-06-27 21:31:46 +0000229 {
230 FPGA_WRITE_1;
231 }
wdenkc6097192002-11-03 00:24:07 +0000232 }
233#endif
234
stroesec231d002003-05-23 11:32:53 +0000235 DBG("%s, ",((in32(GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE" );
236 DBG("%s\n",((in32(GPIO0_IR) & FPGA_INIT) == 0) ? "NOT INIT" : "INIT" );
wdenkc6097192002-11-03 00:24:07 +0000237
238 /*
239 * Check if fpga's DONE signal - correctly booted ?
240 */
241
242 /* Wait for FPGA end of programming period . */
243 count = 0;
stroesec231d002003-05-23 11:32:53 +0000244 while (!(in32(GPIO0_IR) & FPGA_DONE))
wdenkc6097192002-11-03 00:24:07 +0000245 {
246 udelay(1000); /* wait 1ms */
247 /* Check for timeout */
248 if (count++ > 3)
wdenk8bde7f72003-06-27 21:31:46 +0000249 {
250 DBG("FPGA: Booting failed!\n");
251 return ERROR_FPGA_PRG_DONE;
252 }
wdenkc6097192002-11-03 00:24:07 +0000253 }
254
255 DBG("FPGA: Booting successful!\n");
256 return 0;
257}