York Sun | 1cb19fb | 2013-06-27 10:48:29 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2013 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or |
| 5 | * modify it under the terms of the GNU General Public License as |
| 6 | * published by the Free Software Foundation; either version 2 of |
| 7 | * the License, or (at your option) any later version. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program; if not, write to the Free Software |
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 17 | * MA 02111-1307 USA |
| 18 | */ |
| 19 | |
| 20 | #ifndef __DDR_H__ |
| 21 | #define __DDR_H__ |
| 22 | struct board_specific_parameters { |
| 23 | u32 n_ranks; |
| 24 | u32 datarate_mhz_high; |
| 25 | u32 rank_gb; |
| 26 | u32 clk_adjust; |
| 27 | u32 wrlvl_start; |
| 28 | u32 wrlvl_ctl_2; |
| 29 | u32 wrlvl_ctl_3; |
| 30 | u32 cpo; |
| 31 | u32 write_data_delay; |
| 32 | u32 force_2T; |
| 33 | }; |
| 34 | |
| 35 | /* |
| 36 | * These tables contain all valid speeds we want to override with board |
| 37 | * specific parameters. datarate_mhz_high values need to be in ascending order |
| 38 | * for each n_ranks group. |
| 39 | */ |
| 40 | |
| 41 | #ifdef CONFIG_T4240QDS |
| 42 | static const struct board_specific_parameters udimm0[] = { |
| 43 | /* |
| 44 | * memory controller 0 |
| 45 | * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T |
| 46 | * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | |
| 47 | */ |
| 48 | {2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, |
| 49 | {2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0}, |
| 50 | {2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0}, |
| 51 | {2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0}, |
| 52 | {2, 1900, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, |
| 53 | {2, 2140, 0, 4, 8, 0x090a0b0e, 0x0f11120c, 0xff, 2, 0}, |
| 54 | {1, 1350, 0, 5, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0}, |
| 55 | {1, 1700, 0, 5, 8, 0x080a0a0c, 0x0c0d0e0a, 0xff, 2, 0}, |
| 56 | {1, 1900, 0, 4, 8, 0x080a0a0c, 0x0e0e0f0a, 0xff, 2, 0}, |
| 57 | {1, 2140, 0, 4, 8, 0x090a0b0c, 0x0e0f100b, 0xff, 2, 0}, |
| 58 | {} |
| 59 | }; |
| 60 | |
| 61 | static const struct board_specific_parameters rdimm0[] = { |
| 62 | /* |
| 63 | * memory controller 0 |
| 64 | * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T |
| 65 | * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | |
| 66 | */ |
York Sun | 5ecf41c | 2013-06-25 11:37:46 -0700 | [diff] [blame] | 67 | {4, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, |
| 68 | {4, 1666, 0, 5, 11, 0x0a080706, 0x07090906, 0xff, 2, 0}, |
| 69 | {4, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, |
| 70 | {2, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, |
| 71 | {2, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, |
| 72 | {2, 2140, 0, 5, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, |
| 73 | {1, 1350, 0, 5, 9, 0x08070605, 0x06070806, 0xff, 2, 0}, |
| 74 | {1, 1666, 0, 5, 11, 0x0a090806, 0x08090a06, 0xff, 2, 0}, |
| 75 | {1, 2140, 0, 4, 12, 0x0b090807, 0x080a0b07, 0xff, 2, 0}, |
York Sun | 1cb19fb | 2013-06-27 10:48:29 -0700 | [diff] [blame] | 76 | {} |
| 77 | }; |
| 78 | |
| 79 | #else /* CONFIG_T4240EMU */ |
| 80 | static const struct board_specific_parameters udimm0[] = { |
| 81 | /* |
| 82 | * memory controller 0 |
| 83 | * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T |
| 84 | * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | |
| 85 | */ |
| 86 | {2, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0}, |
| 87 | {1, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0}, |
| 88 | {} |
| 89 | }; |
| 90 | |
| 91 | static const struct board_specific_parameters rdimm0[] = { |
| 92 | /* |
| 93 | * memory controller 0 |
| 94 | * num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T |
| 95 | * ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay | |
| 96 | */ |
| 97 | {4, 2140, 0, 5, 8, 0x0, 0x0, 0xff, 2, 0}, |
| 98 | {2, 2140, 0, 5, 8, 0x0, 0x0, 0xff, 2, 0}, |
| 99 | {1, 2140, 0, 4, 8, 0x0, 0x0, 0xff, 2, 0}, |
| 100 | {} |
| 101 | }; |
| 102 | #endif /* CONFIG_T4240EMU */ |
| 103 | |
| 104 | /* |
| 105 | * The three slots have slightly different timing. The center values are good |
| 106 | * for all slots. We use identical speed tables for them. In future use, if |
| 107 | * DIMMs require separated tables, make more entries as needed. |
| 108 | */ |
| 109 | static const struct board_specific_parameters *udimms[] = { |
| 110 | udimm0, |
| 111 | }; |
| 112 | |
| 113 | /* |
| 114 | * The three slots have slightly different timing. See comments above. |
| 115 | */ |
| 116 | static const struct board_specific_parameters *rdimms[] = { |
| 117 | rdimm0, |
| 118 | }; |
| 119 | |
| 120 | |
| 121 | #endif |