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Stefan Roese887e2ec2006-09-07 11:51:23 +02001/*
2 * (C) Copyright 2006
Stefan Roese02388982007-01-05 10:38:05 +01003 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
4 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
5 * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
6 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
7 * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
8 *
Stefan Roese07b7b002007-03-06 07:47:04 +01009 * (C) Copyright 2006-2007
Stefan Roese887e2ec2006-09-07 11:51:23 +020010 * Stefan Roese, DENX Software Engineering, sr@denx.de.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
Stefan Roese02388982007-01-05 10:38:05 +010028/* define DEBUG for debug output */
29#undef DEBUG
30
Stefan Roese887e2ec2006-09-07 11:51:23 +020031#include <common.h>
32#include <asm/processor.h>
Stefan Roese02388982007-01-05 10:38:05 +010033#include <asm/io.h>
Stefan Roese887e2ec2006-09-07 11:51:23 +020034#include <ppc440.h>
35
Stefan Roese02388982007-01-05 10:38:05 +010036/*-----------------------------------------------------------------------------+
Larry Johnsonce3902e2007-12-30 01:00:50 -050037 * Prototypes
38 *-----------------------------------------------------------------------------*/
39extern int denali_wait_for_dlllock(void);
40extern void denali_core_search_data_eye(void);
Stefan Roese02388982007-01-05 10:38:05 +010041
Stefan Roesef544ff62007-05-05 08:29:01 +020042#if defined(CONFIG_NAND_SPL)
43/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
44 * for the 4k NAND boot image so define bus_frequency to 133MHz here
45 * which is save for the refresh counter setup.
46 */
47#define get_bus_freq(val) 133000000
48#endif
49
Stefan Roese887e2ec2006-09-07 11:51:23 +020050/*************************************************************************
51 *
52 * initdram -- 440EPx's DDR controller is a DENALI Core
53 *
54 ************************************************************************/
55long int initdram (int board_type)
56{
57#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
Stefan Roese9d909602007-06-01 15:29:04 +020058#if !defined(CONFIG_NAND_SPL)
Stefan Roese07b7b002007-03-06 07:47:04 +010059 ulong speed = get_bus_freq(0);
Stefan Roese9d909602007-06-01 15:29:04 +020060#else
61 ulong speed = 133333333; /* 133MHz is on the safe side */
62#endif
Stefan Roese07b7b002007-03-06 07:47:04 +010063
Stefan Roese887e2ec2006-09-07 11:51:23 +020064 mtsdram(DDR0_02, 0x00000000);
65
Stefan Roese887e2ec2006-09-07 11:51:23 +020066 mtsdram(DDR0_00, 0x0000190A);
67 mtsdram(DDR0_01, 0x01000000);
68 mtsdram(DDR0_03, 0x02030602);
Stefan Roese07b7b002007-03-06 07:47:04 +010069 mtsdram(DDR0_04, 0x0A020200);
70 mtsdram(DDR0_05, 0x02020308);
71 mtsdram(DDR0_06, 0x0102C812);
Stefan Roese887e2ec2006-09-07 11:51:23 +020072 mtsdram(DDR0_07, 0x000D0100);
Stefan Roese07b7b002007-03-06 07:47:04 +010073 mtsdram(DDR0_08, 0x02430001);
Stefan Roese887e2ec2006-09-07 11:51:23 +020074 mtsdram(DDR0_09, 0x00011D5F);
75 mtsdram(DDR0_10, 0x00000300);
76 mtsdram(DDR0_11, 0x0027C800);
77 mtsdram(DDR0_12, 0x00000003);
78 mtsdram(DDR0_14, 0x00000000);
79 mtsdram(DDR0_17, 0x19000000);
80 mtsdram(DDR0_18, 0x19191919);
81 mtsdram(DDR0_19, 0x19191919);
82 mtsdram(DDR0_20, 0x0B0B0B0B);
83 mtsdram(DDR0_21, 0x0B0B0B0B);
84 mtsdram(DDR0_22, 0x00267F0B);
85 mtsdram(DDR0_23, 0x00000000);
86 mtsdram(DDR0_24, 0x01010002);
Stefan Roesef544ff62007-05-05 08:29:01 +020087 if (speed > 133333334)
Stefan Roese07b7b002007-03-06 07:47:04 +010088 mtsdram(DDR0_26, 0x5B26050C);
89 else
90 mtsdram(DDR0_26, 0x5B260408);
Stefan Roese887e2ec2006-09-07 11:51:23 +020091 mtsdram(DDR0_27, 0x0000682B);
92 mtsdram(DDR0_28, 0x00000000);
93 mtsdram(DDR0_31, 0x00000000);
94 mtsdram(DDR0_42, 0x01000006);
Stefan Roese07b7b002007-03-06 07:47:04 +010095 mtsdram(DDR0_43, 0x030A0200);
96 mtsdram(DDR0_44, 0x00000003);
Stefan Roese887e2ec2006-09-07 11:51:23 +020097 mtsdram(DDR0_02, 0x00000001);
98
Larry Johnsonce3902e2007-12-30 01:00:50 -050099 denali_wait_for_dlllock();
Stefan Roese887e2ec2006-09-07 11:51:23 +0200100#endif /* #ifndef CONFIG_NAND_U_BOOT */
101
Stefan Roese02388982007-01-05 10:38:05 +0100102#ifdef CONFIG_DDR_DATA_EYE
103 /* -----------------------------------------------------------+
104 * Perform data eye search if requested.
105 * ----------------------------------------------------------*/
Larry Johnsonce3902e2007-12-30 01:00:50 -0500106 denali_core_search_data_eye();
Stefan Roese02388982007-01-05 10:38:05 +0100107#endif
108
Stefan Roese887e2ec2006-09-07 11:51:23 +0200109 return (CFG_MBYTES_SDRAM << 20);
110}