Masahiro Yamada | 5894ca0 | 2014-10-03 19:21:06 +0900 | [diff] [blame] | 1 | /* |
Masahiro Yamada | ce3a639 | 2015-03-23 00:07:26 +0900 | [diff] [blame^] | 2 | * Copyright (C) 2012-2015 Panasonic Corporation |
| 3 | * Copyright (C) 2015 Socionext Inc. |
| 4 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> |
Masahiro Yamada | 5894ca0 | 2014-10-03 19:21:06 +0900 | [diff] [blame] | 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | #include <config.h> |
| 10 | #include <linux/linkage.h> |
Masahiro Yamada | 105a9e7 | 2015-02-27 02:27:06 +0900 | [diff] [blame] | 11 | #include <linux/sizes.h> |
Masahiro Yamada | 5894ca0 | 2014-10-03 19:21:06 +0900 | [diff] [blame] | 12 | #include <asm/system.h> |
Masahiro Yamada | a86ac95 | 2015-02-27 02:26:44 +0900 | [diff] [blame] | 13 | #include <mach/led.h> |
| 14 | #include <mach/arm-mpcore.h> |
| 15 | #include <mach/sbc-regs.h> |
Masahiro Yamada | 105a9e7 | 2015-02-27 02:27:06 +0900 | [diff] [blame] | 16 | #include <mach/ssc-regs.h> |
Masahiro Yamada | 5894ca0 | 2014-10-03 19:21:06 +0900 | [diff] [blame] | 17 | |
| 18 | ENTRY(lowlevel_init) |
| 19 | mov r8, lr @ persevere link reg across call |
| 20 | |
| 21 | /* |
| 22 | * The UniPhier Boot ROM loads SPL code to the L2 cache. |
| 23 | * But CPUs can only do instruction fetch now because start.S has |
| 24 | * cleared C and M bits. |
| 25 | * First we need to turn on MMU and Dcache again to get back |
| 26 | * data access to L2. |
| 27 | */ |
| 28 | mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) |
| 29 | orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache |
| 30 | mcr p15, 0, r0, c1, c0, 0 |
| 31 | |
Masahiro Yamada | b4ad44b | 2015-01-06 14:28:16 +0900 | [diff] [blame] | 32 | #ifdef CONFIG_DEBUG_LL |
| 33 | bl setup_lowlevel_debug |
| 34 | #endif |
| 35 | |
Masahiro Yamada | 5894ca0 | 2014-10-03 19:21:06 +0900 | [diff] [blame] | 36 | /* |
| 37 | * Now we are using the page table embedded in the Boot ROM. |
| 38 | * It is not handy since it is not a straight mapped table for sLD3. |
| 39 | * What we need to do next is to switch over to the page table in SPL. |
| 40 | */ |
| 41 | ldr r3, =init_page_table @ page table must be 16KB aligned |
| 42 | |
| 43 | /* Disable MMU and Dcache before switching Page Table */ |
| 44 | mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) |
| 45 | bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache |
| 46 | mcr p15, 0, r0, c1, c0, 0 |
| 47 | |
| 48 | bl enable_mmu |
| 49 | |
| 50 | #ifdef CONFIG_UNIPHIER_SMP |
| 51 | /* |
| 52 | * ACTLR (Auxiliary Control Register) for Cortex-A9 |
| 53 | * bit[9] Parity on |
| 54 | * bit[8] Alloc in one way |
| 55 | * bit[7] EXCL (Exclusive cache bit) |
| 56 | * bit[6] SMP |
| 57 | * bit[3] Write full line of zeros mode |
| 58 | * bit[2] L1 Prefetch enable |
| 59 | * bit[1] L2 prefetch enable |
| 60 | * bit[0] FW (Cache and TLB maintenance broadcast) |
| 61 | */ |
| 62 | mrc p15, 0, r0, c1, c0, 1 @ ACTLR (Auxiliary Control Register) |
| 63 | orr r0, r0, #0x41 @ enable SMP, FW bit |
| 64 | mcr p15, 0, r0, c1, c0, 1 |
| 65 | |
| 66 | /* branch by CPU ID */ |
| 67 | mrc p15, 0, r0, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Register) |
| 68 | and r0, r0, #0x3 |
| 69 | cmp r0, #0x0 |
| 70 | beq primary_cpu |
| 71 | ldr r1, =ROM_BOOT_ROMRSV2 |
| 72 | mov r0, #0 |
| 73 | str r0, [r1] |
| 74 | 0: wfe |
| 75 | ldr r0, [r1] |
| 76 | cmp r0, #0 |
| 77 | beq 0b |
| 78 | bx r0 @ r0: entry point of U-Boot main for the secondary CPU |
| 79 | primary_cpu: |
| 80 | ldr r1, =ROM_BOOT_ROMRSV2 |
| 81 | ldr r0, =_start @ entry for the secondary CPU |
| 82 | str r0, [r1] |
| 83 | ldr r0, [r1] @ make sure str is complete before sev |
| 84 | sev @ kick the sedoncary CPU |
| 85 | mrc p15, 4, r1, c15, c0, 0 @ Configuration Base Address Register |
| 86 | bfc r1, #0, #13 @ clear bit 12-0 |
| 87 | mov r0, #-1 |
| 88 | str r0, [r1, #SCU_INV_ALL] @ SCU Invalidate All Register |
| 89 | mov r0, #1 @ SCU enable |
| 90 | str r0, [r1, #SCU_CTRL] @ SCU Control Register |
| 91 | #endif |
| 92 | |
| 93 | bl setup_init_ram @ RAM area for temporary stack pointer |
| 94 | |
| 95 | mov lr, r8 @ restore link |
| 96 | mov pc, lr @ back to my caller |
| 97 | ENDPROC(lowlevel_init) |
| 98 | |
| 99 | ENTRY(enable_mmu) |
| 100 | mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register) |
| 101 | bic r0, r0, #0x37 |
| 102 | orr r0, r0, #0x20 @ disable TTBR1 |
| 103 | mcr p15, 0, r0, c2, c0, 2 |
| 104 | |
| 105 | orr r0, r3, #0x8 @ Outer Cacheability for table walks: WBWA |
| 106 | mcr p15, 0, r0, c2, c0, 0 @ TTBR0 |
| 107 | |
| 108 | mov r0, #0 |
| 109 | mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs |
| 110 | |
| 111 | mov r0, #-1 @ manager for all domains (No permission check) |
| 112 | mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register) |
| 113 | |
| 114 | dsb |
| 115 | isb |
| 116 | /* |
| 117 | * MMU on: |
| 118 | * TLBs was already invalidated in "../start.S" |
| 119 | * So, we don't need to invalidate it here. |
| 120 | */ |
| 121 | mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Contrl Register) |
| 122 | orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable |
| 123 | mcr p15, 0, r0, c1, c0, 0 |
| 124 | |
| 125 | mov pc, lr |
| 126 | ENDPROC(enable_mmu) |
| 127 | |
Masahiro Yamada | 105a9e7 | 2015-02-27 02:27:06 +0900 | [diff] [blame] | 128 | /* |
| 129 | * For PH1-Pro4 or older SoCs, the size of WAY is 32KB. |
| 130 | * It is large enough for tmp RAM. |
| 131 | */ |
| 132 | #define BOOT_RAM_SIZE (SZ_32K) |
Masahiro Yamada | 5894ca0 | 2014-10-03 19:21:06 +0900 | [diff] [blame] | 133 | #define BOOT_WAY_BITS (0x00000100) /* way 8 */ |
| 134 | |
| 135 | ENTRY(setup_init_ram) |
| 136 | /* |
| 137 | * Touch to zero for the boot way |
| 138 | */ |
| 139 | 0: |
| 140 | /* |
| 141 | * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order |
| 142 | */ |
| 143 | ldr r0, = 0x00408006 @ touch to zero with address range |
| 144 | ldr r1, = SSCOQM |
| 145 | str r0, [r1] |
Masahiro Yamada | ce3a639 | 2015-03-23 00:07:26 +0900 | [diff] [blame^] | 146 | ldr r0, = (CONFIG_SPL_STACK - BOOT_RAM_SIZE) @ base address |
Masahiro Yamada | 5894ca0 | 2014-10-03 19:21:06 +0900 | [diff] [blame] | 147 | ldr r1, = SSCOQAD |
| 148 | str r0, [r1] |
| 149 | ldr r0, = BOOT_RAM_SIZE |
| 150 | ldr r1, = SSCOQSZ |
| 151 | str r0, [r1] |
| 152 | ldr r0, = BOOT_WAY_BITS |
| 153 | ldr r1, = SSCOQWN |
| 154 | str r0, [r1] |
| 155 | ldr r1, = SSCOPPQSEF |
| 156 | ldr r0, [r1] |
| 157 | cmp r0, #0 @ check if the command is successfully set |
| 158 | bne 0b @ try again if an error occurres |
| 159 | |
| 160 | ldr r1, = SSCOLPQS |
| 161 | 1: |
| 162 | ldr r0, [r1] |
| 163 | cmp r0, #0x4 |
| 164 | bne 1b @ wait until the operation is completed |
| 165 | str r0, [r1] @ clear the complete notification flag |
| 166 | |
| 167 | mov pc, lr |
| 168 | ENDPROC(setup_init_ram) |