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Tom Rini4549e782018-05-06 18:27:01 -04001/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
Patrick Delaunay5d0c74e2018-03-12 10:46:12 +01002/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
Patrick Delaunay5d0c74e2018-03-12 10:46:12 +01004 */
5
Patrick Delaunay42f01aa2019-02-04 11:26:17 +01006#ifndef __PMIC_STPMIC1_H_
7#define __PMIC_STPMIC1_H_
Patrick Delaunay5d0c74e2018-03-12 10:46:12 +01008
Patrick Delaunaydb4ff0d2019-02-04 11:26:18 +01009#define STPMIC1_MAIN_CR 0x10
10#define STPMIC1_BUCKS_MRST_CR 0x18
11#define STPMIC1_LDOS_MRST_CR 0x1a
12#define STPMIC1_BUCKX_MAIN_CR(buck) (0x20 + (buck))
13#define STPMIC1_REFDDR_MAIN_CR 0x24
14#define STPMIC1_LDOX_MAIN_CR(ldo) (0x25 + (ldo))
15#define STPMIC1_BST_SW_CR 0x40
16#define STPMIC1_NVM_SR 0xb8
17#define STPMIC1_NVM_CR 0xb9
Patrick Delaunay5d0c74e2018-03-12 10:46:12 +010018
Patrick Delaunaydb4ff0d2019-02-04 11:26:18 +010019/* Main PMIC Control Register (MAIN_CR) */
20#define STPMIC1_SWOFF BIT(0)
21#define STPMIC1_RREQ_EN BIT(1)
Patrick Delaunay5d0c74e2018-03-12 10:46:12 +010022
Patrick Delaunaydb4ff0d2019-02-04 11:26:18 +010023/* BUCKS_MRST_CR */
24#define STPMIC1_MRST_BUCK(buck) BIT(buck)
25#define STPMIC1_MRST_BUCK_ALL GENMASK(3, 0)
Patrick Delaunay5d0c74e2018-03-12 10:46:12 +010026
Patrick Delaunaydb4ff0d2019-02-04 11:26:18 +010027/* LDOS_MRST_CR */
28#define STPMIC1_MRST_LDO(ldo) BIT(ldo)
29#define STPMIC1_MRST_LDO_ALL GENMASK(6, 0)
Patrick Delaunay5d0c74e2018-03-12 10:46:12 +010030
Patrick Delaunaydb4ff0d2019-02-04 11:26:18 +010031/* BUCKx_MAIN_CR (x=1...4) */
32#define STPMIC1_BUCK_ENA BIT(0)
33#define STPMIC1_BUCK_PREG_MODE BIT(1)
34#define STPMIC1_BUCK_VOUT_MASK GENMASK(7, 2)
35#define STPMIC1_BUCK_VOUT_SHIFT 2
36#define STPMIC1_BUCK_VOUT(sel) (sel << STPMIC1_BUCK_VOUT_SHIFT)
Patrick Delaunay5d0c74e2018-03-12 10:46:12 +010037
Patrick Delaunaydb4ff0d2019-02-04 11:26:18 +010038#define STPMIC1_BUCK2_1200000V STPMIC1_BUCK_VOUT(24)
39#define STPMIC1_BUCK2_1350000V STPMIC1_BUCK_VOUT(30)
40
41#define STPMIC1_BUCK3_1800000V STPMIC1_BUCK_VOUT(39)
42
43/* REFDDR_MAIN_CR */
44#define STPMIC1_VREF_ENA BIT(0)
45
46/* LDOX_MAIN_CR */
47#define STPMIC1_LDO_ENA BIT(0)
48#define STPMIC1_LDO12356_VOUT_MASK GENMASK(6, 2)
49#define STPMIC1_LDO12356_VOUT_SHIFT 2
50#define STPMIC1_LDO_VOUT(sel) (sel << STPMIC1_LDO12356_VOUT_SHIFT)
51
Patrick Delaunay42f01aa2019-02-04 11:26:17 +010052#define STPMIC1_LDO3_MODE BIT(7)
53#define STPMIC1_LDO3_DDR_SEL 31
Patrick Delaunaydb4ff0d2019-02-04 11:26:18 +010054#define STPMIC1_LDO3_1800000 STPMIC1_LDO_VOUT(9)
55
Patrick Delaunay42f01aa2019-02-04 11:26:17 +010056#define STPMIC1_LDO4_UV 3300000
Patrick Delaunay5d0c74e2018-03-12 10:46:12 +010057
Patrick Delaunaydb4ff0d2019-02-04 11:26:18 +010058/* BST_SW_CR */
59#define STPMIC1_BST_ON BIT(0)
60#define STPMIC1_VBUSOTG_ON BIT(1)
61#define STPMIC1_SWOUT_ON BIT(2)
62#define STPMIC1_PWR_SW_ON (STPMIC1_VBUSOTG_ON | STPMIC1_SWOUT_ON)
Patrick Delaunay5d0c74e2018-03-12 10:46:12 +010063
Patrick Delaunaydb4ff0d2019-02-04 11:26:18 +010064/* NVM_SR */
65#define STPMIC1_NVM_BUSY BIT(0)
Patrick Delaunay5d0c74e2018-03-12 10:46:12 +010066
Patrick Delaunaydb4ff0d2019-02-04 11:26:18 +010067/* NVM_CR */
68#define STPMIC1_NVM_CMD_PROGRAM 1
69#define STPMIC1_NVM_CMD_READ 2
Patrick Delaunay42f01aa2019-02-04 11:26:17 +010070
Patrick Delaunaydb4ff0d2019-02-04 11:26:18 +010071/* Timeout */
Patrick Delaunay42f01aa2019-02-04 11:26:17 +010072#define STPMIC1_DEFAULT_START_UP_DELAY_MS 1
73#define STPMIC1_DEFAULT_STOP_DELAY_MS 5
74#define STPMIC1_USB_BOOST_START_UP_DELAY_MS 10
Patrick Delaunay5d0c74e2018-03-12 10:46:12 +010075
76enum {
Patrick Delaunay42f01aa2019-02-04 11:26:17 +010077 STPMIC1_BUCK1,
78 STPMIC1_BUCK2,
79 STPMIC1_BUCK3,
80 STPMIC1_BUCK4,
81 STPMIC1_MAX_BUCK,
Patrick Delaunay5d0c74e2018-03-12 10:46:12 +010082};
83
84enum {
Patrick Delaunaydb4ff0d2019-02-04 11:26:18 +010085 STPMIC1_PREG_MODE_HP,
86 STPMIC1_PREG_MODE_LP,
Patrick Delaunay5d0c74e2018-03-12 10:46:12 +010087};
88
89enum {
Patrick Delaunay42f01aa2019-02-04 11:26:17 +010090 STPMIC1_LDO1,
91 STPMIC1_LDO2,
92 STPMIC1_LDO3,
93 STPMIC1_LDO4,
94 STPMIC1_LDO5,
95 STPMIC1_LDO6,
96 STPMIC1_MAX_LDO,
Patrick Delaunay5d0c74e2018-03-12 10:46:12 +010097};
98
99enum {
Patrick Delaunay42f01aa2019-02-04 11:26:17 +0100100 STPMIC1_LDO_MODE_NORMAL,
101 STPMIC1_LDO_MODE_BYPASS,
102 STPMIC1_LDO_MODE_SINK_SOURCE,
Patrick Delaunay5d0c74e2018-03-12 10:46:12 +0100103};
104
105enum {
Patrick Delaunay42f01aa2019-02-04 11:26:17 +0100106 STPMIC1_PWR_SW1,
107 STPMIC1_PWR_SW2,
108 STPMIC1_MAX_PWR_SW,
Patrick Delaunay5d0c74e2018-03-12 10:46:12 +0100109};
Patrick Delaunay31e45a12019-02-04 11:26:22 +0100110
111int stpmic1_shadow_read_byte(u8 addr, u8 *buf);
112int stpmic1_shadow_write_byte(u8 addr, u8 *buf);
113int stpmic1_nvm_read_byte(u8 addr, u8 *buf);
114int stpmic1_nvm_write_byte(u8 addr, u8 *buf);
115int stpmic1_nvm_read_all(u8 *buf, int buf_len);
116int stpmic1_nvm_write_all(u8 *buf, int buf_len);
Patrick Delaunay5d0c74e2018-03-12 10:46:12 +0100117#endif