blob: 65b3734348b010aae6c3a86e83499de4772e875f [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Yen Lin96a78ac2012-03-06 19:00:23 +00002/*
3 * Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
4 * Copyright (c) 2010-2011 NVIDIA Corporation
5 * NVIDIA Corporation <www.nvidia.com>
Yen Lin96a78ac2012-03-06 19:00:23 +00006 */
7
8#include <common.h>
Simon Glassb0e6ef42014-12-10 08:55:57 -07009#include <dm.h>
10#include <errno.h>
Yen Lin96a78ac2012-03-06 19:00:23 +000011#include <i2c.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060012#include <log.h>
Yen Lin96a78ac2012-03-06 19:00:23 +000013#include <asm/io.h>
Bryan Wu3c27fa22016-08-05 16:10:35 -060014#include <clk.h>
15#include <reset.h>
Stephen Warrenfc607d92016-09-13 10:46:02 -060016#ifndef CONFIG_TEGRA186
Yen Lin96a78ac2012-03-06 19:00:23 +000017#include <asm/arch/clock.h>
18#include <asm/arch/funcmux.h>
Bryan Wu3c27fa22016-08-05 16:10:35 -060019#endif
20#include <asm/arch/gpio.h>
Tom Warren150c2492012-09-19 15:50:56 -070021#include <asm/arch-tegra/tegra_i2c.h>
Simon Glassc05ed002020-05-10 11:40:11 -060022#include <linux/delay.h>
Simon Glass61b29b82020-02-03 07:36:15 -070023#include <linux/err.h>
Yen Lin96a78ac2012-03-06 19:00:23 +000024
Simon Glassb0e6ef42014-12-10 08:55:57 -070025enum i2c_type {
26 TYPE_114,
27 TYPE_STD,
28 TYPE_DVC,
29};
30
Yen Lin96a78ac2012-03-06 19:00:23 +000031/* Information about i2c controller */
32struct i2c_bus {
33 int id;
Bryan Wu3c27fa22016-08-05 16:10:35 -060034 struct reset_ctl reset_ctl;
35 struct clk clk;
Yen Lin96a78ac2012-03-06 19:00:23 +000036 int speed;
37 int pinmux_config;
38 struct i2c_control *control;
39 struct i2c_ctlr *regs;
Simon Glassb0e6ef42014-12-10 08:55:57 -070040 enum i2c_type type;
Yen Lin96a78ac2012-03-06 19:00:23 +000041 int inited; /* bus is inited */
42};
43
Yen Lin96a78ac2012-03-06 19:00:23 +000044static void set_packet_mode(struct i2c_bus *i2c_bus)
45{
46 u32 config;
47
48 config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK;
49
Simon Glassb0e6ef42014-12-10 08:55:57 -070050 if (i2c_bus->type == TYPE_DVC) {
Yen Lin96a78ac2012-03-06 19:00:23 +000051 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
52
53 writel(config, &dvc->cnfg);
54 } else {
55 writel(config, &i2c_bus->regs->cnfg);
56 /*
57 * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe
58 * issues, i.e., some slaves may be wrongly detected.
59 */
60 setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK);
61 }
62}
63
64static void i2c_reset_controller(struct i2c_bus *i2c_bus)
65{
66 /* Reset I2C controller. */
Bryan Wu3c27fa22016-08-05 16:10:35 -060067 reset_assert(&i2c_bus->reset_ctl);
68 udelay(1);
69 reset_deassert(&i2c_bus->reset_ctl);
70 udelay(1);
Yen Lin96a78ac2012-03-06 19:00:23 +000071
72 /* re-program config register to packet mode */
73 set_packet_mode(i2c_bus);
74}
75
Bryan Wu3c27fa22016-08-05 16:10:35 -060076static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate)
77{
78 int ret;
79
80 ret = reset_assert(&i2c_bus->reset_ctl);
81 if (ret)
82 return ret;
83 ret = clk_enable(&i2c_bus->clk);
84 if (ret)
85 return ret;
86 ret = clk_set_rate(&i2c_bus->clk, rate);
87 if (IS_ERR_VALUE(ret))
88 return ret;
89 ret = reset_deassert(&i2c_bus->reset_ctl);
90 if (ret)
91 return ret;
92
93 return 0;
94}
Bryan Wu3c27fa22016-08-05 16:10:35 -060095
Yen Lin96a78ac2012-03-06 19:00:23 +000096static void i2c_init_controller(struct i2c_bus *i2c_bus)
97{
Simon Glassb0e6ef42014-12-10 08:55:57 -070098 if (!i2c_bus->speed)
99 return;
100 debug("%s: speed=%d\n", __func__, i2c_bus->speed);
Yen Lin96a78ac2012-03-06 19:00:23 +0000101 /*
102 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8
103 * here, in section 23.3.1, but in fact we seem to need a factor of
104 * 16 to get the right frequency.
105 */
Bryan Wu3c27fa22016-08-05 16:10:35 -0600106 i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8);
Tom Warrene32624e2013-02-08 07:25:30 +0000107
Simon Glassb0e6ef42014-12-10 08:55:57 -0700108 if (i2c_bus->type == TYPE_114) {
Tom Warrene32624e2013-02-08 07:25:30 +0000109 /*
110 * T114 I2C went to a single clock source for standard/fast and
111 * HS clock speeds. The new clock rate setting calculation is:
112 * SCL = CLK_SOURCE.I2C /
113 * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) *
114 * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1).
115 *
116 * NOTE: We do this here, after the initial clock/pll start,
117 * because if we read the clk_div reg before the controller
118 * is running, we hang, and we need it for the new calc.
119 */
120 int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16;
Bryan Wu3c27fa22016-08-05 16:10:35 -0600121 unsigned rate = CLK_MULT_STD_FAST_MODE *
122 (clk_div_stdfst_mode + 1) * i2c_bus->speed * 2;
Tom Warrene32624e2013-02-08 07:25:30 +0000123 debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__,
124 clk_div_stdfst_mode);
125
Bryan Wu3c27fa22016-08-05 16:10:35 -0600126 i2c_init_clock(i2c_bus, rate);
Tom Warrene32624e2013-02-08 07:25:30 +0000127 }
Yen Lin96a78ac2012-03-06 19:00:23 +0000128
129 /* Reset I2C controller. */
130 i2c_reset_controller(i2c_bus);
131
132 /* Configure I2C controller. */
Simon Glassb0e6ef42014-12-10 08:55:57 -0700133 if (i2c_bus->type == TYPE_DVC) { /* only for DVC I2C */
Yen Lin96a78ac2012-03-06 19:00:23 +0000134 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs;
135
136 setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK);
137 }
138
Bryan Wu3c27fa22016-08-05 16:10:35 -0600139#ifndef CONFIG_TEGRA186
Stephen Warrenfc607d92016-09-13 10:46:02 -0600140 funcmux_select(i2c_bus->clk.id, i2c_bus->pinmux_config);
Bryan Wu3c27fa22016-08-05 16:10:35 -0600141#endif
Yen Lin96a78ac2012-03-06 19:00:23 +0000142}
143
144static void send_packet_headers(
145 struct i2c_bus *i2c_bus,
146 struct i2c_trans_info *trans,
Stephen Warren68049a02014-06-25 10:57:27 -0600147 u32 packet_id,
148 bool end_with_repeated_start)
Yen Lin96a78ac2012-03-06 19:00:23 +0000149{
150 u32 data;
151
152 /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */
153 data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT;
154 data |= packet_id << PKT_HDR1_PKT_ID_SHIFT;
155 data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT;
156 writel(data, &i2c_bus->control->tx_fifo);
157 debug("pkt header 1 sent (0x%x)\n", data);
158
159 /* prepare header2 */
160 data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT;
161 writel(data, &i2c_bus->control->tx_fifo);
162 debug("pkt header 2 sent (0x%x)\n", data);
163
164 /* prepare IO specific header: configure the slave address */
165 data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT;
166
167 /* Enable Read if it is not a write transaction */
168 if (!(trans->flags & I2C_IS_WRITE))
169 data |= PKT_HDR3_READ_MODE_MASK;
Stephen Warren68049a02014-06-25 10:57:27 -0600170 if (end_with_repeated_start)
171 data |= PKT_HDR3_REPEAT_START_MASK;
Yen Lin96a78ac2012-03-06 19:00:23 +0000172
173 /* Write I2C specific header */
174 writel(data, &i2c_bus->control->tx_fifo);
175 debug("pkt header 3 sent (0x%x)\n", data);
176}
177
178static int wait_for_tx_fifo_empty(struct i2c_control *control)
179{
180 u32 count;
181 int timeout_us = I2C_TIMEOUT_USEC;
182
183 while (timeout_us >= 0) {
184 count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK)
185 >> TX_FIFO_EMPTY_CNT_SHIFT;
186 if (count == I2C_FIFO_DEPTH)
187 return 1;
188 udelay(10);
189 timeout_us -= 10;
190 }
191
192 return 0;
193}
194
195static int wait_for_rx_fifo_notempty(struct i2c_control *control)
196{
197 u32 count;
198 int timeout_us = I2C_TIMEOUT_USEC;
199
200 while (timeout_us >= 0) {
201 count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK)
202 >> TX_FIFO_FULL_CNT_SHIFT;
203 if (count)
204 return 1;
205 udelay(10);
206 timeout_us -= 10;
207 }
208
209 return 0;
210}
211
212static int wait_for_transfer_complete(struct i2c_control *control)
213{
214 int int_status;
215 int timeout_us = I2C_TIMEOUT_USEC;
216
217 while (timeout_us >= 0) {
218 int_status = readl(&control->int_status);
219 if (int_status & I2C_INT_NO_ACK_MASK)
220 return -int_status;
221 if (int_status & I2C_INT_ARBITRATION_LOST_MASK)
222 return -int_status;
223 if (int_status & I2C_INT_XFER_COMPLETE_MASK)
224 return 0;
225
226 udelay(10);
227 timeout_us -= 10;
228 }
229
230 return -1;
231}
232
233static int send_recv_packets(struct i2c_bus *i2c_bus,
234 struct i2c_trans_info *trans)
235{
236 struct i2c_control *control = i2c_bus->control;
237 u32 int_status;
238 u32 words;
239 u8 *dptr;
240 u32 local;
241 uchar last_bytes;
242 int error = 0;
243 int is_write = trans->flags & I2C_IS_WRITE;
244
245 /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */
246 int_status = readl(&control->int_status);
247 writel(int_status, &control->int_status);
248
Stephen Warren68049a02014-06-25 10:57:27 -0600249 send_packet_headers(i2c_bus, trans, 1,
250 trans->flags & I2C_USE_REPEATED_START);
Yen Lin96a78ac2012-03-06 19:00:23 +0000251
252 words = DIV_ROUND_UP(trans->num_bytes, 4);
253 last_bytes = trans->num_bytes & 3;
254 dptr = trans->buf;
255
256 while (words) {
257 u32 *wptr = (u32 *)dptr;
258
259 if (is_write) {
260 /* deal with word alignment */
Stephen Warren981b14f2014-06-25 10:57:28 -0600261 if ((words == 1) && last_bytes) {
262 local = 0;
263 memcpy(&local, dptr, last_bytes);
Thierry Reding8e67c5d2015-07-22 15:33:22 -0600264 } else if ((unsigned long)dptr & 3) {
Yen Lin96a78ac2012-03-06 19:00:23 +0000265 memcpy(&local, dptr, sizeof(u32));
Yen Lin96a78ac2012-03-06 19:00:23 +0000266 } else {
Stephen Warren981b14f2014-06-25 10:57:28 -0600267 local = *wptr;
Yen Lin96a78ac2012-03-06 19:00:23 +0000268 }
Stephen Warren981b14f2014-06-25 10:57:28 -0600269 writel(local, &control->tx_fifo);
270 debug("pkt data sent (0x%x)\n", local);
Yen Lin96a78ac2012-03-06 19:00:23 +0000271 if (!wait_for_tx_fifo_empty(control)) {
272 error = -1;
273 goto exit;
274 }
275 } else {
276 if (!wait_for_rx_fifo_notempty(control)) {
277 error = -1;
278 goto exit;
279 }
280 /*
281 * for the last word, we read into our local buffer,
282 * in case that caller did not provide enough buffer.
283 */
284 local = readl(&control->rx_fifo);
285 if ((words == 1) && last_bytes)
286 memcpy(dptr, (char *)&local, last_bytes);
Thierry Reding8e67c5d2015-07-22 15:33:22 -0600287 else if ((unsigned long)dptr & 3)
Yen Lin96a78ac2012-03-06 19:00:23 +0000288 memcpy(dptr, &local, sizeof(u32));
289 else
290 *wptr = local;
291 debug("pkt data received (0x%x)\n", local);
292 }
293 words--;
294 dptr += sizeof(u32);
295 }
296
297 if (wait_for_transfer_complete(control)) {
298 error = -1;
299 goto exit;
300 }
301 return 0;
302exit:
303 /* error, reset the controller. */
304 i2c_reset_controller(i2c_bus);
305
306 return error;
307}
308
Simon Glassb0e6ef42014-12-10 08:55:57 -0700309static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
Stephen Warren68049a02014-06-25 10:57:27 -0600310 u32 len, bool end_with_repeated_start)
Yen Lin96a78ac2012-03-06 19:00:23 +0000311{
312 int error;
313 struct i2c_trans_info trans_info;
314
315 trans_info.address = addr;
316 trans_info.buf = data;
317 trans_info.flags = I2C_IS_WRITE;
Stephen Warren68049a02014-06-25 10:57:27 -0600318 if (end_with_repeated_start)
319 trans_info.flags |= I2C_USE_REPEATED_START;
Yen Lin96a78ac2012-03-06 19:00:23 +0000320 trans_info.num_bytes = len;
321 trans_info.is_10bit_address = 0;
322
Simon Glassb0e6ef42014-12-10 08:55:57 -0700323 error = send_recv_packets(i2c_bus, &trans_info);
Yen Lin96a78ac2012-03-06 19:00:23 +0000324 if (error)
Tom Warren29f3e3f2012-09-04 17:00:24 -0700325 debug("tegra_i2c_write_data: Error (%d) !!!\n", error);
Yen Lin96a78ac2012-03-06 19:00:23 +0000326
327 return error;
328}
329
Simon Glassb0e6ef42014-12-10 08:55:57 -0700330static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data,
Simon Glassd84eb852012-10-30 07:28:52 +0000331 u32 len)
Yen Lin96a78ac2012-03-06 19:00:23 +0000332{
333 int error;
334 struct i2c_trans_info trans_info;
335
336 trans_info.address = addr | 1;
337 trans_info.buf = data;
338 trans_info.flags = 0;
339 trans_info.num_bytes = len;
340 trans_info.is_10bit_address = 0;
341
Simon Glassb0e6ef42014-12-10 08:55:57 -0700342 error = send_recv_packets(i2c_bus, &trans_info);
Yen Lin96a78ac2012-03-06 19:00:23 +0000343 if (error)
Tom Warren29f3e3f2012-09-04 17:00:24 -0700344 debug("tegra_i2c_read_data: Error (%d) !!!\n", error);
Yen Lin96a78ac2012-03-06 19:00:23 +0000345
346 return error;
347}
348
Simon Glassb0e6ef42014-12-10 08:55:57 -0700349static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
Yen Lin96a78ac2012-03-06 19:00:23 +0000350{
Simon Glassb0e6ef42014-12-10 08:55:57 -0700351 struct i2c_bus *i2c_bus = dev_get_priv(dev);
Simon Glassd84eb852012-10-30 07:28:52 +0000352
Simon Glassb0e6ef42014-12-10 08:55:57 -0700353 i2c_bus->speed = speed;
354 i2c_init_controller(i2c_bus);
Yen Lin96a78ac2012-03-06 19:00:23 +0000355
356 return 0;
357}
358
Simon Glassb0e6ef42014-12-10 08:55:57 -0700359static int tegra_i2c_probe(struct udevice *dev)
Yen Lin96a78ac2012-03-06 19:00:23 +0000360{
Simon Glassb0e6ef42014-12-10 08:55:57 -0700361 struct i2c_bus *i2c_bus = dev_get_priv(dev);
Bryan Wu3c27fa22016-08-05 16:10:35 -0600362 int ret;
Simon Glassb0e6ef42014-12-10 08:55:57 -0700363 bool is_dvc;
364
365 i2c_bus->id = dev->seq;
Simon Glass39de8432015-03-25 12:21:55 -0600366 i2c_bus->type = dev_get_driver_data(dev);
Simon Glassd8554d02017-07-25 08:30:06 -0600367 i2c_bus->regs = (struct i2c_ctlr *)dev_read_addr(dev);
368 if ((ulong)i2c_bus->regs == FDT_ADDR_T_NONE) {
369 debug("%s: Cannot get regs address\n", __func__);
370 return -EINVAL;
371 }
Yen Lin96a78ac2012-03-06 19:00:23 +0000372
Bryan Wu3c27fa22016-08-05 16:10:35 -0600373 ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl);
374 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900375 pr_err("reset_get_by_name() failed: %d\n", ret);
Bryan Wu3c27fa22016-08-05 16:10:35 -0600376 return ret;
377 }
Stephen Warrenb4ee0812016-08-18 11:08:43 -0600378 ret = clk_get_by_name(dev, "div-clk", &i2c_bus->clk);
Bryan Wu3c27fa22016-08-05 16:10:35 -0600379 if (ret) {
Masahiro Yamada9b643e32017-09-16 14:10:41 +0900380 pr_err("clk_get_by_name() failed: %d\n", ret);
Bryan Wu3c27fa22016-08-05 16:10:35 -0600381 return ret;
382 }
Stephen Warrenfc607d92016-09-13 10:46:02 -0600383
384#ifndef CONFIG_TEGRA186
385 /*
386 * We don't have a binding for pinmux yet. Leave it out for now. So
387 * far no one needs anything other than the default.
388 */
Yen Lin96a78ac2012-03-06 19:00:23 +0000389 i2c_bus->pinmux_config = FUNCMUX_DEFAULT;
Yen Lin96a78ac2012-03-06 19:00:23 +0000390
391 /*
392 * We can't specify the pinmux config in the fdt, so I2C2 will not
393 * work on Seaboard. It normally has no devices on it anyway.
394 * You could add in this little hack if you need to use it.
395 * The correct solution is a pinmux binding in the fdt.
396 *
Stephen Warrenfc607d92016-09-13 10:46:02 -0600397 * if (i2c_bus->clk.id == PERIPH_ID_I2C2)
Yen Lin96a78ac2012-03-06 19:00:23 +0000398 * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA;
399 */
Bryan Wu3c27fa22016-08-05 16:10:35 -0600400#endif
Yen Lin96a78ac2012-03-06 19:00:23 +0000401
Simon Glass39de8432015-03-25 12:21:55 -0600402 is_dvc = dev_get_driver_data(dev) == TYPE_DVC;
Simon Glassb0e6ef42014-12-10 08:55:57 -0700403 if (is_dvc) {
404 i2c_bus->control =
405 &((struct dvc_ctlr *)i2c_bus->regs)->control;
406 } else {
407 i2c_bus->control = &i2c_bus->regs->control;
Yen Lin96a78ac2012-03-06 19:00:23 +0000408 }
Simon Glassb0e6ef42014-12-10 08:55:57 -0700409 i2c_init_controller(i2c_bus);
Stephen Warrenfc607d92016-09-13 10:46:02 -0600410 debug("%s: controller bus %d at %p, speed %d: ",
411 is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs, i2c_bus->speed);
Yen Lin96a78ac2012-03-06 19:00:23 +0000412
413 return 0;
414}
415
Yen Lin96a78ac2012-03-06 19:00:23 +0000416/* i2c write version without the register address */
Simon Glassb0e6ef42014-12-10 08:55:57 -0700417static int i2c_write_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
Jeroen Hofstee19d7bf32014-10-08 22:57:46 +0200418 int len, bool end_with_repeated_start)
Yen Lin96a78ac2012-03-06 19:00:23 +0000419{
420 int rc;
421
422 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len);
423 debug("write_data: ");
424 /* use rc for counter */
425 for (rc = 0; rc < len; ++rc)
426 debug(" 0x%02x", buffer[rc]);
427 debug("\n");
428
429 /* Shift 7-bit address over for lower-level i2c functions */
Simon Glassb0e6ef42014-12-10 08:55:57 -0700430 rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len,
Stephen Warren68049a02014-06-25 10:57:27 -0600431 end_with_repeated_start);
Yen Lin96a78ac2012-03-06 19:00:23 +0000432 if (rc)
433 debug("i2c_write_data(): rc=%d\n", rc);
434
435 return rc;
436}
437
438/* i2c read version without the register address */
Simon Glassb0e6ef42014-12-10 08:55:57 -0700439static int i2c_read_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer,
440 int len)
Yen Lin96a78ac2012-03-06 19:00:23 +0000441{
442 int rc;
443
444 debug("inside i2c_read_data():\n");
445 /* Shift 7-bit address over for lower-level i2c functions */
Simon Glassb0e6ef42014-12-10 08:55:57 -0700446 rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len);
Yen Lin96a78ac2012-03-06 19:00:23 +0000447 if (rc) {
448 debug("i2c_read_data(): rc=%d\n", rc);
449 return rc;
450 }
451
452 debug("i2c_read_data: ");
453 /* reuse rc for counter*/
454 for (rc = 0; rc < len; ++rc)
455 debug(" 0x%02x", buffer[rc]);
456 debug("\n");
457
458 return 0;
459}
460
461/* Probe to see if a chip is present. */
Simon Glassb0e6ef42014-12-10 08:55:57 -0700462static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr,
463 uint chip_flags)
Yen Lin96a78ac2012-03-06 19:00:23 +0000464{
Simon Glassb0e6ef42014-12-10 08:55:57 -0700465 struct i2c_bus *i2c_bus = dev_get_priv(bus);
Yen Lin96a78ac2012-03-06 19:00:23 +0000466 int rc;
Simon Glassb0e6ef42014-12-10 08:55:57 -0700467 u8 reg;
Yen Lin96a78ac2012-03-06 19:00:23 +0000468
Simon Glassb0e6ef42014-12-10 08:55:57 -0700469 /* Shift 7-bit address over for lower-level i2c functions */
470 rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, &reg, sizeof(reg),
471 false);
472
473 return rc;
Yen Lin96a78ac2012-03-06 19:00:23 +0000474}
475
Simon Glassb0e6ef42014-12-10 08:55:57 -0700476static int tegra_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
477 int nmsgs)
Yen Lin96a78ac2012-03-06 19:00:23 +0000478{
Simon Glassb0e6ef42014-12-10 08:55:57 -0700479 struct i2c_bus *i2c_bus = dev_get_priv(bus);
480 int ret;
Yen Lin96a78ac2012-03-06 19:00:23 +0000481
Simon Glassb0e6ef42014-12-10 08:55:57 -0700482 debug("i2c_xfer: %d messages\n", nmsgs);
483 for (; nmsgs > 0; nmsgs--, msg++) {
484 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
Yen Lin96a78ac2012-03-06 19:00:23 +0000485
Simon Glassb0e6ef42014-12-10 08:55:57 -0700486 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
487 if (msg->flags & I2C_M_RD) {
488 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf,
489 msg->len);
490 } else {
491 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf,
492 msg->len, next_is_read);
Yen Lin96a78ac2012-03-06 19:00:23 +0000493 }
Simon Glassb0e6ef42014-12-10 08:55:57 -0700494 if (ret) {
495 debug("i2c_write: error sending\n");
496 return -EREMOTEIO;
Yen Lin96a78ac2012-03-06 19:00:23 +0000497 }
498 }
499
500 return 0;
501}
502
Simon Glassb0e6ef42014-12-10 08:55:57 -0700503int tegra_i2c_get_dvc_bus(struct udevice **busp)
Yen Lin96a78ac2012-03-06 19:00:23 +0000504{
Simon Glassfdec36f2020-02-06 09:54:52 -0700505 return uclass_first_device_drvdata(UCLASS_I2C, TYPE_DVC, busp);
Simon Glassb0e6ef42014-12-10 08:55:57 -0700506}
507
508static const struct dm_i2c_ops tegra_i2c_ops = {
509 .xfer = tegra_i2c_xfer,
510 .probe_chip = tegra_i2c_probe_chip,
511 .set_bus_speed = tegra_i2c_set_bus_speed,
512};
513
Simon Glassb0e6ef42014-12-10 08:55:57 -0700514static const struct udevice_id tegra_i2c_ids[] = {
515 { .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 },
516 { .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD },
517 { .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC },
518 { }
519};
Simon Glasse31c1e52012-04-02 13:19:01 +0000520
Simon Glassb0e6ef42014-12-10 08:55:57 -0700521U_BOOT_DRIVER(i2c_tegra) = {
522 .name = "i2c_tegra",
523 .id = UCLASS_I2C,
524 .of_match = tegra_i2c_ids,
Simon Glassb0e6ef42014-12-10 08:55:57 -0700525 .probe = tegra_i2c_probe,
Simon Glassb0e6ef42014-12-10 08:55:57 -0700526 .priv_auto_alloc_size = sizeof(struct i2c_bus),
527 .ops = &tegra_i2c_ops,
528};