blob: 20fee2d39cc48610e2d1543da5d2dd852d0a9cbd [file] [log] [blame]
Wolfgang Denkba94a1b2006-05-30 15:56:48 +02001/*-----------------------------------------------------------------------------+
2 |
3 | This source code has been made available to you by IBM on an AS-IS
4 | basis. Anyone receiving this source is licensed under IBM
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6 | copying it, modifying it, compiling it, and redistributing it either
7 | with or without modifications. No license under IBM patents or
8 | patent applications is to be implied by the copyright license.
9 |
10 | Any user of this software should understand that IBM cannot provide
11 | technical support for this software and will not be responsible for
12 | any consequences resulting from the use of this software.
13 |
14 | Any person who transfers this source code or any derivative work
15 | must include the IBM copyright notice, this paragraph, and the
16 | preceding two paragraphs in the transferred software.
17 |
18 | COPYRIGHT I B M CORPORATION 1995
19 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20 +-----------------------------------------------------------------------------*/
21/*-----------------------------------------------------------------------------+
22 |
23 | File Name: miiphy.c
24 |
25 | Function: This module has utilities for accessing the MII PHY through
26 | the EMAC3 macro.
27 |
28 | Author: Mark Wisner
29 |
30 | Change Activity-
31 |
32 | Date Description of Change BY
33 | --------- --------------------- ---
34 | 05-May-99 Created MKW
Wolfgang Denk8ed44d92008-10-19 02:35:50 +020035 | 01-Jul-99 Changed clock setting of sta_reg from 66MHz to 50MHz to
Wolfgang Denkba94a1b2006-05-30 15:56:48 +020036 | better match OPB speed. Also modified delay times. JWB
37 | 29-Jul-99 Added Full duplex support MKW
38 | 24-Aug-99 Removed printf from dp83843_duplex() JWB
39 | 19-Jul-00 Ported to esd cpci405 sr
40 | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS
41 | <travis.sawyer@sandburst.com>
42 |
43 +-----------------------------------------------------------------------------*/
44
45#include <common.h>
46#include <miiphy.h>
47#include "IxOsal.h"
48#include "IxEthAcc.h"
49#include "IxEthAcc_p.h"
50#include "IxEthAccMac_p.h"
51#include "IxEthAccMii_p.h"
52
53/***********************************************************/
54/* Dump out to the screen PHY regs */
55/***********************************************************/
56
57void miiphy_dump (char *devname, unsigned char addr)
58{
59 unsigned long i;
60 unsigned short data;
61
62
63 for (i = 0; i < 0x1A; i++) {
64 if (miiphy_read (devname, addr, i, &data)) {
65 printf ("read error for reg %lx\n", i);
66 return;
67 }
68 printf ("Phy reg %lx ==> %4x\n", i, data);
69
70 /* jump to the next set of regs */
71 if (i == 0x07)
72 i = 0x0f;
73
74 } /* end for loop */
75} /* end dump */
76
77
78/***********************************************************/
79/* (Re)start autonegotiation */
80/***********************************************************/
81int phy_setup_aneg (char *devname, unsigned char addr)
82{
83 unsigned short ctl, adv;
84
85 /* Setup standard advertise */
86 miiphy_read (devname, addr, PHY_ANAR, &adv);
87 adv |= (PHY_ANLPAR_ACK | PHY_ANLPAR_RF | PHY_ANLPAR_T4 |
88 PHY_ANLPAR_TXFD | PHY_ANLPAR_TX | PHY_ANLPAR_10FD |
89 PHY_ANLPAR_10);
90 miiphy_write (devname, addr, PHY_ANAR, adv);
91
92 /* Start/Restart aneg */
93 miiphy_read (devname, addr, PHY_BMCR, &ctl);
94 ctl |= (PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
95 miiphy_write (devname, addr, PHY_BMCR, ctl);
96
97 return 0;
98}
99
100
101int npe_miiphy_read (char *devname, unsigned char addr,
102 unsigned char reg, unsigned short *value)
103{
104 u16 val;
105
106 ixEthAccMiiReadRtn(addr, reg, &val);
107 *value = val;
108
109 return 0;
110} /* phy_read */
111
112
113int npe_miiphy_write (char *devname, unsigned char addr,
114 unsigned char reg, unsigned short value)
115{
116 ixEthAccMiiWriteRtn(addr, reg, value);
117 return 0;
118} /* phy_write */