Blame - arch/arm/cpu/u-boot.lds - platform/external/u-boot

blob: d7adf90dafd9484125e5be2e36367bcda509cb05 [file] [log] [blame]

Simon Glass	dde3b70	2012-02-23 03:28:41 +0000	[diff] [blame]	1	/*
				2	* Copyright (c) 2004-2008 Texas Instruments
				3	*
				4	* (C) Copyright 2002
				5	* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
				6	*
				7	* See file CREDITS for list of people who contributed to this
				8	* project.
				9	*
				10	* This program is free software; you can redistribute it and/or
				11	* modify it under the terms of the GNU General Public License as
				12	* published by the Free Software Foundation; either version 2 of
				13	* the License, or (at your option) any later version.
				14	*
				15	* This program is distributed in the hope that it will be useful,
				16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
				17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
				18	* GNU General Public License for more details.
				19	*
				20	* You should have received a copy of the GNU General Public License
				21	* along with this program; if not, write to the Free Software
				22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
				23	* MA 02111-1307 USA
				24	*/
				25
				26	OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
				27	OUTPUT_ARCH(arm)
				28	ENTRY(_start)
				29	SECTIONS
				30	{
				31	. = 0x00000000;
				32
				33	. = ALIGN(4);
				34	.text :
				35	{
Albert ARIBAUD	d026dec	2013-06-11 14:17:33 +0200	[diff] [blame^]	36	*(.__image_copy_start)
Stephen Warren	b68d671	2012-10-22 06:19:32 +0000	[diff] [blame]	37	CPUDIR/start.o (.text*)
				38	(.text)
Simon Glass	dde3b70	2012-02-23 03:28:41 +0000	[diff] [blame]	39	}
				40
				41	. = ALIGN(4);
				42	.rodata : { (SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata))) }
				43
				44	. = ALIGN(4);
				45	.data : {
Stephen Warren	b68d671	2012-10-22 06:19:32 +0000	[diff] [blame]	46	(.data)
Simon Glass	dde3b70	2012-02-23 03:28:41 +0000	[diff] [blame]	47	}
				48
				49	. = ALIGN(4);
				50
				51	. = .;
Simon Glass	dde3b70	2012-02-23 03:28:41 +0000	[diff] [blame]	52
				53	. = ALIGN(4);
Marek Vasut	5567514	2012-10-12 10:27:03 +0000	[diff] [blame]	54	.u_boot_list : {
Albert ARIBAUD	ef123c5	2013-02-25 00:59:00 +0000	[diff] [blame]	55	KEEP((SORT(.u_boot_list)));
Marek Vasut	5567514	2012-10-12 10:27:03 +0000	[diff] [blame]	56	}
				57
				58	. = ALIGN(4);
Simon Glass	dde3b70	2012-02-23 03:28:41 +0000	[diff] [blame]	59
Albert ARIBAUD	d026dec	2013-06-11 14:17:33 +0200	[diff] [blame^]	60	.image_copy_end :
				61	{
				62	*(.__image_copy_end)
				63	}
Simon Glass	dde3b70	2012-02-23 03:28:41 +0000	[diff] [blame]	64
				65	.rel.dyn : {
				66	__rel_dyn_start = .;
				67	(.rel)
				68	__rel_dyn_end = .;
				69	}
				70
Simon Glass	dde3b70	2012-02-23 03:28:41 +0000	[diff] [blame]	71	_end = .;
				72
				73	/*
				74	* Deprecated: this MMU section is used by pxa at present but
				75	* should not be used by new boards/CPUs.
				76	*/
				77	. = ALIGN(4096);
				78	.mmutable : {
				79	*(.mmutable)
				80	}
				81
Albert ARIBAUD	f84a7b8	2013-04-11 05:43:21 +0000	[diff] [blame]	82	/*
				83	* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
				84	* __bss_base and __bss_limit are for linker only (overlay ordering)
				85	*/
				86
Albert ARIBAUD	3ebd1cb	2013-02-25 00:58:59 +0000	[diff] [blame]	87	.bss_start __rel_dyn_start (OVERLAY) : {
				88	KEEP(*(.__bss_start));
Albert ARIBAUD	f84a7b8	2013-04-11 05:43:21 +0000	[diff] [blame]	89	__bss_base = .;
Albert ARIBAUD	3ebd1cb	2013-02-25 00:58:59 +0000	[diff] [blame]	90	}
				91
Albert ARIBAUD	f84a7b8	2013-04-11 05:43:21 +0000	[diff] [blame]	92	.bss __bss_base (OVERLAY) : {
Stephen Warren	b68d671	2012-10-22 06:19:32 +0000	[diff] [blame]	93	(.bss)
Simon Glass	dde3b70	2012-02-23 03:28:41 +0000	[diff] [blame]	94	. = ALIGN(4);
Albert ARIBAUD	f84a7b8	2013-04-11 05:43:21 +0000	[diff] [blame]	95	__bss_limit = .;
Albert ARIBAUD	3ebd1cb	2013-02-25 00:58:59 +0000	[diff] [blame]	96	}
Tom Rini	0ce033d	2013-03-18 12:31:00 -0400	[diff] [blame]	97
Albert ARIBAUD	f84a7b8	2013-04-11 05:43:21 +0000	[diff] [blame]	98	.bss_end __bss_limit (OVERLAY) : {
				99	KEEP(*(.__bss_end));
Simon Glass	dde3b70	2012-02-23 03:28:41 +0000	[diff] [blame]	100	}
				101
Albert ARIBAUD	09d8118	2013-06-11 14:17:31 +0200	[diff] [blame]	102	/DISCARD/ : { *(.dynsym) }
Simon Glass	dde3b70	2012-02-23 03:28:41 +0000	[diff] [blame]	103	/DISCARD/ : { (.dynstr) }
				104	/DISCARD/ : { (.dynamic) }
				105	/DISCARD/ : { (.plt) }
				106	/DISCARD/ : { (.interp) }
				107	/DISCARD/ : { (.gnu) }
				108	}