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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / d026dec8751378473b4f12eb87717c8059472b3e / . / board / actux2 / u-boot.lds
blob: aff773ce9c4b89baef696b51541a742bdb97080b [file] [log] [blame]
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100[diff] [blame]1/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
25OUTPUT_ARCH (arm)
26ENTRY (_start)
27SECTIONS
28{
29 . = 0x00000000;
30
31 . = ALIGN (4);
32 .text : {
Albert ARIBAUDd026dec2013-06-11 14:17:33 +0200[diff] [blame^]33 *(.__image_copy_start)
Michael Schwingenaf050482011-05-23 00:00:05 +0200[diff] [blame]34 arch/arm/cpu/ixp/start.o(.text*)
35 net/libnet.o(.text*)
36 board/actux2/libactux2.o(.text*)
37 arch/arm/cpu/ixp/libixp.o(.text*)
Tom Rini1fb187b2012-10-17 10:18:29 +0000[diff] [blame]38 drivers/input/libinput.o(.text*)
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100[diff] [blame]39
40 . = env_offset;
Michael Schwingenaf050482011-05-23 00:00:05 +0200[diff] [blame]41 common/env_embedded.o(.ppcenv)
42 *(.text*)
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100[diff] [blame]43 }
44
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +0000[diff] [blame]45 . = ALIGN(4);
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100[diff] [blame]46 .rodata : {
Trent Piephof62fb992009-02-18 15:22:05 -0800[diff] [blame]47 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100[diff] [blame]48 }
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +0000[diff] [blame]49 . = ALIGN(4);
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100[diff] [blame]50 .data : {
Michael Schwingenaf050482011-05-23 00:00:05 +0200[diff] [blame]51 *(.data*)
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100[diff] [blame]52 }
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +0000[diff] [blame]53 . = ALIGN(4);
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100[diff] [blame]54 .got : {
55 *(.got)
56 }
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100[diff] [blame]57 . =.;
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100[diff] [blame]58
Marek Vasut55675142012-10-12 10:27:03 +0000[diff] [blame]59 . = ALIGN(4);
60 .u_boot_list : {
Albert ARIBAUDef123c52013-02-25 00:59:00 +0000[diff] [blame]61 KEEP(*(SORT(.u_boot_list*)));
Marek Vasut55675142012-10-12 10:27:03 +0000[diff] [blame]62 }
63
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100[diff] [blame]64 . = ALIGN (4);
Benoît Thébaudeau7086e912013-04-11 09:35:46 +0000[diff] [blame]65
Albert ARIBAUDd026dec2013-06-11 14:17:33 +0200[diff] [blame^]66 .image_copy_end :
67 {
68 *(.__image_copy_end)
69 }
Benoît Thébaudeau7086e912013-04-11 09:35:46 +0000[diff] [blame]70
Michael Schwingenaf050482011-05-23 00:00:05 +0200[diff] [blame]71 .rel.dyn : {
72 __rel_dyn_start = .;
73 *(.rel*)
74 __rel_dyn_end = .;
75 }
76
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +0000[diff] [blame]77 _end = .;
78
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000[diff] [blame]79/*
80 * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
81 * __bss_base and __bss_limit are for linker only (overlay ordering)
82 */
83
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +0000[diff] [blame]84 .bss_start __rel_dyn_start (OVERLAY) : {
85 KEEP(*(.__bss_start));
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000[diff] [blame]86 __bss_base = .;
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +0000[diff] [blame]87 }
88
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000[diff] [blame]89 .bss __bss_base (OVERLAY) : {
Michael Schwingenaf050482011-05-23 00:00:05 +0200[diff] [blame]90 *(.bss*)
91 . = ALIGN(4);
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000[diff] [blame]92 __bss_limit = .;
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100[diff] [blame]93 }
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +0000[diff] [blame]94 .bss_end __bss_limit (OVERLAY) : {
95 KEEP(*(.__bss_end));
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +0000[diff] [blame]96 }
97
Albert ARIBAUD09d81182013-06-11 14:17:31 +0200[diff] [blame]98 /DISCARD/ : { *(.dynsym) }
Michael Schwingenaf050482011-05-23 00:00:05 +0200[diff] [blame]99 /DISCARD/ : { *(.dynstr*) }
100 /DISCARD/ : { *(.dynamic*) }
101 /DISCARD/ : { *(.plt*) }
102 /DISCARD/ : { *(.interp*) }
103 /DISCARD/ : { *(.gnu*) }
Michael Schwingenaebf00f2008-01-16 19:51:14 +0100[diff] [blame]104}