Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
maxims@google.com | 14e4b14 | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2016 Google Inc. |
maxims@google.com | 14e4b14 | 2017-01-18 13:44:56 -0800 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | /* Core Clocks */ |
| 7 | #define PLL_HPLL 1 |
| 8 | #define PLL_DPLL 2 |
| 9 | #define PLL_D2PLL 3 |
| 10 | #define PLL_MPLL 4 |
| 11 | #define ARMCLK 5 |
| 12 | |
| 13 | |
| 14 | /* Bus Clocks, derived from core clocks */ |
| 15 | #define BCLK_PCLK 101 |
| 16 | #define BCLK_LHCLK 102 |
| 17 | #define BCLK_MACCLK 103 |
| 18 | #define BCLK_SDCLK 104 |
| 19 | #define BCLK_ARMCLK 105 |
| 20 | |
| 21 | #define MCLK_DDR 201 |
| 22 | |
| 23 | /* Special clocks */ |
| 24 | #define PCLK_UART1 501 |
| 25 | #define PCLK_UART2 502 |
| 26 | #define PCLK_UART3 503 |
| 27 | #define PCLK_UART4 504 |
| 28 | #define PCLK_UART5 505 |
maxims@google.com | 3b95902 | 2017-04-17 12:00:32 -0700 | [diff] [blame] | 29 | #define PCLK_MAC1 506 |
| 30 | #define PCLK_MAC2 507 |