| Sergei Poselenov | b448962 | 2007-07-05 08:17:37 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2007 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * Author: Igor Lisitsin <igor@emcraft.com> |
| 6 | * |
| 7 | * See file CREDITS for list of people who contributed to this |
| 8 | * project. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA |
| 24 | */ |
| 25 | |
| 26 | #include <common.h> |
| 27 | |
| 28 | /* Cache test |
| 29 | * |
| 30 | * This test verifies the CPU data and instruction cache using |
| 31 | * several test scenarios. |
| 32 | */ |
| 33 | |
| 34 | #ifdef CONFIG_POST |
| 35 | |
| 36 | #include <post.h> |
| 37 | |
| 38 | #if CONFIG_POST & CFG_POST_CACHE |
| 39 | |
| 40 | #include <asm/mmu.h> |
| 41 | #include <watchdog.h> |
| 42 | |
| 43 | #define CACHE_POST_SIZE 1024 |
| 44 | |
| 45 | void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); |
| 46 | |
| 47 | int cache_post_test1 (int tlb, void *p, int size); |
| 48 | int cache_post_test2 (int tlb, void *p, int size); |
| 49 | int cache_post_test3 (int tlb, void *p, int size); |
| 50 | int cache_post_test4 (int tlb, void *p, int size); |
| 51 | int cache_post_test5 (int tlb, void *p, int size); |
| 52 | int cache_post_test6 (int tlb, void *p, int size); |
| 53 | |
| 54 | static int tlb = -1; /* index to the victim TLB entry */ |
| 55 | |
| 56 | static unsigned char testarea[CACHE_POST_SIZE] |
| 57 | __attribute__((__aligned__(CACHE_POST_SIZE))); |
| 58 | |
| 59 | int cache_post_test (int flags) |
| 60 | { |
| 61 | void* virt = (void*)CFG_POST_CACHE_ADDR; |
| 62 | int ints, i, res = 0; |
| 63 | u32 word0; |
| 64 | |
| 65 | if (tlb < 0) { |
| 66 | /* |
| 67 | * Allocate a new TLB entry, since we are going to modify |
| 68 | * the write-through and caching inhibited storage attributes. |
| 69 | */ |
| 70 | program_tlb((u32)testarea, (u32)virt, |
| 71 | CACHE_POST_SIZE, TLB_WORD2_I_ENABLE); |
| 72 | |
| 73 | /* Find the TLB entry */ |
| 74 | for (i = 0;; i++) { |
| 75 | if (i >= PPC4XX_TLB_SIZE) { |
| 76 | printf ("Failed to program tlb entry\n"); |
| 77 | return -1; |
| 78 | } |
| 79 | word0 = mftlb1(i); |
| 80 | if (TLB_WORD0_EPN_DECODE(word0) == (u32)virt) { |
| 81 | tlb = i; |
| 82 | break; |
| 83 | } |
| 84 | } |
| 85 | } |
| 86 | ints = disable_interrupts (); |
| 87 | |
| 88 | WATCHDOG_RESET (); |
| 89 | if (res == 0) |
| 90 | res = cache_post_test1 (tlb, virt, CACHE_POST_SIZE); |
| 91 | WATCHDOG_RESET (); |
| 92 | if (res == 0) |
| 93 | res = cache_post_test2 (tlb, virt, CACHE_POST_SIZE); |
| 94 | WATCHDOG_RESET (); |
| 95 | if (res == 0) |
| 96 | res = cache_post_test3 (tlb, virt, CACHE_POST_SIZE); |
| 97 | WATCHDOG_RESET (); |
| 98 | if (res == 0) |
| 99 | res = cache_post_test4 (tlb, virt, CACHE_POST_SIZE); |
| 100 | WATCHDOG_RESET (); |
| 101 | if (res == 0) |
| 102 | res = cache_post_test5 (tlb, virt, CACHE_POST_SIZE); |
| 103 | WATCHDOG_RESET (); |
| 104 | if (res == 0) |
| 105 | res = cache_post_test6 (tlb, virt, CACHE_POST_SIZE); |
| 106 | |
| 107 | if (ints) |
| 108 | enable_interrupts (); |
| 109 | |
| 110 | return res; |
| 111 | } |
| 112 | |
| 113 | #endif /* CONFIG_POST & CFG_POST_CACHE */ |
| 114 | #endif /* CONFIG_POST */ |