blob: 4716e4f0e034ee11b071d8a2458dc5458b17bcc1 [file] [log] [blame]
Michael Schwingenea99e8f2008-01-16 19:50:37 +01001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Michael Schwingenea99e8f2008-01-16 19:50:37 +01006 */
7
8OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm")
9OUTPUT_ARCH (arm)
10ENTRY (_start)
11SECTIONS
12{
13 . = 0x00000000;
14
15 . = ALIGN (4);
16 .text : {
Albert ARIBAUDd026dec2013-06-11 14:17:33 +020017 *(.__image_copy_start)
Michael Schwingen517c5df2011-05-23 00:00:04 +020018 arch/arm/cpu/ixp/start.o(.text*)
Masahiro Yamadae2906a52013-11-11 14:36:00 +090019 net/built-in.o(.text*)
20 board/actux1/built-in.o(.text*)
21 arch/arm/cpu/ixp/built-in.o(.text*)
22 drivers/input/built-in.o(.text*)
Michael Schwingen517c5df2011-05-23 00:00:04 +020023
Michael Schwingenea99e8f2008-01-16 19:50:37 +010024 . = env_offset;
Jean-Christophe PLAGNIOL-VILLARD0cf4fd32008-09-10 22:48:01 +020025 common/env_embedded.o(.ppcenv)
Michael Schwingen517c5df2011-05-23 00:00:04 +020026 *(.text*)
Michael Schwingenea99e8f2008-01-16 19:50:37 +010027 }
28
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +000029 . = ALIGN(4);
Michael Schwingenea99e8f2008-01-16 19:50:37 +010030 .rodata : {
Trent Piephof62fb992009-02-18 15:22:05 -080031 *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
Michael Schwingenea99e8f2008-01-16 19:50:37 +010032 }
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +000033 . = ALIGN(4);
Michael Schwingenea99e8f2008-01-16 19:50:37 +010034 .data : {
Michael Schwingen517c5df2011-05-23 00:00:04 +020035 *(.data*)
Michael Schwingenea99e8f2008-01-16 19:50:37 +010036 }
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +000037 . = ALIGN(4);
Michael Schwingenea99e8f2008-01-16 19:50:37 +010038 .got : {
39 *(.got)
40 }
41 . =.;
Michael Schwingenea99e8f2008-01-16 19:50:37 +010042
Marek Vasut55675142012-10-12 10:27:03 +000043 . = ALIGN(4);
44 .u_boot_list : {
Albert ARIBAUDef123c52013-02-25 00:59:00 +000045 KEEP(*(SORT(.u_boot_list*)));
Marek Vasut55675142012-10-12 10:27:03 +000046 }
47
Michael Schwingenea99e8f2008-01-16 19:50:37 +010048 . = ALIGN (4);
Benoît Thébaudeau7086e912013-04-11 09:35:46 +000049
Albert ARIBAUDd026dec2013-06-11 14:17:33 +020050 .image_copy_end :
51 {
52 *(.__image_copy_end)
53 }
Benoît Thébaudeau7086e912013-04-11 09:35:46 +000054
Albert ARIBAUD47bd65e2013-06-11 14:17:34 +020055 .rel_dyn_start :
56 {
57 *(.__rel_dyn_start)
58 }
59
Michael Schwingen517c5df2011-05-23 00:00:04 +020060 .rel.dyn : {
Michael Schwingen517c5df2011-05-23 00:00:04 +020061 *(.rel*)
Albert ARIBAUD47bd65e2013-06-11 14:17:34 +020062 }
63
64 .rel_dyn_end :
65 {
66 *(.__rel_dyn_end)
Michael Schwingen517c5df2011-05-23 00:00:04 +020067 }
68
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +000069 _end = .;
70
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +000071/*
72 * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
73 * __bss_base and __bss_limit are for linker only (overlay ordering)
74 */
75
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +000076 .bss_start __rel_dyn_start (OVERLAY) : {
77 KEEP(*(.__bss_start));
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +000078 __bss_base = .;
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +000079 }
80
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +000081 .bss __bss_base (OVERLAY) : {
Michael Schwingen517c5df2011-05-23 00:00:04 +020082 *(.bss*)
83 . = ALIGN(4);
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +000084 __bss_limit = .;
Michael Schwingenea99e8f2008-01-16 19:50:37 +010085 }
Albert ARIBAUDf84a7b82013-04-11 05:43:21 +000086 .bss_end __bss_limit (OVERLAY) : {
87 KEEP(*(.__bss_end));
Albert ARIBAUD3ebd1cb2013-02-25 00:58:59 +000088 }
89
Albert ARIBAUD47ed5dd2013-11-07 14:21:46 +010090 .dynsym _end : { *(.dynsym) }
91 .dynbss : { *(.dynbss) }
92 .dynstr : { *(.dynstr*) }
93 .dynamic : { *(.dynamic*) }
94 .hash : { *(.hash*) }
95 .plt : { *(.plt*) }
96 .interp : { *(.interp*) }
97 .gnu : { *(.gnu*) }
98 .ARM.exidx : { *(.ARM.exidx*) }
Michael Schwingenea99e8f2008-01-16 19:50:37 +010099}