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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glass1f8f7732015-08-30 16:55:27 -06002/*
3 * (C) Copyright 2015 Google, Inc
4 *
5 * (C) Copyright 2008-2014 Rockchip Electronics
6 * Peter, Software Engineering, <superpeter.cai@gmail.com>.
Simon Glass1f8f7732015-08-30 16:55:27 -06007 */
8
9#include <common.h>
10#include <dm.h>
Simon Glass48647822016-01-21 19:44:09 -070011#include <syscon.h>
Masahiro Yamada1221ce42016-09-21 11:28:55 +090012#include <linux/errno.h>
Simon Glass1f8f7732015-08-30 16:55:27 -060013#include <asm/gpio.h>
14#include <asm/io.h>
Kever Yang15f09a12019-03-28 11:01:23 +080015#include <asm/arch-rockchip/clock.h>
16#include <asm/arch-rockchip/gpio.h>
Simon Glass48647822016-01-21 19:44:09 -070017#include <dm/pinctrl.h>
Simon Glass48647822016-01-21 19:44:09 -070018#include <dt-bindings/clock/rk3288-cru.h>
Simon Glass1f8f7732015-08-30 16:55:27 -060019
20enum {
21 ROCKCHIP_GPIOS_PER_BANK = 32,
22};
23
24#define OFFSET_TO_BIT(bit) (1UL << (bit))
25
26struct rockchip_gpio_priv {
27 struct rockchip_gpio_regs *regs;
Simon Glass48647822016-01-21 19:44:09 -070028 struct udevice *pinctrl;
29 int bank;
Simon Glass1f8f7732015-08-30 16:55:27 -060030 char name[2];
31};
32
33static int rockchip_gpio_direction_input(struct udevice *dev, unsigned offset)
34{
35 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
36 struct rockchip_gpio_regs *regs = priv->regs;
37
38 clrbits_le32(&regs->swport_ddr, OFFSET_TO_BIT(offset));
39
40 return 0;
41}
42
43static int rockchip_gpio_direction_output(struct udevice *dev, unsigned offset,
44 int value)
45{
46 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
47 struct rockchip_gpio_regs *regs = priv->regs;
48 int mask = OFFSET_TO_BIT(offset);
49
50 clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0);
51 setbits_le32(&regs->swport_ddr, mask);
52
53 return 0;
54}
55
56static int rockchip_gpio_get_value(struct udevice *dev, unsigned offset)
57{
58 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
59 struct rockchip_gpio_regs *regs = priv->regs;
60
Simon Glass7d0c2c32016-01-21 19:44:08 -070061 return readl(&regs->ext_port) & OFFSET_TO_BIT(offset) ? 1 : 0;
Simon Glass1f8f7732015-08-30 16:55:27 -060062}
63
64static int rockchip_gpio_set_value(struct udevice *dev, unsigned offset,
65 int value)
66{
67 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
68 struct rockchip_gpio_regs *regs = priv->regs;
69 int mask = OFFSET_TO_BIT(offset);
70
71 clrsetbits_le32(&regs->swport_dr, mask, value ? mask : 0);
72
73 return 0;
74}
75
76static int rockchip_gpio_get_function(struct udevice *dev, unsigned offset)
77{
Simon Glass48647822016-01-21 19:44:09 -070078#ifdef CONFIG_SPL_BUILD
79 return -ENODATA;
80#else
81 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
82 struct rockchip_gpio_regs *regs = priv->regs;
83 bool is_output;
84 int ret;
85
86 ret = pinctrl_get_gpio_mux(priv->pinctrl, priv->bank, offset);
87 if (ret)
88 return ret;
Simon Glass48647822016-01-21 19:44:09 -070089 is_output = readl(&regs->swport_ddr) & OFFSET_TO_BIT(offset);
90
91 return is_output ? GPIOF_OUTPUT : GPIOF_INPUT;
92#endif
Simon Glass1f8f7732015-08-30 16:55:27 -060093}
94
Simon Glassaa48c942019-01-21 14:53:34 -070095/* Simple SPL interface to GPIOs */
96#ifdef CONFIG_SPL_BUILD
97
98enum {
99 PULL_NONE_1V8 = 0,
100 PULL_DOWN_1V8 = 1,
101 PULL_UP_1V8 = 3,
102};
103
104int spl_gpio_set_pull(void *vregs, uint gpio, int pull)
105{
106 u32 *regs = vregs;
107 uint val;
108
109 regs += gpio >> GPIO_BANK_SHIFT;
110 gpio &= GPIO_OFFSET_MASK;
111 switch (pull) {
112 case GPIO_PULL_UP:
113 val = PULL_UP_1V8;
114 break;
115 case GPIO_PULL_DOWN:
116 val = PULL_DOWN_1V8;
117 break;
118 case GPIO_PULL_NORMAL:
119 default:
120 val = PULL_NONE_1V8;
121 break;
122 }
123 clrsetbits_le32(regs, 3 << (gpio * 2), val << (gpio * 2));
124
125 return 0;
126}
127
128int spl_gpio_output(void *vregs, uint gpio, int value)
129{
130 struct rockchip_gpio_regs * const regs = vregs;
131
132 clrsetbits_le32(&regs->swport_dr, 1 << gpio, value << gpio);
133
134 /* Set direction */
135 clrsetbits_le32(&regs->swport_ddr, 1 << gpio, 1 << gpio);
136
137 return 0;
138}
139#endif /* CONFIG_SPL_BUILD */
140
Simon Glass1f8f7732015-08-30 16:55:27 -0600141static int rockchip_gpio_probe(struct udevice *dev)
142{
143 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
144 struct rockchip_gpio_priv *priv = dev_get_priv(dev);
145 char *end;
Simon Glass48647822016-01-21 19:44:09 -0700146 int ret;
Simon Glass1f8f7732015-08-30 16:55:27 -0600147
Philipp Tomsicha1d34802017-09-11 22:04:24 +0200148 priv->regs = dev_read_addr_ptr(dev);
Simon Glass3f603cb2016-02-11 13:23:26 -0700149 ret = uclass_first_device_err(UCLASS_PINCTRL, &priv->pinctrl);
Simon Glass48647822016-01-21 19:44:09 -0700150 if (ret)
151 return ret;
Simon Glass48647822016-01-21 19:44:09 -0700152
Simon Glass1f8f7732015-08-30 16:55:27 -0600153 uc_priv->gpio_count = ROCKCHIP_GPIOS_PER_BANK;
154 end = strrchr(dev->name, '@');
Simon Glass48647822016-01-21 19:44:09 -0700155 priv->bank = trailing_strtoln(dev->name, end);
156 priv->name[0] = 'A' + priv->bank;
Simon Glass1f8f7732015-08-30 16:55:27 -0600157 uc_priv->bank_name = priv->name;
158
159 return 0;
160}
161
162static const struct dm_gpio_ops gpio_rockchip_ops = {
163 .direction_input = rockchip_gpio_direction_input,
164 .direction_output = rockchip_gpio_direction_output,
165 .get_value = rockchip_gpio_get_value,
166 .set_value = rockchip_gpio_set_value,
167 .get_function = rockchip_gpio_get_function,
Simon Glass1f8f7732015-08-30 16:55:27 -0600168};
169
170static const struct udevice_id rockchip_gpio_ids[] = {
171 { .compatible = "rockchip,gpio-bank" },
172 { }
173};
174
Walter Lozanoe3e24702020-06-25 01:10:04 -0300175U_BOOT_DRIVER(rockchip_gpio_bank) = {
176 .name = "rockchip_gpio_bank",
Simon Glass1f8f7732015-08-30 16:55:27 -0600177 .id = UCLASS_GPIO,
178 .of_match = rockchip_gpio_ids,
179 .ops = &gpio_rockchip_ops,
Simon Glass41575d82020-12-03 16:55:17 -0700180 .priv_auto = sizeof(struct rockchip_gpio_priv),
Simon Glass1f8f7732015-08-30 16:55:27 -0600181 .probe = rockchip_gpio_probe,
182};