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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Sedji Gaouaou22ee6472009-07-09 10:16:29 +02002/*
3 * (C) Copyright 2007-2008
Stelian Popc9e798d2011-11-01 00:00:39 +01004 * Stelian Pop <stelian@popies.net>
Sedji Gaouaou22ee6472009-07-09 10:16:29 +02005 * Lead Tech Design <www.leadtechdesign.com>
6 *
7 * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES).
Sedji Gaouaou22ee6472009-07-09 10:16:29 +02008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000013#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
Jens Scharsig425de622010-02-03 22:45:42 +010014
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020015/* ARM asynchronous clock */
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000016#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
17#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020018
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000019#define CONFIG_AT91SAM9M10G45EK
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020020
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000021#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
22#define CONFIG_SETUP_MEMORY_TAGS
23#define CONFIG_INITRD_TAG
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020024#define CONFIG_SKIP_LOWLEVEL_INIT
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000025
26/* general purpose I/O */
27#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020028
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020029/* LCD */
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020030#define LCD_BPP LCD_COLOR8
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000031#define CONFIG_LCD_LOGO
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020032#undef LCD_TEST_PATTERN
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000033#define CONFIG_LCD_INFO
34#define CONFIG_LCD_INFO_BELOW_LOGO
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000035#define CONFIG_ATMEL_LCD
36#define CONFIG_ATMEL_LCD_RGB565
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020037/* board specific(not enough SRAM) */
38#define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000
39
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020040/*
41 * BOOTP options
42 */
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000043#define CONFIG_BOOTP_BOOTFILESIZE
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020044
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020045/* SDRAM */
Wenyou Yange61ed482017-09-14 11:07:42 +080046#define CONFIG_SYS_SDRAM_BASE 0x70000000
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000047#define CONFIG_SYS_SDRAM_SIZE 0x08000000
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020048
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000049#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou Yang59b37122017-04-18 15:15:48 +080050 (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020051
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020052/* NAND flash */
53#ifdef CONFIG_CMD_NAND
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020054#define CONFIG_SYS_MAX_NAND_DEVICE 1
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000055#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
56#define CONFIG_SYS_NAND_DBW_8
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020057/* our ALE is AD21 */
58#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
59/* our CLE is AD22 */
60#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
61#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
62#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
Wolfgang Denk2eb99ca2009-07-18 21:52:24 +020063
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020064#endif
65
66/* Ethernet */
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000067#define CONFIG_RESET_PHY_R
Heiko Schocher4535a242013-11-18 08:07:23 +010068#define CONFIG_AT91_WANTS_COMMON_PHY
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020069
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000070#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020071
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000072#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
73#define CONFIG_SYS_MEMTEST_END 0x23e00000
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020074
Wenyou Yang55415432017-09-14 11:07:44 +080075#ifdef CONFIG_NAND_BOOT
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000076/* bootstrap + u-boot + env in nandflash */
Nicolas Ferre7b8b19f2018-05-09 10:30:25 +030077#define CONFIG_ENV_OFFSET 0x140000
Bo Shen0c58cfa2013-02-20 00:16:25 +000078#define CONFIG_ENV_OFFSET_REDUND 0x100000
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000079#define CONFIG_ENV_SIZE 0x20000
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020080
Bo Shen0c58cfa2013-02-20 00:16:25 +000081#define CONFIG_BOOTCOMMAND \
82 "nand read 0x70000000 0x200000 0x300000;" \
Thomas Petazzoni5cfeec52011-08-04 11:08:50 +000083 "bootm 0x70000000"
Wenyou Yang55415432017-09-14 11:07:44 +080084#elif CONFIG_SD_BOOT
Wu, Josh9637a1b2014-05-21 10:42:16 +080085/* bootstrap + u-boot + env + linux in mmc */
Wu, Josh9637a1b2014-05-21 10:42:16 +080086#define CONFIG_ENV_SIZE 0x4000
87
Wu, Josh9637a1b2014-05-21 10:42:16 +080088#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x71000000 dtb; " \
89 "fatload mmc 0:1 0x72000000 zImage; " \
90 "bootz 0x72000000 - 0x71000000"
91#endif
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020092
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020093/*
94 * Size of malloc() pool
95 */
96#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
Sedji Gaouaou22ee6472009-07-09 10:16:29 +020097
Bo Shen41d41a92015-03-27 14:23:34 +080098/* Defines for SPL */
Bo Shen41d41a92015-03-27 14:23:34 +080099#define CONFIG_SPL_MAX_SIZE 0x010000
100#define CONFIG_SPL_STACK 0x310000
101
Bo Shen41d41a92015-03-27 14:23:34 +0800102#define CONFIG_SYS_MONITOR_LEN 0x80000
103
Wenyou Yang55415432017-09-14 11:07:44 +0800104#ifdef CONFIG_SD_BOOT
Bo Shen41d41a92015-03-27 14:23:34 +0800105
106#define CONFIG_SPL_BSS_START_ADDR 0x70000000
107#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000
108#define CONFIG_SYS_SPL_MALLOC_START 0x70080000
109#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000
110
Bo Shen41d41a92015-03-27 14:23:34 +0800111#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
112#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Bo Shen41d41a92015-03-27 14:23:34 +0800113
Wenyou Yang55415432017-09-14 11:07:44 +0800114#elif CONFIG_NAND_BOOT
Bo Shen41d41a92015-03-27 14:23:34 +0800115#define CONFIG_SPL_NAND_DRIVERS
116#define CONFIG_SPL_NAND_BASE
117#define CONFIG_SPL_NAND_ECC
118#define CONFIG_SPL_NAND_SOFTECC
119#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
120#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
121#define CONFIG_SYS_NAND_5_ADDR_CYCLE
122
123#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
124#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
125#define CONFIG_SYS_NAND_PAGE_COUNT 64
126#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
127#define CONFIG_SYS_NAND_ECCSIZE 256
128#define CONFIG_SYS_NAND_ECCBYTES 3
129#define CONFIG_SYS_NAND_OOBSIZE 64
130#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
131 48, 49, 50, 51, 52, 53, 54, 55, \
132 56, 57, 58, 59, 60, 61, 62, 63, }
133#endif
134
135#define CONFIG_SPL_ATMEL_SIZE
136#define CONFIG_SYS_MASTER_CLOCK 132096000
137#define CONFIG_SYS_AT91_PLLA 0x20c73f03
138#define CONFIG_SYS_MCKR 0x1301
139#define CONFIG_SYS_MCKR_CSS 0x1302
140
Sedji Gaouaou22ee6472009-07-09 10:16:29 +0200141#endif