blob: cb04710737426121fe203211b755bda849df039e [file] [log] [blame]
Stefan Roesefeaedfc2005-11-15 10:35:59 +01001/*
2 * (C) Copyright 2005
3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25#include <asm/processor.h>
26#include <command.h>
27#include <malloc.h>
28
Wolfgang Denkd87080b2006-03-31 18:32:53 +020029DECLARE_GLOBAL_DATA_PTR;
Stefan Roesefeaedfc2005-11-15 10:35:59 +010030
31extern void lxt971_no_sleep(void);
32
Stefan Roesefeaedfc2005-11-15 10:35:59 +010033/* fpga configuration data - not compressed, generated by bin2c */
34const unsigned char fpgadata[] =
35{
36#include "fpgadata.c"
37};
38int filesize = sizeof(fpgadata);
39
40
41int board_early_init_f (void)
42{
43 /*
44 * IRQ 0-15 405GP internally generated; active high; level sensitive
45 * IRQ 16 405GP internally generated; active low; level sensitive
46 * IRQ 17-24 RESERVED
47 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
48 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
49 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
50 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
51 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
52 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
53 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
54 */
55 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
56 mtdcr(uicer, 0x00000000); /* disable all ints */
57 mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
58 mtdcr(uicpr, 0xFFFFFF80); /* set int polarities */
59 mtdcr(uictr, 0x10000000); /* set int trigger levels */
60 mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
61 mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
62
63 /*
64 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
65 */
66 mtebc (epcr, 0xa8400000); /* ebc always driven */
67
68 /*
69 * Reset CPLD via GPIO12 (CS3) pin
70 */
71 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_PLD_RESET);
72 udelay(1000); /* wait 1ms */
73 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_PLD_RESET);
74 udelay(1000); /* wait 1ms */
75
76 return 0;
77}
78
79
80/* ------------------------------------------------------------------------- */
81
82int misc_init_f (void)
83{
84 return 0; /* dummy implementation */
85}
86
87
88int misc_init_r (void)
89{
Stefan Roesefeaedfc2005-11-15 10:35:59 +010090 /* adjust flash start and offset */
91 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
92 gd->bd->bi_flashoffset = 0;
93
94 /*
95 * Setup and enable EEPROM write protection
96 */
97 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
98
99 /*
100 * Set NAND-FLASH GPIO signals to default
101 */
102 out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
103 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
104
105 return (0);
106}
107
108
109/*
110 * Check Board Identity:
111 */
112
113int checkboard (void)
114{
Stefan Roese18c5e642006-01-18 20:06:44 +0100115 char str[64];
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100116 int flashcnt;
117 int delay;
118 volatile unsigned char *led_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1000);
119 volatile unsigned char *ver_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1001);
120
121 puts ("Board: ");
122
123 if (getenv_r("serial#", str, sizeof(str)) == -1) {
124 puts ("### No HW ID - assuming CMS700");
125 } else {
126 puts(str);
127 }
128
129 printf(" (PLD-Version=%02d)\n", *ver_reg);
130
131 /*
132 * Flash LEDs
133 */
134 for (flashcnt = 0; flashcnt < 3; flashcnt++) {
135 *led_reg = 0x00; /* LEDs off */
136 for (delay = 0; delay < 100; delay++)
137 udelay(1000);
138 *led_reg = 0x0f; /* LEDs on */
139 for (delay = 0; delay < 50; delay++)
140 udelay(1000);
141 }
142 *led_reg = 0x70;
143
144 return 0;
145}
146
147/* ------------------------------------------------------------------------- */
148
149long int initdram (int board_type)
150{
151 unsigned long val;
152
153 mtdcr(memcfga, mem_mb0cf);
154 val = mfdcr(memcfgd);
155
156#if 0
157 printf("\nmb0cf=%x\n", val); /* test-only */
158 printf("strap=%x\n", mfdcr(strap)); /* test-only */
159#endif
160
161 return (4*1024*1024 << ((val & 0x000e0000) >> 17));
162}
163
164/* ------------------------------------------------------------------------- */
165
166#if defined(CFG_EEPROM_WREN)
167/* Input: <dev_addr> I2C address of EEPROM device to enable.
168 * <state> -1: deliver current state
169 * 0: disable write
170 * 1: enable write
171 * Returns: -1: wrong device address
172 * 0: dis-/en- able done
173 * 0/1: current state if <state> was -1.
174 */
175int eeprom_write_enable (unsigned dev_addr, int state)
176{
177 if (CFG_I2C_EEPROM_ADDR != dev_addr) {
178 return -1;
179 } else {
180 switch (state) {
181 case 1:
182 /* Enable write access, clear bit GPIO_SINT2. */
183 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
184 state = 0;
185 break;
186 case 0:
187 /* Disable write access, set bit GPIO_SINT2. */
188 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
189 state = 0;
190 break;
191 default:
192 /* Read current status back. */
193 state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
194 break;
195 }
196 }
197 return state;
198}
199
200int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
201{
202 int query = argc == 1;
203 int state = 0;
204
205 if (query) {
206 /* Query write access state. */
207 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
208 if (state < 0) {
209 puts ("Query of write access state failed.\n");
210 } else {
211 printf ("Write access for device 0x%0x is %sabled.\n",
212 CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
213 state = 0;
214 }
215 } else {
216 if ('0' == argv[1][0]) {
217 /* Disable write access. */
218 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
219 } else {
220 /* Enable write access. */
221 state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
222 }
223 if (state < 0) {
224 puts ("Setup of write access state failed.\n");
225 }
226 }
227
228 return state;
229}
230
231U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
232 "eepwren - Enable / disable / query EEPROM write access\n",
233 NULL);
234#endif /* #if defined(CFG_EEPROM_WREN) */
235
236/* ------------------------------------------------------------------------- */
237
238#if (CONFIG_COMMANDS & CFG_CMD_NAND)
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100239#include <linux/mtd/nand_legacy.h>
Stefan Roesefeaedfc2005-11-15 10:35:59 +0100240extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
241
242void nand_init(void)
243{
244 nand_probe(CFG_NAND_BASE);
245 if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
246 print_size(nand_dev_desc[0].totlen, "\n");
247 }
248}
249#endif
250
251void reset_phy(void)
252{
253#ifdef CONFIG_LXT971_NO_SLEEP
254
255 /*
256 * Disable sleep mode in LXT971
257 */
258 lxt971_no_sleep();
259#endif
260}