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Eran Libertyf046ccd2005-07-28 10:08:46 -05001/*
2 * Copyright 2004 Freescale Semiconductor, Inc.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 *
22 * Change log:
23 *
24 * 20050101: Eran Liberty (liberty@freescale.com)
25 * Initial file creating (porting from 85XX & 8260)
26 */
27
28#include <common.h>
29#include <mpc83xx.h>
30#include <ioports.h>
31
Wolfgang Denkd87080b2006-03-31 18:32:53 +020032DECLARE_GLOBAL_DATA_PTR;
33
Eran Libertyf046ccd2005-07-28 10:08:46 -050034/*
35 * Breathe some life into the CPU...
36 *
37 * Set up the memory map,
38 * initialize a bunch of registers,
39 * initialize the UPM's
40 */
41void cpu_init_f (volatile immap_t * im)
42{
Eran Libertyf046ccd2005-07-28 10:08:46 -050043 /* Pointer is writable since we allocated a register for it */
44 gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
45
46 /* Clear initial global data */
47 memset ((void *) gd, 0, sizeof (gd_t));
48
49 /* RSR - Reset Status Register - clear all status (4.6.1.3) */
50 gd->reset_status = im->reset.rsr;
51 im->reset.rsr = ~(RSR_RES);
52
53 /*
54 * RMR - Reset Mode Register
55 * contains checkstop reset enable (4.6.1.4)
56 */
57 im->reset.rmr = (RMR_CSRE & (1<<RMR_CSRE_SHIFT));
58
59 /* LCRR - Clock Ratio Register (10.3.1.16) */
60 im->lbus.lcrr = CFG_LCRR;
61
62 /* Enable Time Base & Decrimenter ( so we will have udelay() )*/
63 im->sysconf.spcr |= SPCR_TBEN;
64
65 /* System General Purpose Register */
Kumar Gala9260a562006-01-11 11:12:57 -060066#ifdef CFG_SICRH
67 im->sysconf.sicrh = CFG_SICRH;
68#endif
69#ifdef CFG_SICRL
70 im->sysconf.sicrl = CFG_SICRL;
71#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -050072
73 /*
74 * Memory Controller:
75 */
76
77 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
78 * addresses - these have to be modified later when FLASH size
79 * has been determined
80 */
81
82#if defined(CFG_BR0_PRELIM) \
83 && defined(CFG_OR0_PRELIM) \
84 && defined(CFG_LBLAWBAR0_PRELIM) \
85 && defined(CFG_LBLAWAR0_PRELIM)
86 im->lbus.bank[0].br = CFG_BR0_PRELIM;
87 im->lbus.bank[0].or = CFG_OR0_PRELIM;
88 im->sysconf.lblaw[0].bar = CFG_LBLAWBAR0_PRELIM;
89 im->sysconf.lblaw[0].ar = CFG_LBLAWAR0_PRELIM;
90#else
91#error CFG_BR0_PRELIM, CFG_OR0_PRELIM, CFG_LBLAWBAR0_PRELIM & CFG_LBLAWAR0_PRELIM must be defined
92#endif
93
Kumar Galac99f3842006-01-25 16:12:46 -060094#if defined(CFG_BR1_PRELIM) && defined(CFG_OR1_PRELIM)
Eran Libertyf046ccd2005-07-28 10:08:46 -050095 im->lbus.bank[1].br = CFG_BR1_PRELIM;
96 im->lbus.bank[1].or = CFG_OR1_PRELIM;
Kumar Galac99f3842006-01-25 16:12:46 -060097#endif
98#if defined(CFG_LBLAWBAR1_PRELIM) && defined(CFG_LBLAWAR1_PRELIM)
Eran Libertyf046ccd2005-07-28 10:08:46 -050099 im->sysconf.lblaw[1].bar = CFG_LBLAWBAR1_PRELIM;
100 im->sysconf.lblaw[1].ar = CFG_LBLAWAR1_PRELIM;
101#endif
Kumar Galac99f3842006-01-25 16:12:46 -0600102#if defined(CFG_BR2_PRELIM) && defined(CFG_OR2_PRELIM)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500103 im->lbus.bank[2].br = CFG_BR2_PRELIM;
104 im->lbus.bank[2].or = CFG_OR2_PRELIM;
Kumar Galac99f3842006-01-25 16:12:46 -0600105#endif
106#if defined(CFG_LBLAWBAR2_PRELIM) && defined(CFG_LBLAWAR2_PRELIM)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500107 im->sysconf.lblaw[2].bar = CFG_LBLAWBAR2_PRELIM;
108 im->sysconf.lblaw[2].ar = CFG_LBLAWAR2_PRELIM;
109#endif
Kumar Galac99f3842006-01-25 16:12:46 -0600110#if defined(CFG_BR3_PRELIM) && defined(CFG_OR3_PRELIM)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500111 im->lbus.bank[3].br = CFG_BR3_PRELIM;
112 im->lbus.bank[3].or = CFG_OR3_PRELIM;
Kumar Galac99f3842006-01-25 16:12:46 -0600113#endif
114#if defined(CFG_LBLAWBAR3_PRELIM) && defined(CFG_LBLAWAR3_PRELIM)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500115 im->sysconf.lblaw[3].bar = CFG_LBLAWBAR3_PRELIM;
116 im->sysconf.lblaw[3].ar = CFG_LBLAWAR3_PRELIM;
117#endif
Kumar Galac99f3842006-01-25 16:12:46 -0600118#if defined(CFG_BR4_PRELIM) && defined(CFG_OR4_PRELIM)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500119 im->lbus.bank[4].br = CFG_BR4_PRELIM;
120 im->lbus.bank[4].or = CFG_OR4_PRELIM;
Kumar Galac99f3842006-01-25 16:12:46 -0600121#endif
122#if defined(CFG_LBLAWBAR4_PRELIM) && defined(CFG_LBLAWAR4_PRELIM)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500123 im->sysconf.lblaw[4].bar = CFG_LBLAWBAR4_PRELIM;
124 im->sysconf.lblaw[4].ar = CFG_LBLAWAR4_PRELIM;
125#endif
Kumar Galac99f3842006-01-25 16:12:46 -0600126#if defined(CFG_BR5_PRELIM) && defined(CFG_OR5_PRELIM)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500127 im->lbus.bank[5].br = CFG_BR5_PRELIM;
128 im->lbus.bank[5].or = CFG_OR5_PRELIM;
Kumar Galac99f3842006-01-25 16:12:46 -0600129#endif
130#if defined(CFG_LBLAWBAR5_PRELIM) && defined(CFG_LBLAWAR5_PRELIM)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500131 im->sysconf.lblaw[5].bar = CFG_LBLAWBAR5_PRELIM;
132 im->sysconf.lblaw[5].ar = CFG_LBLAWAR5_PRELIM;
133#endif
Kumar Galac99f3842006-01-25 16:12:46 -0600134#if defined(CFG_BR6_PRELIM) && defined(CFG_OR6_PRELIM)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500135 im->lbus.bank[6].br = CFG_BR6_PRELIM;
136 im->lbus.bank[6].or = CFG_OR6_PRELIM;
Kumar Galac99f3842006-01-25 16:12:46 -0600137#endif
138#if defined(CFG_LBLAWBAR6_PRELIM) && defined(CFG_LBLAWAR6_PRELIM)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500139 im->sysconf.lblaw[6].bar = CFG_LBLAWBAR6_PRELIM;
140 im->sysconf.lblaw[6].ar = CFG_LBLAWAR6_PRELIM;
141#endif
Kumar Galac99f3842006-01-25 16:12:46 -0600142#if defined(CFG_BR7_PRELIM) && defined(CFG_OR7_PRELIM)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500143 im->lbus.bank[7].br = CFG_BR7_PRELIM;
144 im->lbus.bank[7].or = CFG_OR7_PRELIM;
Kumar Galac99f3842006-01-25 16:12:46 -0600145#endif
146#if defined(CFG_LBLAWBAR7_PRELIM) && defined(CFG_LBLAWAR7_PRELIM)
Eran Libertyf046ccd2005-07-28 10:08:46 -0500147 im->sysconf.lblaw[7].bar = CFG_LBLAWBAR7_PRELIM;
148 im->sysconf.lblaw[7].ar = CFG_LBLAWAR7_PRELIM;
149#endif
Kumar Galaa15b44d2006-01-11 11:21:14 -0600150#ifdef CFG_GPIO1_PRELIM
151 im->pgio[0].dir = CFG_GPIO1_DIR;
152 im->pgio[0].dat = CFG_GPIO1_DAT;
153#endif
154#ifdef CFG_GPIO2_PRELIM
155 im->pgio[1].dir = CFG_GPIO2_DIR;
156 im->pgio[1].dat = CFG_GPIO2_DAT;
157#endif
Eran Libertyf046ccd2005-07-28 10:08:46 -0500158}
159
160
161/*
162 * Initialize higher level parts of CPU like time base and timers.
163 */
164
165int cpu_init_r (void)
166{
167 return 0;
168}