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Dave Liu7737d5c2006-11-03 12:11:15 -06001/*
2 * Copyright (C) 2005 Freescale Semiconductor, Inc.
3 *
4 * Author: Shlomi Gridish <gridish@freescale.com>
5 *
6 * Description: UCC ethernet driver -- PHY handling
Wolfgang Denkdd520bf2006-11-30 18:02:20 +01007 * Driver for UEC on QE
8 * Based on 8260_io/fcc_enet.c
Dave Liu7737d5c2006-11-03 12:11:15 -06009 *
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010010 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
Dave Liu7737d5c2006-11-03 12:11:15 -060012 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16#ifndef __UEC_PHY_H__
17#define __UEC_PHY_H__
18
19#define MII_end ((u32)-2)
20#define MII_read ((u32)-1)
21
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010022#define MIIMIND_BUSY 0x00000001
23#define MIIMIND_NOTVALID 0x00000004
Dave Liu7737d5c2006-11-03 12:11:15 -060024
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010025#define UGETH_AN_TIMEOUT 2000
Dave Liu7737d5c2006-11-03 12:11:15 -060026
27/* 1000BT control (Marvell & BCM54xx at least) */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010028#define MII_1000BASETCONTROL 0x09
Dave Liu7737d5c2006-11-03 12:11:15 -060029#define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200
30#define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100
31
32/* Cicada Extended Control Register 1 */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010033#define MII_CIS8201_EXT_CON1 0x17
Dave Liu7737d5c2006-11-03 12:11:15 -060034#define MII_CIS8201_EXTCON1_INIT 0x0000
35
36/* Cicada Interrupt Mask Register */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010037#define MII_CIS8201_IMASK 0x19
38#define MII_CIS8201_IMASK_IEN 0x8000
39#define MII_CIS8201_IMASK_SPEED 0x4000
40#define MII_CIS8201_IMASK_LINK 0x2000
Dave Liu7737d5c2006-11-03 12:11:15 -060041#define MII_CIS8201_IMASK_DUPLEX 0x1000
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010042#define MII_CIS8201_IMASK_MASK 0xf000
Dave Liu7737d5c2006-11-03 12:11:15 -060043
44/* Cicada Interrupt Status Register */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010045#define MII_CIS8201_ISTAT 0x1a
Dave Liu7737d5c2006-11-03 12:11:15 -060046#define MII_CIS8201_ISTAT_STATUS 0x8000
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010047#define MII_CIS8201_ISTAT_SPEED 0x4000
48#define MII_CIS8201_ISTAT_LINK 0x2000
Dave Liu7737d5c2006-11-03 12:11:15 -060049#define MII_CIS8201_ISTAT_DUPLEX 0x1000
50
51/* Cicada Auxiliary Control/Status Register */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010052#define MII_CIS8201_AUX_CONSTAT 0x1c
Dave Liu7737d5c2006-11-03 12:11:15 -060053#define MII_CIS8201_AUXCONSTAT_INIT 0x0004
54#define MII_CIS8201_AUXCONSTAT_DUPLEX 0x0020
55#define MII_CIS8201_AUXCONSTAT_SPEED 0x0018
56#define MII_CIS8201_AUXCONSTAT_GBIT 0x0010
57#define MII_CIS8201_AUXCONSTAT_100 0x0008
58
59/* 88E1011 PHY Status Register */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010060#define MII_M1011_PHY_SPEC_STATUS 0x11
61#define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
62#define MII_M1011_PHY_SPEC_STATUS_100 0x4000
63#define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
64#define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
65#define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
66#define MII_M1011_PHY_SPEC_STATUS_LINK 0x0400
Dave Liu7737d5c2006-11-03 12:11:15 -060067
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010068#define MII_M1011_IEVENT 0x13
69#define MII_M1011_IEVENT_CLEAR 0x0000
Dave Liu7737d5c2006-11-03 12:11:15 -060070
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010071#define MII_M1011_IMASK 0x12
72#define MII_M1011_IMASK_INIT 0x6400
73#define MII_M1011_IMASK_CLEAR 0x0000
Dave Liu7737d5c2006-11-03 12:11:15 -060074
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010075#define MII_DM9161_SCR 0x10
76#define MII_DM9161_SCR_INIT 0x0610
Dave Liu7737d5c2006-11-03 12:11:15 -060077#define MII_DM9161_SCR_RMII_INIT 0x0710
78
79/* DM9161 Specified Configuration and Status Register */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010080#define MII_DM9161_SCSR 0x11
81#define MII_DM9161_SCSR_100F 0x8000
82#define MII_DM9161_SCSR_100H 0x4000
83#define MII_DM9161_SCSR_10F 0x2000
84#define MII_DM9161_SCSR_10H 0x1000
Dave Liu7737d5c2006-11-03 12:11:15 -060085
86/* DM9161 Interrupt Register */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010087#define MII_DM9161_INTR 0x15
88#define MII_DM9161_INTR_PEND 0x8000
89#define MII_DM9161_INTR_DPLX_MASK 0x0800
90#define MII_DM9161_INTR_SPD_MASK 0x0400
91#define MII_DM9161_INTR_LINK_MASK 0x0200
92#define MII_DM9161_INTR_MASK 0x0100
93#define MII_DM9161_INTR_DPLX_CHANGE 0x0010
94#define MII_DM9161_INTR_SPD_CHANGE 0x0008
95#define MII_DM9161_INTR_LINK_CHANGE 0x0004
96#define MII_DM9161_INTR_INIT 0x0000
97#define MII_DM9161_INTR_STOP \
Dave Liu7737d5c2006-11-03 12:11:15 -060098(MII_DM9161_INTR_DPLX_MASK | MII_DM9161_INTR_SPD_MASK \
99 | MII_DM9161_INTR_LINK_MASK | MII_DM9161_INTR_MASK)
100
101/* DM9161 10BT Configuration/Status */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100102#define MII_DM9161_10BTCSR 0x12
103#define MII_DM9161_10BTCSR_INIT 0x7800
Dave Liu7737d5c2006-11-03 12:11:15 -0600104
105#define MII_BASIC_FEATURES (SUPPORTED_10baseT_Half | \
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100106 SUPPORTED_10baseT_Full | \
107 SUPPORTED_100baseT_Half | \
108 SUPPORTED_100baseT_Full | \
109 SUPPORTED_Autoneg | \
110 SUPPORTED_TP | \
111 SUPPORTED_MII)
Dave Liu7737d5c2006-11-03 12:11:15 -0600112
113#define MII_GBIT_FEATURES (MII_BASIC_FEATURES | \
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100114 SUPPORTED_1000baseT_Half | \
115 SUPPORTED_1000baseT_Full)
Dave Liu7737d5c2006-11-03 12:11:15 -0600116
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100117#define MII_READ_COMMAND 0x00000001
Dave Liu7737d5c2006-11-03 12:11:15 -0600118
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100119#define MII_INTERRUPT_DISABLED 0x0
120#define MII_INTERRUPT_ENABLED 0x1
Dave Liu7737d5c2006-11-03 12:11:15 -0600121
122#define SPEED_10 10
123#define SPEED_100 100
124#define SPEED_1000 1000
125
126/* Duplex, half or full. */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100127#define DUPLEX_HALF 0x00
128#define DUPLEX_FULL 0x01
Dave Liu7737d5c2006-11-03 12:11:15 -0600129
130/* Indicates what features are supported by the interface. */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100131#define SUPPORTED_10baseT_Half (1 << 0)
132#define SUPPORTED_10baseT_Full (1 << 1)
133#define SUPPORTED_100baseT_Half (1 << 2)
134#define SUPPORTED_100baseT_Full (1 << 3)
135#define SUPPORTED_1000baseT_Half (1 << 4)
136#define SUPPORTED_1000baseT_Full (1 << 5)
137#define SUPPORTED_Autoneg (1 << 6)
138#define SUPPORTED_TP (1 << 7)
139#define SUPPORTED_AUI (1 << 8)
140#define SUPPORTED_MII (1 << 9)
141#define SUPPORTED_FIBRE (1 << 10)
142#define SUPPORTED_BNC (1 << 11)
143#define SUPPORTED_10000baseT_Full (1 << 12)
Dave Liu7737d5c2006-11-03 12:11:15 -0600144
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100145#define ADVERTISED_10baseT_Half (1 << 0)
146#define ADVERTISED_10baseT_Full (1 << 1)
147#define ADVERTISED_100baseT_Half (1 << 2)
148#define ADVERTISED_100baseT_Full (1 << 3)
149#define ADVERTISED_1000baseT_Half (1 << 4)
150#define ADVERTISED_1000baseT_Full (1 << 5)
151#define ADVERTISED_Autoneg (1 << 6)
152#define ADVERTISED_TP (1 << 7)
153#define ADVERTISED_AUI (1 << 8)
154#define ADVERTISED_MII (1 << 9)
155#define ADVERTISED_FIBRE (1 << 10)
156#define ADVERTISED_BNC (1 << 11)
157#define ADVERTISED_10000baseT_Full (1 << 12)
Dave Liu7737d5c2006-11-03 12:11:15 -0600158
159/* Advertisement control register. */
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100160#define ADVERTISE_SLCT 0x001f /* Selector bits */
161#define ADVERTISE_CSMA 0x0001 /* Only selector supported */
162#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */
163#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */
164#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */
165#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */
166#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */
167#define ADVERTISE_RESV 0x1c00 /* Unused... */
168#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */
169#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */
170#define ADVERTISE_NPAGE 0x8000 /* Next page bit */
Dave Liu7737d5c2006-11-03 12:11:15 -0600171
172#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100173 ADVERTISE_CSMA)
Dave Liu7737d5c2006-11-03 12:11:15 -0600174#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100175 ADVERTISE_100HALF | ADVERTISE_100FULL)
Dave Liu7737d5c2006-11-03 12:11:15 -0600176
177/* Taken from mii_if_info and sungem_phy.h */
178struct uec_mii_info {
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100179 /* Information about the PHY type */
180 /* And management functions */
181 struct phy_info *phyinfo;
Dave Liu7737d5c2006-11-03 12:11:15 -0600182
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100183 struct eth_device *dev;
Dave Liu7737d5c2006-11-03 12:11:15 -0600184
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100185 /* forced speed & duplex (no autoneg)
186 * partner speed & duplex & pause (autoneg)
187 */
188 int speed;
189 int duplex;
190 int pause;
Dave Liu7737d5c2006-11-03 12:11:15 -0600191
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100192 /* The most recently read link state */
193 int link;
Dave Liu7737d5c2006-11-03 12:11:15 -0600194
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100195 /* Enabled Interrupts */
196 u32 interrupts;
Dave Liu7737d5c2006-11-03 12:11:15 -0600197
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100198 u32 advertising;
199 int autoneg;
200 int mii_id;
Dave Liu7737d5c2006-11-03 12:11:15 -0600201
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100202 /* private data pointer */
203 /* For use by PHYs to maintain extra state */
204 void *priv;
Dave Liu7737d5c2006-11-03 12:11:15 -0600205
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100206 /* Provided by ethernet driver */
207 int (*mdio_read) (struct eth_device * dev, int mii_id, int reg);
208 void (*mdio_write) (struct eth_device * dev, int mii_id, int reg,
209 int val);
Dave Liu7737d5c2006-11-03 12:11:15 -0600210};
211
212/* struct phy_info: a structure which defines attributes for a PHY
213 *
214 * id will contain a number which represents the PHY. During
215 * startup, the driver will poll the PHY to find out what its
216 * UID--as defined by registers 2 and 3--is. The 32-bit result
217 * gotten from the PHY will be ANDed with phy_id_mask to
218 * discard any bits which may change based on revision numbers
219 * unimportant to functionality
220 *
221 * There are 6 commands which take a ugeth_mii_info structure.
222 * Each PHY must declare config_aneg, and read_status.
223 */
224struct phy_info {
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100225 u32 phy_id;
226 char *name;
227 unsigned int phy_id_mask;
228 u32 features;
Dave Liu7737d5c2006-11-03 12:11:15 -0600229
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100230 /* Called to initialize the PHY */
231 int (*init) (struct uec_mii_info * mii_info);
Dave Liu7737d5c2006-11-03 12:11:15 -0600232
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100233 /* Called to suspend the PHY for power */
234 int (*suspend) (struct uec_mii_info * mii_info);
Dave Liu7737d5c2006-11-03 12:11:15 -0600235
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100236 /* Reconfigures autonegotiation (or disables it) */
237 int (*config_aneg) (struct uec_mii_info * mii_info);
Dave Liu7737d5c2006-11-03 12:11:15 -0600238
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100239 /* Determines the negotiated speed and duplex */
240 int (*read_status) (struct uec_mii_info * mii_info);
Dave Liu7737d5c2006-11-03 12:11:15 -0600241
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100242 /* Clears any pending interrupts */
243 int (*ack_interrupt) (struct uec_mii_info * mii_info);
Dave Liu7737d5c2006-11-03 12:11:15 -0600244
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100245 /* Enables or disables interrupts */
246 int (*config_intr) (struct uec_mii_info * mii_info);
Dave Liu7737d5c2006-11-03 12:11:15 -0600247
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100248 /* Clears up any memory if needed */
249 void (*close) (struct uec_mii_info * mii_info);
Dave Liu7737d5c2006-11-03 12:11:15 -0600250};
251
Wolfgang Denkdd520bf2006-11-30 18:02:20 +0100252struct phy_info *get_phy_info (struct uec_mii_info *mii_info);
253void write_phy_reg (struct eth_device *dev, int mii_id, int regnum,
254 int value);
255int read_phy_reg (struct eth_device *dev, int mii_id, int regnum);
256void mii_clear_phy_interrupt (struct uec_mii_info *mii_info);
257void mii_configure_phy_interrupt (struct uec_mii_info *mii_info,
258 u32 interrupts);
Dave Liu7737d5c2006-11-03 12:11:15 -0600259#endif /* __UEC_PHY_H__ */