| Martyn Welch | c8f3402 | 2022-10-25 10:55:02 +0100 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_IMX8M=y |
| 3 | CONFIG_TEXT_BASE=0x40200000 |
| 4 | CONFIG_SYS_MALLOC_LEN=0x2000000 |
| 5 | CONFIG_SPL_GPIO=y |
| 6 | CONFIG_SPL_LIBCOMMON_SUPPORT=y |
| 7 | CONFIG_SPL_LIBGENERIC_SUPPORT=y |
| 8 | CONFIG_ENV_SIZE=0x1000 |
| 9 | CONFIG_DM_GPIO=y |
| 10 | CONFIG_DEFAULT_DEVICE_TREE="imx8mp-msc-sm2s" |
| 11 | CONFIG_SPL_TEXT_BASE=0x920000 |
| 12 | CONFIG_TARGET_MSC_SM2S_IMX8MP=y |
| Tom Rini | c90e189 | 2023-05-29 10:43:26 -0400 | [diff] [blame] | 13 | CONFIG_SYS_MONITOR_LEN=524288 |
| Martyn Welch | c8f3402 | 2022-10-25 10:55:02 +0100 | [diff] [blame] | 14 | CONFIG_SPL_MMC=y |
| 15 | CONFIG_SPL_SERIAL=y |
| 16 | CONFIG_SPL_DRIVERS_MISC=y |
| Tom Rini | fcb5117 | 2023-02-17 09:58:06 -0500 | [diff] [blame] | 17 | CONFIG_SPL_STACK=0x960000 |
| Martyn Welch | c8f3402 | 2022-10-25 10:55:02 +0100 | [diff] [blame] | 18 | CONFIG_SPL=y |
| 19 | CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 |
| 20 | CONFIG_SYS_LOAD_ADDR=0x40480000 |
| Martyn Welch | c8f3402 | 2022-10-25 10:55:02 +0100 | [diff] [blame] | 21 | CONFIG_SYS_BOOT_GET_CMDLINE=y |
| 22 | CONFIG_SYS_BARGSIZE=2048 |
| Martyn Welch | c8f3402 | 2022-10-25 10:55:02 +0100 | [diff] [blame] | 23 | CONFIG_FIT=y |
| 24 | CONFIG_FIT_EXTERNAL_OFFSET=0x3000 |
| 25 | CONFIG_SPL_LOAD_FIT=y |
| Tom Rini | c358af8 | 2023-03-27 13:39:17 -0400 | [diff] [blame] | 26 | CONFIG_DISTRO_DEFAULTS=y |
| Tom Rini | ec6f06b | 2023-10-02 13:58:20 -0400 | [diff] [blame] | 27 | CONFIG_OF_SYSTEM_SETUP=y |
| Martyn Welch | c8f3402 | 2022-10-25 10:55:02 +0100 | [diff] [blame] | 28 | CONFIG_DEFAULT_FDT_FILE="imx8mp-msc-sm2s.dtb" |
| 29 | CONFIG_SPL_MAX_SIZE=0x26000 |
| 30 | CONFIG_SPL_HAS_BSS_LINKER_SECTION=y |
| 31 | CONFIG_SPL_BSS_START_ADDR=0x0098FC00 |
| 32 | CONFIG_SPL_BSS_MAX_SIZE=0x400 |
| 33 | CONFIG_SPL_BOARD_INIT=y |
| 34 | CONFIG_SPL_BOOTROM_SUPPORT=y |
| 35 | CONFIG_SPL_SYS_MALLOC_SIMPLE=y |
| 36 | # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set |
| Simon Glass | 82e26e0 | 2023-09-26 08:14:16 -0600 | [diff] [blame] | 37 | CONFIG_SPL_SYS_MALLOC=y |
| 38 | CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y |
| 39 | CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x42200000 |
| 40 | CONFIG_SPL_SYS_MALLOC_SIZE=0x80000 |
| Martyn Welch | c8f3402 | 2022-10-25 10:55:02 +0100 | [diff] [blame] | 41 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y |
| 42 | CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300 |
| 43 | CONFIG_SPL_I2C=y |
| 44 | CONFIG_SPL_POWER=y |
| 45 | CONFIG_SPL_WATCHDOG=y |
| Tom Rini | ba6d575 | 2023-10-02 10:35:27 -0400 | [diff] [blame] | 46 | CONFIG_SYS_PROMPT="u-boot=> " |
| Martyn Welch | c8f3402 | 2022-10-25 10:55:02 +0100 | [diff] [blame] | 47 | CONFIG_SYS_MAXARGS=64 |
| 48 | CONFIG_SYS_CBSIZE=2048 |
| 49 | CONFIG_SYS_PBSIZE=2074 |
| 50 | CONFIG_SYS_BOOTM_LEN=0x2000000 |
| 51 | # CONFIG_CMD_EXPORTENV is not set |
| 52 | # CONFIG_CMD_IMPORTENV is not set |
| 53 | # CONFIG_CMD_CRC32 is not set |
| 54 | CONFIG_CMD_CLK=y |
| 55 | CONFIG_CMD_FUSE=y |
| 56 | CONFIG_CMD_GPIO=y |
| 57 | CONFIG_CMD_I2C=y |
| 58 | CONFIG_CMD_MMC=y |
| 59 | CONFIG_CMD_CACHE=y |
| 60 | CONFIG_CMD_REGULATOR=y |
| 61 | CONFIG_CMD_EXT4_WRITE=y |
| 62 | CONFIG_OF_CONTROL=y |
| Martyn Welch | c8f3402 | 2022-10-25 10:55:02 +0100 | [diff] [blame] | 63 | CONFIG_SPL_OF_CONTROL=y |
| 64 | CONFIG_ENV_OVERWRITE=y |
| 65 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 66 | CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y |
| 67 | CONFIG_USE_ETHPRIME=y |
| 68 | CONFIG_ETHPRIME="eth1" |
| 69 | CONFIG_SPL_DM=y |
| 70 | CONFIG_SPL_CLK_COMPOSITE_CCF=y |
| 71 | CONFIG_CLK_COMPOSITE_CCF=y |
| 72 | CONFIG_SPL_CLK_IMX8MP=y |
| 73 | CONFIG_CLK_IMX8MP=y |
| 74 | CONFIG_MXC_GPIO=y |
| 75 | CONFIG_DM_I2C=y |
| 76 | CONFIG_LED=y |
| 77 | CONFIG_LED_GPIO=y |
| 78 | CONFIG_SUPPORT_EMMC_BOOT=y |
| 79 | CONFIG_MMC_IO_VOLTAGE=y |
| 80 | CONFIG_MMC_UHS_SUPPORT=y |
| 81 | CONFIG_MMC_HS400_ES_SUPPORT=y |
| 82 | CONFIG_MMC_HS400_SUPPORT=y |
| 83 | CONFIG_FSL_USDHC=y |
| 84 | CONFIG_PHY_TI=y |
| Martyn Welch | c8f3402 | 2022-10-25 10:55:02 +0100 | [diff] [blame] | 85 | CONFIG_DM_ETH_PHY=y |
| 86 | CONFIG_PHY_GIGE=y |
| 87 | CONFIG_DWC_ETH_QOS=y |
| 88 | CONFIG_DWC_ETH_QOS_IMX=y |
| 89 | CONFIG_FEC_MXC=y |
| 90 | CONFIG_MII=y |
| 91 | CONFIG_PINCTRL=y |
| 92 | CONFIG_SPL_PINCTRL=y |
| 93 | CONFIG_PINCTRL_IMX8M=y |
| 94 | CONFIG_DM_PMIC=y |
| 95 | CONFIG_PMIC_RN5T567=y |
| 96 | CONFIG_SPL_PMIC_RN5T567=y |
| 97 | CONFIG_DM_REGULATOR=y |
| 98 | CONFIG_DM_REGULATOR_FIXED=y |
| 99 | CONFIG_DM_REGULATOR_GPIO=y |
| 100 | CONFIG_MXC_UART=y |
| 101 | CONFIG_SYSRESET=y |
| 102 | CONFIG_SPL_SYSRESET=y |
| 103 | CONFIG_SYSRESET_PSCI=y |