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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Wolfgang Denkad5bb452007-03-06 18:08:43 +01002/*
3 * (C) Copyright 2002
4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Wolfgang Denkad5bb452007-03-06 18:08:43 +01005 */
6
7#include <common.h>
Simon Glass36bf4462019-11-14 12:57:42 -07008#include <irq_func.h>
Wolfgang Denkad5bb452007-03-06 18:08:43 +01009
10/*
11 * CPU test
12 * Shift instructions: rlwnm
13 *
14 * The test contains a pre-built table of instructions, operands and
15 * expected results. For each table entry, the test will cyclically use
16 * different sets of operand registers and result registers.
17 */
18
Wolfgang Denkad5bb452007-03-06 18:08:43 +010019#include <post.h>
20#include "cpu_asm.h"
21
Tom Rini1e019502022-12-04 10:14:17 -050022#if CFG_POST & CFG_SYS_POST_CPU
Wolfgang Denkad5bb452007-03-06 18:08:43 +010023
24extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
25 ulong op2);
26extern ulong cpu_post_makecr (long v);
27
28static struct cpu_post_rlwnm_s
29{
30 ulong cmd;
31 ulong op1;
32 ulong op2;
33 uchar mb;
34 uchar me;
35 ulong res;
36} cpu_post_rlwnm_table[] =
37{
38 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +020039 OP_RLWNM,
Wolfgang Denkad5bb452007-03-06 18:08:43 +010040 0xffff0000,
41 24,
42 16,
43 23,
44 0x0000ff00
45 },
46};
Mike Frysingerd2397812011-05-10 07:28:35 +000047static unsigned int cpu_post_rlwnm_size = ARRAY_SIZE(cpu_post_rlwnm_table);
Wolfgang Denkad5bb452007-03-06 18:08:43 +010048
49int cpu_post_test_rlwnm (void)
50{
51 int ret = 0;
52 unsigned int i, reg;
53 int flag = disable_interrupts();
54
55 for (i = 0; i < cpu_post_rlwnm_size && ret == 0; i++)
56 {
57 struct cpu_post_rlwnm_s *test = cpu_post_rlwnm_table + i;
58
59 for (reg = 0; reg < 32 && ret == 0; reg++)
60 {
61 unsigned int reg0 = (reg + 0) % 32;
62 unsigned int reg1 = (reg + 1) % 32;
63 unsigned int reg2 = (reg + 2) % 32;
64 unsigned int stk = reg < 16 ? 31 : 15;
Wolfgang Denk53677ef2008-05-20 16:00:29 +020065 unsigned long code[] =
Wolfgang Denkad5bb452007-03-06 18:08:43 +010066 {
67 ASM_STW(stk, 1, -4),
68 ASM_ADDI(stk, 1, -24),
69 ASM_STW(3, stk, 12),
70 ASM_STW(4, stk, 16),
71 ASM_STW(reg0, stk, 8),
72 ASM_STW(reg1, stk, 4),
73 ASM_STW(reg2, stk, 0),
74 ASM_LWZ(reg1, stk, 12),
75 ASM_LWZ(reg0, stk, 16),
76 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me),
77 ASM_STW(reg2, stk, 12),
78 ASM_LWZ(reg2, stk, 0),
79 ASM_LWZ(reg1, stk, 4),
80 ASM_LWZ(reg0, stk, 8),
81 ASM_LWZ(3, stk, 12),
82 ASM_ADDI(1, stk, 24),
83 ASM_LWZ(stk, 1, -4),
84 ASM_BLR,
85 };
Wolfgang Denk53677ef2008-05-20 16:00:29 +020086 unsigned long codecr[] =
Wolfgang Denkad5bb452007-03-06 18:08:43 +010087 {
88 ASM_STW(stk, 1, -4),
89 ASM_ADDI(stk, 1, -24),
90 ASM_STW(3, stk, 12),
91 ASM_STW(4, stk, 16),
92 ASM_STW(reg0, stk, 8),
93 ASM_STW(reg1, stk, 4),
94 ASM_STW(reg2, stk, 0),
95 ASM_LWZ(reg1, stk, 12),
96 ASM_LWZ(reg0, stk, 16),
97 ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me) |
98 BIT_C,
99 ASM_STW(reg2, stk, 12),
100 ASM_LWZ(reg2, stk, 0),
101 ASM_LWZ(reg1, stk, 4),
102 ASM_LWZ(reg0, stk, 8),
103 ASM_LWZ(3, stk, 12),
104 ASM_ADDI(1, stk, 24),
105 ASM_LWZ(stk, 1, -4),
106 ASM_BLR,
107 };
108 ulong res;
109 ulong cr;
110
111 if (ret == 0)
112 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200113 cr = 0;
114 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100115
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200116 ret = res == test->res && cr == 0 ? 0 : -1;
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100117
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200118 if (ret != 0)
119 {
Wolfgang Denk93e14592013-10-04 17:43:24 +0200120 post_log ("Error at rlwnm test %d !\n", i);
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200121 }
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100122 }
123
124 if (ret == 0)
125 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200126 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100127
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200128 ret = res == test->res &&
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100129 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
130
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200131 if (ret != 0)
132 {
Wolfgang Denk93e14592013-10-04 17:43:24 +0200133 post_log ("Error at rlwnm test %d !\n", i);
134 }
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100135 }
136 }
137 }
138
139 if (flag)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200140 enable_interrupts();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100141
142 return ret;
143}
144
145#endif