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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Prafulla Wadaskar91315892009-06-14 22:33:46 +05302/*
3 * (C) Copyright 2009
4 * Marvell Semiconductor <www.marvell.com>
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
6 *
7 * based on - Driver for MV64360X ethernet ports
8 * Copyright (C) 2002 rabeeh@galileo.co.il
Prafulla Wadaskar91315892009-06-14 22:33:46 +05309 */
10
Albert Aribaudd44265a2010-07-12 22:24:28 +020011#ifndef __MVGBE_H__
12#define __MVGBE_H__
Prafulla Wadaskar91315892009-06-14 22:33:46 +053013
Prafulla Wadaskar91315892009-06-14 22:33:46 +053014/* Constants */
15#define INT_CAUSE_UNMASK_ALL 0x0007ffff
16#define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff
17#define MRU_MASK 0xfff1ffff
18#define PHYADR_MASK 0x0000001f
19#define PHYREG_MASK 0x0000001f
20#define QTKNBKT_DEF_VAL 0x3fffffff
21#define QMTBS_DEF_VAL 0x000003ff
22#define QTKNRT_DEF_VAL 0x0000fcff
23#define RXUQ 0 /* Used Rx queue */
24#define TXUQ 0 /* Used Rx queue */
25
Albert Aribaudd44265a2010-07-12 22:24:28 +020026#define MVGBE_REG_WR(adr, val) writel(val, &adr)
27#define MVGBE_REG_RD(adr) readl(&adr)
28#define MVGBE_REG_BITS_RESET(adr, val) writel(readl(&adr) & ~(val), &adr)
29#define MVGBE_REG_BITS_SET(adr, val) writel(readl(&adr) | val, &adr)
Prafulla Wadaskar91315892009-06-14 22:33:46 +053030
31/* Default port configuration value */
32#define PRT_CFG_VAL ( \
Albert Aribaudd44265a2010-07-12 22:24:28 +020033 MVGBE_UCAST_MOD_NRML | \
34 MVGBE_DFLT_RXQ(RXUQ) | \
35 MVGBE_DFLT_RX_ARPQ(RXUQ) | \
36 MVGBE_RX_BC_IF_NOT_IP_OR_ARP | \
37 MVGBE_RX_BC_IF_IP | \
38 MVGBE_RX_BC_IF_ARP | \
39 MVGBE_CPTR_TCP_FRMS_DIS | \
40 MVGBE_CPTR_UDP_FRMS_DIS | \
41 MVGBE_DFLT_RX_TCPQ(RXUQ) | \
42 MVGBE_DFLT_RX_UDPQ(RXUQ) | \
43 MVGBE_DFLT_RX_BPDUQ(RXUQ))
Prafulla Wadaskar91315892009-06-14 22:33:46 +053044
45/* Default port extend configuration value */
46#define PORT_CFG_EXTEND_VALUE \
Albert Aribaudd44265a2010-07-12 22:24:28 +020047 MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL | \
48 MVGBE_PARTITION_DIS | \
49 MVGBE_TX_CRC_GENERATION_EN
Prafulla Wadaskar91315892009-06-14 22:33:46 +053050
Albert Aribaudd44265a2010-07-12 22:24:28 +020051#define GT_MVGBE_IPG_INT_RX(value) ((value & 0x3fff) << 8)
Prafulla Wadaskar91315892009-06-14 22:33:46 +053052
53/* Default sdma control value */
54#define PORT_SDMA_CFG_VALUE ( \
Albert Aribaudd44265a2010-07-12 22:24:28 +020055 MVGBE_RX_BURST_SIZE_16_64BIT | \
56 MVGBE_BLM_RX_NO_SWAP | \
57 MVGBE_BLM_TX_NO_SWAP | \
58 GT_MVGBE_IPG_INT_RX(RXUQ) | \
59 MVGBE_TX_BURST_SIZE_16_64BIT)
Prafulla Wadaskar91315892009-06-14 22:33:46 +053060
61/* Default port serial control value */
Valentin Longchampd3920142011-05-31 02:12:51 +000062#ifndef PORT_SERIAL_CONTROL_VALUE
Prafulla Wadaskar91315892009-06-14 22:33:46 +053063#define PORT_SERIAL_CONTROL_VALUE ( \
Albert Aribaudd44265a2010-07-12 22:24:28 +020064 MVGBE_FORCE_LINK_PASS | \
65 MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
66 MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
67 MVGBE_ADV_NO_FLOW_CTRL | \
68 MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
69 MVGBE_FORCE_BP_MODE_NO_JAM | \
Prafulla Wadaskar91315892009-06-14 22:33:46 +053070 (1 << 9) /* Reserved bit has to be 1 */ | \
Albert Aribaudd44265a2010-07-12 22:24:28 +020071 MVGBE_DO_NOT_FORCE_LINK_FAIL | \
72 MVGBE_EN_AUTO_NEG_SPEED_GMII | \
73 MVGBE_DTE_ADV_0 | \
74 MVGBE_MIIPHY_MAC_MODE | \
75 MVGBE_AUTO_NEG_NO_CHANGE | \
76 MVGBE_MAX_RX_PACKET_1552BYTE | \
77 MVGBE_CLR_EXT_LOOPBACK | \
78 MVGBE_SET_FULL_DUPLEX_MODE | \
79 MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX)
Valentin Longchampd3920142011-05-31 02:12:51 +000080#endif
Prafulla Wadaskar91315892009-06-14 22:33:46 +053081
82/* Tx WRR confoguration macros */
83#define PORT_MAX_TRAN_UNIT 0x24 /* MTU register (default) 9KByte */
84#define PORT_MAX_TOKEN_BUCKET_SIZE 0x_FFFF /* PMTBS reg (default) */
85#define PORT_TOKEN_RATE 1023 /* PTTBRC reg (default) */
86/* MAC accepet/reject macros */
87#define ACCEPT_MAC_ADDR 0
88#define REJECT_MAC_ADDR 1
89/* Size of a Tx/Rx descriptor used in chain list data structure */
Albert Aribaudd44265a2010-07-12 22:24:28 +020090#define MV_RXQ_DESC_ALIGNED_SIZE \
91 (((sizeof(struct mvgbe_rxdesc) / PKTALIGN) + 1) * PKTALIGN)
Prafulla Wadaskar91315892009-06-14 22:33:46 +053092/* Buffer offset from buffer pointer */
93#define RX_BUF_OFFSET 0x2
94
95/* Port serial status reg (PSR) */
Albert Aribaudd44265a2010-07-12 22:24:28 +020096#define MVGBE_INTERFACE_GMII_MII 0
97#define MVGBE_INTERFACE_PCM 1
98#define MVGBE_LINK_IS_DOWN 0
99#define MVGBE_LINK_IS_UP (1 << 1)
100#define MVGBE_PORT_AT_HALF_DUPLEX 0
101#define MVGBE_PORT_AT_FULL_DUPLEX (1 << 2)
102#define MVGBE_RX_FLOW_CTRL_DISD 0
103#define MVGBE_RX_FLOW_CTRL_ENBALED (1 << 3)
104#define MVGBE_GMII_SPEED_100_10 0
105#define MVGBE_GMII_SPEED_1000 (1 << 4)
106#define MVGBE_MII_SPEED_10 0
107#define MVGBE_MII_SPEED_100 (1 << 5)
108#define MVGBE_NO_TX 0
109#define MVGBE_TX_IN_PROGRESS (1 << 7)
110#define MVGBE_BYPASS_NO_ACTIVE 0
111#define MVGBE_BYPASS_ACTIVE (1 << 8)
112#define MVGBE_PORT_NOT_AT_PARTN_STT 0
113#define MVGBE_PORT_AT_PARTN_STT (1 << 9)
114#define MVGBE_PORT_TX_FIFO_NOT_EMPTY 0
115#define MVGBE_PORT_TX_FIFO_EMPTY (1 << 10)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530116
117/* These macros describes the Port configuration reg (Px_cR) bits */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200118#define MVGBE_UCAST_MOD_NRML 0
119#define MVGBE_UNICAST_PROMISCUOUS_MODE 1
120#define MVGBE_DFLT_RXQ(_x) (_x << 1)
121#define MVGBE_DFLT_RX_ARPQ(_x) (_x << 4)
122#define MVGBE_RX_BC_IF_NOT_IP_OR_ARP 0
123#define MVGBE_REJECT_BC_IF_NOT_IP_OR_ARP (1 << 7)
124#define MVGBE_RX_BC_IF_IP 0
125#define MVGBE_REJECT_BC_IF_IP (1 << 8)
126#define MVGBE_RX_BC_IF_ARP 0
127#define MVGBE_REJECT_BC_IF_ARP (1 << 9)
128#define MVGBE_TX_AM_NO_UPDATE_ERR_SMRY (1 << 12)
129#define MVGBE_CPTR_TCP_FRMS_DIS 0
130#define MVGBE_CPTR_TCP_FRMS_EN (1 << 14)
131#define MVGBE_CPTR_UDP_FRMS_DIS 0
132#define MVGBE_CPTR_UDP_FRMS_EN (1 << 15)
133#define MVGBE_DFLT_RX_TCPQ(_x) (_x << 16)
134#define MVGBE_DFLT_RX_UDPQ(_x) (_x << 19)
135#define MVGBE_DFLT_RX_BPDUQ(_x) (_x << 22)
136#define MVGBE_DFLT_RX_TCP_CHKSUM_MODE (1 << 25)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530137
138/* These macros describes the Port configuration extend reg (Px_cXR) bits*/
Albert Aribaudd44265a2010-07-12 22:24:28 +0200139#define MVGBE_CLASSIFY_EN 1
140#define MVGBE_SPAN_BPDU_PACKETS_AS_NORMAL 0
141#define MVGBE_SPAN_BPDU_PACKETS_TO_RX_Q7 (1 << 1)
142#define MVGBE_PARTITION_DIS 0
143#define MVGBE_PARTITION_EN (1 << 2)
144#define MVGBE_TX_CRC_GENERATION_EN 0
145#define MVGBE_TX_CRC_GENERATION_DIS (1 << 3)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530146
147/* These macros describes the Port Sdma configuration reg (SDCR) bits */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200148#define MVGBE_RIFB 1
149#define MVGBE_RX_BURST_SIZE_1_64BIT 0
150#define MVGBE_RX_BURST_SIZE_2_64BIT (1 << 1)
151#define MVGBE_RX_BURST_SIZE_4_64BIT (1 << 2)
152#define MVGBE_RX_BURST_SIZE_8_64BIT ((1 << 2) | (1 << 1))
153#define MVGBE_RX_BURST_SIZE_16_64BIT (1 << 3)
154#define MVGBE_BLM_RX_NO_SWAP (1 << 4)
155#define MVGBE_BLM_RX_BYTE_SWAP 0
156#define MVGBE_BLM_TX_NO_SWAP (1 << 5)
157#define MVGBE_BLM_TX_BYTE_SWAP 0
158#define MVGBE_DESCRIPTORS_BYTE_SWAP (1 << 6)
159#define MVGBE_DESCRIPTORS_NO_SWAP 0
160#define MVGBE_TX_BURST_SIZE_1_64BIT 0
161#define MVGBE_TX_BURST_SIZE_2_64BIT (1 << 22)
162#define MVGBE_TX_BURST_SIZE_4_64BIT (1 << 23)
163#define MVGBE_TX_BURST_SIZE_8_64BIT ((1 << 23) | (1 << 22))
164#define MVGBE_TX_BURST_SIZE_16_64BIT (1 << 24)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530165
166/* These macros describes the Port serial control reg (PSCR) bits */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200167#define MVGBE_SERIAL_PORT_DIS 0
168#define MVGBE_SERIAL_PORT_EN 1
169#define MVGBE_FORCE_LINK_PASS (1 << 1)
170#define MVGBE_DO_NOT_FORCE_LINK_PASS 0
171#define MVGBE_EN_AUTO_NEG_FOR_DUPLX 0
172#define MVGBE_DIS_AUTO_NEG_FOR_DUPLX (1 << 2)
173#define MVGBE_EN_AUTO_NEG_FOR_FLOW_CTRL 0
174#define MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
175#define MVGBE_ADV_NO_FLOW_CTRL 0
176#define MVGBE_ADV_SYMMETRIC_FLOW_CTRL (1 << 4)
177#define MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
178#define MVGBE_FORCE_FC_MODE_TX_PAUSE_DIS (1 << 5)
179#define MVGBE_FORCE_BP_MODE_NO_JAM 0
180#define MVGBE_FORCE_BP_MODE_JAM_TX (1 << 7)
181#define MVGBE_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1 << 8)
182#define MVGBE_FORCE_LINK_FAIL 0
183#define MVGBE_DO_NOT_FORCE_LINK_FAIL (1 << 10)
184#define MVGBE_DIS_AUTO_NEG_SPEED_GMII (1 << 13)
185#define MVGBE_EN_AUTO_NEG_SPEED_GMII 0
186#define MVGBE_DTE_ADV_0 0
187#define MVGBE_DTE_ADV_1 (1 << 14)
188#define MVGBE_MIIPHY_MAC_MODE 0
189#define MVGBE_MIIPHY_PHY_MODE (1 << 15)
190#define MVGBE_AUTO_NEG_NO_CHANGE 0
191#define MVGBE_RESTART_AUTO_NEG (1 << 16)
192#define MVGBE_MAX_RX_PACKET_1518BYTE 0
193#define MVGBE_MAX_RX_PACKET_1522BYTE (1 << 17)
194#define MVGBE_MAX_RX_PACKET_1552BYTE (1 << 18)
195#define MVGBE_MAX_RX_PACKET_9022BYTE ((1 << 18) | (1 << 17))
196#define MVGBE_MAX_RX_PACKET_9192BYTE (1 << 19)
197#define MVGBE_MAX_RX_PACKET_9700BYTE ((1 << 19) | (1 << 17))
198#define MVGBE_SET_EXT_LOOPBACK (1 << 20)
199#define MVGBE_CLR_EXT_LOOPBACK 0
200#define MVGBE_SET_FULL_DUPLEX_MODE (1 << 21)
201#define MVGBE_SET_HALF_DUPLEX_MODE 0
202#define MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1 << 22)
203#define MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
204#define MVGBE_SET_GMII_SPEED_TO_10_100 0
205#define MVGBE_SET_GMII_SPEED_TO_1000 (1 << 23)
206#define MVGBE_SET_MII_SPEED_TO_10 0
207#define MVGBE_SET_MII_SPEED_TO_100 (1 << 24)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530208
209/* SMI register fields */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200210#define MVGBE_PHY_SMI_TIMEOUT 10000
Chris Packham5194ed72018-06-09 20:46:16 +1200211#define MVGBE_PHY_SMI_TIMEOUT_MS 1000
Albert Aribaudd44265a2010-07-12 22:24:28 +0200212#define MVGBE_PHY_SMI_DATA_OFFS 0 /* Data */
213#define MVGBE_PHY_SMI_DATA_MASK (0xffff << MVGBE_PHY_SMI_DATA_OFFS)
214#define MVGBE_PHY_SMI_DEV_ADDR_OFFS 16 /* PHY device address */
215#define MVGBE_PHY_SMI_DEV_ADDR_MASK \
216 (PHYADR_MASK << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
217#define MVGBE_SMI_REG_ADDR_OFFS 21 /* PHY device reg addr */
218#define MVGBE_SMI_REG_ADDR_MASK \
219 (PHYADR_MASK << MVGBE_SMI_REG_ADDR_OFFS)
220#define MVGBE_PHY_SMI_OPCODE_OFFS 26 /* Write/Read opcode */
221#define MVGBE_PHY_SMI_OPCODE_MASK (3 << MVGBE_PHY_SMI_OPCODE_OFFS)
222#define MVGBE_PHY_SMI_OPCODE_WRITE (0 << MVGBE_PHY_SMI_OPCODE_OFFS)
223#define MVGBE_PHY_SMI_OPCODE_READ (1 << MVGBE_PHY_SMI_OPCODE_OFFS)
224#define MVGBE_PHY_SMI_READ_VALID_MASK (1 << 27) /* Read Valid */
225#define MVGBE_PHY_SMI_BUSY_MASK (1 << 28) /* Busy */
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530226
227/* SDMA command status fields macros */
228/* Tx & Rx descriptors status */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200229#define MVGBE_ERROR_SUMMARY 1
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530230/* Tx & Rx descriptors command */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200231#define MVGBE_BUFFER_OWNED_BY_DMA (1 << 31)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530232/* Tx descriptors status */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200233#define MVGBE_LC_ERROR 0
234#define MVGBE_UR_ERROR (1 << 1)
235#define MVGBE_RL_ERROR (1 << 2)
236#define MVGBE_LLC_SNAP_FORMAT (1 << 9)
237#define MVGBE_TX_LAST_FRAME (1 << 20)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530238
239/* Rx descriptors status */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200240#define MVGBE_CRC_ERROR 0
241#define MVGBE_OVERRUN_ERROR (1 << 1)
242#define MVGBE_MAX_FRAME_LENGTH_ERROR (1 << 2)
243#define MVGBE_RESOURCE_ERROR ((1 << 2) | (1 << 1))
244#define MVGBE_VLAN_TAGGED (1 << 19)
245#define MVGBE_BPDU_FRAME (1 << 20)
246#define MVGBE_TCP_FRAME_OVER_IP_V_4 0
247#define MVGBE_UDP_FRAME_OVER_IP_V_4 (1 << 21)
248#define MVGBE_OTHER_FRAME_TYPE (1 << 22)
249#define MVGBE_LAYER_2_IS_MVGBE_V_2 (1 << 23)
250#define MVGBE_FRAME_TYPE_IP_V_4 (1 << 24)
251#define MVGBE_FRAME_HEADER_OK (1 << 25)
252#define MVGBE_RX_LAST_DESC (1 << 26)
253#define MVGBE_RX_FIRST_DESC (1 << 27)
254#define MVGBE_UNKNOWN_DESTINATION_ADDR (1 << 28)
255#define MVGBE_RX_EN_INTERRUPT (1 << 29)
256#define MVGBE_LAYER_4_CHECKSUM_OK (1 << 30)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530257
258/* Rx descriptors byte count */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200259#define MVGBE_FRAME_FRAGMENTED (1 << 2)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530260
261/* Tx descriptors command */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200262#define MVGBE_LAYER_4_CHECKSUM_FIRST_DESC (1 << 10)
263#define MVGBE_FRAME_SET_TO_VLAN (1 << 15)
264#define MVGBE_TCP_FRAME 0
265#define MVGBE_UDP_FRAME (1 << 16)
266#define MVGBE_GEN_TCP_UDP_CHECKSUM (1 << 17)
267#define MVGBE_GEN_IP_V_4_CHECKSUM (1 << 18)
268#define MVGBE_ZERO_PADDING (1 << 19)
269#define MVGBE_TX_LAST_DESC (1 << 20)
270#define MVGBE_TX_FIRST_DESC (1 << 21)
271#define MVGBE_GEN_CRC (1 << 22)
272#define MVGBE_TX_EN_INTERRUPT (1 << 23)
273#define MVGBE_AUTO_MODE (1 << 30)
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530274
275/* Address decode parameters */
276/* Ethernet Base Address Register bits */
277#define EBAR_TARGET_DRAM 0x00000000
278#define EBAR_TARGET_DEVICE 0x00000001
279#define EBAR_TARGET_CBS 0x00000002
280#define EBAR_TARGET_PCI0 0x00000003
281#define EBAR_TARGET_PCI1 0x00000004
282#define EBAR_TARGET_CUNIT 0x00000005
283#define EBAR_TARGET_AUNIT 0x00000006
284#define EBAR_TARGET_GUNIT 0x00000007
285
286/* Window attrib */
287#define EBAR_DRAM_CS0 0x00000E00
288#define EBAR_DRAM_CS1 0x00000D00
289#define EBAR_DRAM_CS2 0x00000B00
290#define EBAR_DRAM_CS3 0x00000700
291
292/* DRAM Target interface */
293#define EBAR_DRAM_NO_CACHE_COHERENCY 0x00000000
294#define EBAR_DRAM_CACHE_COHERENCY_WT 0x00001000
295#define EBAR_DRAM_CACHE_COHERENCY_WB 0x00002000
296
297/* Device Bus Target interface */
298#define EBAR_DEVICE_DEVCS0 0x00001E00
299#define EBAR_DEVICE_DEVCS1 0x00001D00
300#define EBAR_DEVICE_DEVCS2 0x00001B00
301#define EBAR_DEVICE_DEVCS3 0x00001700
302#define EBAR_DEVICE_BOOTCS3 0x00000F00
303
304/* PCI Target interface */
305#define EBAR_PCI_BYTE_SWAP 0x00000000
306#define EBAR_PCI_NO_SWAP 0x00000100
307#define EBAR_PCI_BYTE_WORD_SWAP 0x00000200
308#define EBAR_PCI_WORD_SWAP 0x00000300
309#define EBAR_PCI_NO_SNOOP_NOT_ASSERT 0x00000000
310#define EBAR_PCI_NO_SNOOP_ASSERT 0x00000400
311#define EBAR_PCI_IO_SPACE 0x00000000
312#define EBAR_PCI_MEMORY_SPACE 0x00000800
313#define EBAR_PCI_REQ64_FORCE 0x00000000
314#define EBAR_PCI_REQ64_SIZE 0x00001000
315
316/* Window access control */
317#define EWIN_ACCESS_NOT_ALLOWED 0
318#define EWIN_ACCESS_READ_ONLY 1
319#define EWIN_ACCESS_FULL ((1 << 1) | 1)
320
321/* structures represents Controller registers */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200322struct mvgbe_barsz {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530323 u32 bar;
324 u32 size;
325};
326
Albert Aribaudd44265a2010-07-12 22:24:28 +0200327struct mvgbe_rxcdp {
328 struct mvgbe_rxdesc *rxcdp;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530329 u32 rxcdp_pad[3];
330};
331
Albert Aribaudd44265a2010-07-12 22:24:28 +0200332struct mvgbe_tqx {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530333 u32 qxttbc;
334 u32 tqxtbc;
335 u32 tqxac;
336 u32 tqxpad;
337};
338
Albert Aribaudd44265a2010-07-12 22:24:28 +0200339struct mvgbe_registers {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530340 u32 phyadr;
341 u32 smi;
342 u32 euda;
343 u32 eudid;
344 u8 pad1[0x080 - 0x00c - 4];
345 u32 euic;
346 u32 euim;
347 u8 pad2[0x094 - 0x084 - 4];
348 u32 euea;
349 u32 euiae;
350 u8 pad3[0x0b0 - 0x098 - 4];
351 u32 euc;
352 u8 pad3a[0x200 - 0x0b0 - 4];
Albert Aribaudd44265a2010-07-12 22:24:28 +0200353 struct mvgbe_barsz barsz[6];
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530354 u8 pad4[0x280 - 0x22c - 4];
355 u32 ha_remap[4];
356 u32 bare;
357 u32 epap;
358 u8 pad5[0x400 - 0x294 - 4];
359 u32 pxc;
360 u32 pxcx;
361 u32 mii_ser_params;
362 u8 pad6[0x410 - 0x408 - 4];
363 u32 evlane;
364 u32 macal;
365 u32 macah;
366 u32 sdc;
367 u32 dscp[7];
368 u32 psc0;
369 u32 vpt2p;
370 u32 ps0;
371 u32 tqc;
372 u32 psc1;
373 u32 ps1;
374 u32 mrvl_header;
375 u8 pad7[0x460 - 0x454 - 4];
376 u32 ic;
377 u32 ice;
378 u32 pim;
379 u32 peim;
380 u8 pad8[0x474 - 0x46c - 4];
381 u32 pxtfut;
382 u32 pad9;
383 u32 pxmfs;
384 u32 pad10;
385 u32 pxdfc;
386 u32 pxofc;
387 u8 pad11[0x494 - 0x488 - 4];
388 u32 peuiae;
389 u8 pad12[0x4bc - 0x494 - 4];
390 u32 eth_type_prio;
391 u8 pad13[0x4dc - 0x4bc - 4];
392 u32 tqfpc;
393 u32 pttbrc;
394 u32 tqc1;
395 u32 pmtu;
396 u32 pmtbs;
397 u8 pad14[0x60c - 0x4ec - 4];
Albert Aribaudd44265a2010-07-12 22:24:28 +0200398 struct mvgbe_rxcdp rxcdp[7];
399 struct mvgbe_rxdesc *rxcdp7;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530400 u32 rqc;
Albert Aribaudd44265a2010-07-12 22:24:28 +0200401 struct mvgbe_txdesc *tcsdp;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530402 u8 pad15[0x6c0 - 0x684 - 4];
Albert Aribaudd44265a2010-07-12 22:24:28 +0200403 struct mvgbe_txdesc *tcqdp[8];
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530404 u8 pad16[0x700 - 0x6dc - 4];
Albert Aribaudd44265a2010-07-12 22:24:28 +0200405 struct mvgbe_tqx tqx[8];
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530406 u32 pttbc;
407 u8 pad17[0x7a8 - 0x780 - 4];
408 u32 tqxipg0;
409 u32 pad18[3];
410 u32 tqxipg1;
411 u8 pad19[0x7c0 - 0x7b8 - 4];
412 u32 hitkninlopkt;
413 u32 hitkninasyncpkt;
414 u32 lotkninasyncpkt;
415 u32 pad20;
416 u32 ts;
417 u8 pad21[0x3000 - 0x27d0 - 4];
418 u32 pad20_1[32]; /* mib counter registes */
419 u8 pad22[0x3400 - 0x3000 - sizeof(u32) * 32];
420 u32 dfsmt[64];
421 u32 dfomt[64];
422 u32 dfut[4];
423 u8 pad23[0xe20c0 - 0x7360c - 4];
424 u32 pmbus_top_arbiter;
425};
426
427/* structures/enums needed by driver */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200428enum mvgbe_adrwin {
429 MVGBE_WIN0,
430 MVGBE_WIN1,
431 MVGBE_WIN2,
432 MVGBE_WIN3,
433 MVGBE_WIN4,
434 MVGBE_WIN5
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530435};
436
Albert Aribaudd44265a2010-07-12 22:24:28 +0200437enum mvgbe_target {
438 MVGBE_TARGET_DRAM,
439 MVGBE_TARGET_DEV,
440 MVGBE_TARGET_CBS,
441 MVGBE_TARGET_PCI0,
442 MVGBE_TARGET_PCI1
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530443};
444
Albert Aribaudd44265a2010-07-12 22:24:28 +0200445struct mvgbe_winparam {
446 enum mvgbe_adrwin win; /* Window number */
447 enum mvgbe_target target; /* System targets */
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530448 u16 attrib; /* BAR attrib. See above macros */
449 u32 base_addr; /* Window base address in u32 form */
450 u32 high_addr; /* Window high address in u32 form */
451 u32 size; /* Size in MBytes. Must be % 64Kbyte. */
452 int enable; /* Enable/disable access to the window. */
453 u16 access_ctrl; /*Access ctrl register. see above macros */
454};
455
Albert Aribaudd44265a2010-07-12 22:24:28 +0200456struct mvgbe_rxdesc {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530457 u32 cmd_sts; /* Descriptor command status */
458 u16 buf_size; /* Buffer size */
459 u16 byte_cnt; /* Descriptor buffer byte count */
460 u8 *buf_ptr; /* Descriptor buffer pointer */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200461 struct mvgbe_rxdesc *nxtdesc_p; /* Next descriptor pointer */
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530462};
463
Albert Aribaudd44265a2010-07-12 22:24:28 +0200464struct mvgbe_txdesc {
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530465 u32 cmd_sts; /* Descriptor command status */
466 u16 l4i_chk; /* CPU provided TCP Checksum */
467 u16 byte_cnt; /* Descriptor buffer byte count */
468 u8 *buf_ptr; /* Descriptor buffer ptr */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200469 struct mvgbe_txdesc *nxtdesc_p; /* Next descriptor ptr */
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530470};
471
472/* port device data struct */
Albert Aribaudd44265a2010-07-12 22:24:28 +0200473struct mvgbe_device {
Albert Aribaudd44265a2010-07-12 22:24:28 +0200474 struct mvgbe_registers *regs;
475 struct mvgbe_txdesc *p_txdesc;
476 struct mvgbe_rxdesc *p_rxdesc;
477 struct mvgbe_rxdesc *p_rxdesc_curr;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530478 u8 *p_rxbuf;
Simon Kagstrom477fa632009-08-20 10:14:11 +0200479 u8 *p_aligned_txbuf;
Chris Packhamfb731072018-07-09 21:34:00 +1200480
Chris Packhamfb731072018-07-09 21:34:00 +1200481 phy_interface_t phy_interface;
482 unsigned int link;
483 unsigned int duplex;
484 unsigned int speed;
485
486 int init;
487 int phyaddr;
488 struct phy_device *phydev;
489 struct mii_dev *bus;
Prafulla Wadaskar91315892009-06-14 22:33:46 +0530490};
491
Albert Aribaudd44265a2010-07-12 22:24:28 +0200492#endif /* __MVGBE_H__ */